diff options
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_revert_sbe_mcs_setup.C | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 31 |
2 files changed, 37 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_revert_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_revert_sbe_mcs_setup.C index 3d43aad5a..a20ccc28a 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_revert_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_revert_sbe_mcs_setup.C @@ -127,6 +127,11 @@ revert_mc_hb_dcbz_config( fapi2::buffer<uint64_t> l_mcperf1; fapi2::buffer<uint64_t> l_mcfirmask; uint8_t l_mc_pos = 0; + fapi2::ATTR_CHIP_EC_FEATURE_HW414958_Type l_hw414958 = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414958, + i_target, + l_hw414958), + "Error from FAPI_ATTR_GET (fapi2::ATTR_CHIP_EC_FEATURE_HW414958)"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc_target, @@ -166,7 +171,10 @@ revert_mc_hb_dcbz_config( MCS_MCMODE1_DISABLE_SPEC_OP_LEN>(); // We need to set dcbf bit - l_mcmode1.setBit<MCS_MCMODE1_DISABLE_SPEC_OP_DCBF_BIT>(); + if (l_hw414958) + { + l_mcmode1.setBit<MCS_MCMODE1_DISABLE_SPEC_OP_DCBF_BIT>(); + } l_mcmode1.clearBit<MCS_MCMODE1_DISABLE_COMMAND_BYPASS, MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN>(); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 2ff30e080..eeb3c04e7 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2891,7 +2891,7 @@ <id>ATTR_CHIP_EC_FEATURE_HW426891</id> <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> <description> - HW426891 for INT initfile on Coral, Cumulus, and Axone systems for + HW426891 for INT initfile on Coral, Cumulus, and Axone systems for ship mode </description> <chipEcFeature> @@ -3080,7 +3080,7 @@ <id>ATTR_CHIP_EC_FEATURE_DISABLE_64B_STORE</id>> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Nimbus DD1 only: don't set 64B store, dials didn't exist + Nimbus DD1 only: don't set 64B store, dials didn't exist </description> <chipEcFeature> <chip> @@ -3097,7 +3097,7 @@ <id>ATTR_CHIP_EC_FEATURE_DISABLE_TLBIE_PACING</id>> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Nimbus DD1 only: don't set tlbie pacing, dials didn't exist + Nimbus DD1 only: don't set tlbie pacing, dials didn't exist </description> <chipEcFeature> <chip> @@ -7177,4 +7177,29 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW414958</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Disabling speculative dcbf* ttypes. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + </attributes> |
