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-rw-r--r--src/include/usr/hwpf/istepreasoncodes.H1
-rw-r--r--src/usr/hwpf/hwp/dmi_training/dmi_training.C135
-rw-r--r--src/usr/hwpf/hwp/dmi_training/makefile5
-rw-r--r--src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C175
-rw-r--r--src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H74
-rw-r--r--src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml38
-rw-r--r--src/usr/hwpf/makefile3
-rw-r--r--src/usr/targeting/common/xmltohb/attribute_types.xml5
-rw-r--r--src/usr/targeting/common/xmltohb/common.mk3
-rw-r--r--src/usr/targeting/common/xmltohb/vbu.system.xml16
-rw-r--r--[-rwxr-xr-x]src/usr/targeting/xmltohb/TULETA.mrw.xml66
11 files changed, 483 insertions, 38 deletions
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index 658a79a09..39894f4ac 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -102,6 +102,7 @@ enum istepModuleId
ISTEP_PROC_PCIE_SCOMINIT = 0x35,
ISTEP_PROC_PCIE_CONFIG = 0x36,
ISTEP_HOST_MPIPL_SERVICE = 0x37,
+ ISTEP_PROC_CEN_SET_INBAND_ADDR = 0x38,
};
/**
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
index eda3786b6..5645bb71a 100644
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
@@ -66,6 +66,7 @@
#include "proc_cen_framelock.H"
#include "dmi_io_run_training.H"
#include "dmi_scominit.H"
+#include "proc_cen_set_inband_addr.H"
namespace DMI_TRAINING
{
@@ -82,20 +83,20 @@ using namespace fapi;
void* call_dmi_scominit( void *io_pArgs )
{
errlHndl_t l_errl = NULL;
-
IStepError l_StepError;
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_scominit entry" );
- uint8_t l_num = 0;
// Get all functional MCS chiplets
TARGETING::TargetHandleList l_mcsTargetList;
getAllChiplets(l_mcsTargetList, TYPE_MCS);
// Invoke dmi_scominit on each one
- for (l_num = 0; l_num < l_mcsTargetList.size(); l_num++)
+ for (TargetHandleList::iterator l_mcs_iter = l_mcsTargetList.begin();
+ l_mcs_iter != l_mcsTargetList.end();
+ ++l_mcs_iter)
{
- const TARGETING::Target* l_pTarget = l_mcsTargetList[l_num];
+ const TARGETING::Target* l_pTarget = *l_mcs_iter;
const fapi::Target l_fapi_target(
TARGET_TYPE_MCS_CHIPLET,
reinterpret_cast<void *>
@@ -114,10 +115,8 @@ void* call_dmi_scominit( void *io_pArgs )
"ERROR 0x%.8X : dmi_scominit HWP returns error",
l_errl->reasonCode());
- ErrlUserDetailsTarget myDetails(l_pTarget);
-
// capture the target data in the elog
- myDetails.addToLog( l_errl );
+ ErrlUserDetailsTarget(l_pTarget).addToLog( l_errl );
break;
}
@@ -134,9 +133,11 @@ void* call_dmi_scominit( void *io_pArgs )
getAllChips(l_membufTargetList, TYPE_MEMBUF);
// Invoke dmi_scominit on each one
- for (l_num = 0; l_num < l_membufTargetList.size(); l_num++)
+ for (TargetHandleList::iterator l_membuf_iter = l_membufTargetList.begin();
+ l_membuf_iter != l_membufTargetList.end();
+ ++l_membuf_iter)
{
- const TARGETING::Target* l_pTarget = l_membufTargetList[l_num];
+ const TARGETING::Target* l_pTarget = *l_membuf_iter;
const fapi::Target l_fapi_target(
TARGET_TYPE_MEMBUF_CHIP,
reinterpret_cast<void *>
@@ -153,10 +154,8 @@ void* call_dmi_scominit( void *io_pArgs )
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : dmi_scominit HWP returns error",
l_errl->reasonCode());
- ErrlUserDetailsTarget myDetails(l_pTarget);
-
// capture the target data in the elog
- myDetails.addToLog( l_errl );
+ ErrlUserDetailsTarget(l_pTarget).addToLog( l_errl );
break;
}
@@ -257,10 +256,12 @@ void* call_dmi_io_run_training( void *io_pArgs )
TARGETING::TargetHandleList l_cpuTargetList;
getAllChips(l_cpuTargetList, TYPE_PROC);
- for ( size_t i = 0; i < l_cpuTargetList.size(); i++ )
+ for (TargetHandleList::iterator l_cpu_iter = l_cpuTargetList.begin();
+ l_cpu_iter != l_cpuTargetList.end();
+ ++l_cpu_iter)
{
// make a local copy of the CPU target
- const TARGETING::Target* l_cpu_target = l_cpuTargetList[i];
+ const TARGETING::Target* l_cpu_target = *l_cpu_iter;
uint8_t l_cpuNum = l_cpu_target->getAttr<ATTR_POSITION>();
@@ -268,20 +269,27 @@ void* call_dmi_io_run_training( void *io_pArgs )
TARGETING::TargetHandleList l_mcsTargetList;
getChildChiplets( l_mcsTargetList, l_cpu_target, TYPE_MCS );
- for ( size_t j = 0; j < l_mcsTargetList.size(); j++ )
+ for (TargetHandleList::iterator l_mcs_iter = l_mcsTargetList.begin();
+ l_mcs_iter != l_mcsTargetList.end();
+ ++l_mcs_iter)
{
// make a local copy of the MCS target
- const TARGETING::Target* l_mcs_target = l_mcsTargetList[j];
+ const TARGETING::Target* l_mcs_target = *l_mcs_iter;
+
uint8_t l_mcsNum = l_mcs_target->getAttr<ATTR_CHIP_UNIT>();
// find all the Centaurs that are associated with this MCS
TARGETING::TargetHandleList l_memTargetList;
getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF);
- for ( size_t k = 0; k < l_memTargetList.size(); k++ )
+ for (TargetHandleList::iterator l_mem_iter = l_memTargetList.begin();
+ l_mem_iter != l_memTargetList.end();
+ ++l_mem_iter)
{
// make a local copy of the MEMBUF target
- const TARGETING::Target* l_mem_target = l_memTargetList[k];
+ const TARGETING::Target* l_mem_target = *l_mem_iter;
+
+ uint8_t l_memNum = l_mem_target->getAttr<ATTR_POSITION>();
// struct containing custom parameters that is fed to HWP
// call the HWP with each target ( if parallel, spin off a task )
@@ -300,7 +308,7 @@ void* call_dmi_io_run_training( void *io_pArgs )
"===== Call dmi_io_run_training HWP( cpu 0x%x, mcs 0x%x, mem 0x%x ) : ",
l_cpuNum,
l_mcsNum,
- k );
+ l_memNum );
EntityPath l_path;
l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>();
@@ -321,12 +329,10 @@ void* call_dmi_io_run_training( void *io_pArgs )
l_err->reasonCode(),
l_cpuNum,
l_mcsNum,
- k );
-
- ErrlUserDetailsTarget myDetails( l_mem_target );
+ l_memNum );
// capture the target data in the elog
- myDetails.addToLog( l_err );
+ ErrlUserDetailsTarget(l_mem_target).addToLog( l_err );
/*@
* @errortype
@@ -354,7 +360,7 @@ void* call_dmi_io_run_training( void *io_pArgs )
"( cpu 0x%x, mcs 0x%x, mem 0x%x ) ",
l_cpuNum,
l_mcsNum,
- k );
+ l_memNum );
}
} //end for l_mem_target
@@ -411,20 +417,25 @@ void* call_proc_cen_framelock( void *io_pArgs )
TARGETING::TargetHandleList l_mcsTargetList;
getAllChiplets(l_mcsTargetList, TYPE_MCS);
- for ( size_t i = 0; i < l_mcsTargetList.size() ; ++i )
+ for (TargetHandleList::iterator l_mcs_iter = l_mcsTargetList.begin();
+ l_mcs_iter != l_mcsTargetList.end();
+ ++l_mcs_iter)
{
// make a local copy of the MCS target
- const TARGETING::Target* l_mcs_target = l_mcsTargetList[i];
+ const TARGETING::Target* l_mcs_target = *l_mcs_iter;
// find all the Centaurs that are associated with this MCS
TARGETING::TargetHandleList l_memTargetList;
getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF);
- for ( uint8_t k = 0, l_memNum = 0; k < l_memTargetList.size();
- k++, l_memNum++ )
+ for (TargetHandleList::iterator l_mem_iter = l_memTargetList.begin();
+ l_mem_iter != l_memTargetList.end();
+ ++l_mem_iter)
{
// make a local copy of the MEMBUF target
- const TARGETING::Target* l_mem_target = l_memTargetList[k];
+ const TARGETING::Target* l_mem_target = *l_mem_iter;
+
+ uint8_t l_memNum = l_mem_target->getAttr<ATTR_POSITION>();
// fill out the args struct.
l_args.in_error_state = false;
@@ -538,14 +549,72 @@ void* call_host_attnlisten_cen( void *io_pArgs )
//
void* call_cen_set_inband_addr( void *io_pArgs )
{
- errlHndl_t l_err = NULL;
+ IStepError l_StepError;
- TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr entry" );
+ TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "call_cen_set_inband_addr entry" );
+ // get the mcs chiplets
+ TARGETING::TargetHandleList l_mcsTargetList;
+ getAllChiplets(l_mcsTargetList, TYPE_MCS);
- TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_set_inband_addr exit" );
+ for (TargetHandleList::iterator l_mcs_iter = l_mcsTargetList.begin();
+ l_mcs_iter != l_mcsTargetList.end();
+ ++l_mcs_iter)
+ {
+ const TARGETING::Target* l_pTarget = *l_mcs_iter;
+ const fapi::Target l_fapi_target( TARGET_TYPE_MCS_CHIPLET,
+ reinterpret_cast<void *>
+ (const_cast<TARGETING::Target*>(l_pTarget)));
- return l_err;
+ TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+ "Running cen_set_inband_addr HWP on...");
+ EntityPath l_path;
+ l_path = l_pTarget->getAttr<ATTR_PHYS_PATH>();
+ l_path.dump();
+
+ errlHndl_t l_err = NULL;
+ FAPI_INVOKE_HWP(l_err, proc_cen_set_inband_addr, l_fapi_target);
+ if ( l_err )
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X : proc_cen_set_inband_addr HWP", l_err->reasonCode());
+
+ // capture the target data in the elog
+ ErrlUserDetailsTarget(l_pTarget).addToLog( l_err );
+
+ /*@
+ * @errortype
+ * @reasoncode ISTEP_DMI_TRAINING_FAILED
+ * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE
+ * @moduleid ISTEP_PROC_CEN_SET_INBAND_ADDR
+ * @userdata1 bytes 0-1: plid identifying first error
+ * bytes 2-3: reason code of first error
+ * @userdata2 bytes 0-1: total number of elogs included
+ * bytes 2-3: N/A
+ * @devdesc call to proc_cen_set_inband_addr has failed
+ *
+ */
+ l_StepError.addErrorDetails(ISTEP_DMI_TRAINING_FAILED,
+ ISTEP_PROC_CEN_SET_INBAND_ADDR,
+ l_err);
+
+ errlCommit( l_err, HWPF_COMP_ID );
+
+ break; // break out of mcs loop
+ }
+ else
+ {
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "SUCCESS : proc_cen_set_inband_addr HWP");
+ }
+ } // end for mcs
+
+
+ TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "call_cen_set_inband_addr exit" );
+
+ return l_StepError.getErrorHandle();
}
diff --git a/src/usr/hwpf/hwp/dmi_training/makefile b/src/usr/hwpf/hwp/dmi_training/makefile
index 70cd04b29..338efcd51 100644
--- a/src/usr/hwpf/hwp/dmi_training/makefile
+++ b/src/usr/hwpf/hwp/dmi_training/makefile
@@ -40,15 +40,18 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
OBJS = dmi_training.o \
proc_cen_framelock.o \
dmi_io_run_training.o \
- dmi_scominit.o
+ dmi_scominit.o \
+ proc_cen_set_inband_addr.o
## NOTE: add a new directory onto the vpaths when you add a new HWP
VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C
new file mode 100644
index 000000000..c10ae1502
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C
@@ -0,0 +1,175 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* COPYRIGHT International Business Machines Corp. 2012 */
+/* */
+/* p1 */
+/* */
+/* Object Code Only (OCO) source materials */
+/* Licensed Internal Code Source Materials */
+/* IBM HostBoot Licensed Internal Code */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* Origin: 30 */
+/* */
+/* IBM_PROLOG_END_TAG */
+// -*- mode: C++; c-file-style: "linux"; -*-
+// $Id: proc_cen_set_inband_addr.C,v 1.7 2012/11/30 15:33:50 mfred Exp $
+// $Source: /afs/awd.austin.ibm.com/proj/p9/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_set_inband_addr.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE : proc_cen_set_inband_addr.C
+// *! DESCRIPTION : Set the inband base address in the MCS MDFGPR register
+// *!
+// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com
+// *!
+// *! The purpose of this procedure is to set the inband base address in the MCS MDFGPR register
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "p8_scom_addresses.H"
+#include "proc_cen_set_inband_addr.H"
+#include <fapi.H>
+
+
+using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+
+
+
+//------------------------------------------------------------------------------
+// Function definition
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+ //------------------------------------------------------------------------------
+ // function: Set the inband base address in the MCS MDFGPR register
+ //
+ // parameters: i_target => MCS chiplet of processor chip
+ // returns: FAPI_RC_SUCCESS if operation was successful, else error
+ //------------------------------------------------------------------------------
+ fapi::ReturnCode proc_cen_set_inband_addr(const fapi::Target & i_target)
+ {
+ // data buffer to hold register values
+ ecmdDataBufferBase scom_data(64);
+ ecmdDataBufferBase attr_data(64);
+
+ // return codes
+ uint32_t rc_ecmd = 0;
+ fapi::ReturnCode rc;
+
+ // locals
+ uint64_t inband_base_addr = 0;
+
+
+ // mark function entry
+ FAPI_INF("********* Starting proc_cen_set_inband_addr *********");
+ do
+ {
+
+ // Read the ATTR_MCS_INBAND_BASE_ADDRESS attribute
+ rc = FAPI_ATTR_GET( ATTR_MCS_INBAND_BASE_ADDRESS, &i_target, inband_base_addr);
+ if (rc)
+ {
+ FAPI_ERR("Failed to get attribute: ATTR_MCS_INBAND_BASE_ADDRESS.");
+ break;
+ }
+ FAPI_DBG("The inband base address is specified to be set to: %#llX.", inband_base_addr);
+
+
+
+ // Munge the bits:
+ // Extract bits 14:27 from the attribute value, pass them into bits 6:19 of the register
+ // In the target register:
+ // Bit 0 is MCFGPRQ_VALID. Needs to be set to '1'.
+ // Bits 6:19 are MCFGPRQ_BASE_ADDRESS. Needs to be set to base address for inband SCOM operations.
+ rc_ecmd |= attr_data.setDoubleWord(0, inband_base_addr);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("Error 0x%x filling ecmd data buffer with value from an attribute.", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+ rc_ecmd |= scom_data.flushTo0();
+ // Insert bits 17:27 from the attribute data into the scom data buffer bits 6:19
+ rc_ecmd |= scom_data.insert( attr_data, 6, 14, 14);
+ // Set bit 0 to be a '1'
+ rc_ecmd |= scom_data.setBit(0);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("Error 0x%x setting up ecmd data buffer to write MCS MCFGPR Register.", rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+
+
+ // Write the MCS MCFGPR register.
+ // Write SCOM address=MCS_MCFGPR_0x02011802 using data from attibute.
+ FAPI_DBG("Writing MCS MCFGPR Register to set base address for inband SCOM operations.");
+ rc = fapiPutScom( i_target, MCS_MCFGPR_0x02011802, scom_data);
+ if (rc)
+ {
+ FAPI_ERR("Error writing MCS MCFGPR Register to set base address for inband SCOM operations.");
+ break;
+ }
+
+
+
+ } while (0); // end do
+
+ // mark function exit
+ FAPI_INF("********* proc_cen_set_inband_addr complete *********");
+ return rc;
+ } // end FAPI procedure proc_cen_set_inband_addr
+
+} // extern "C"
+
+/*
+*************** Do not edit this area ***************
+This section is automatically updated by CVS when you check in this file.
+Be sure to create CVS comments when you commit so that they can be included here.
+$Log: proc_cen_set_inband_addr.C,v $
+Revision 1.7 2012/11/30 15:33:50 mfred
+Several updates suggested by gerrit code review. Get rid of unused attribute reference. Change name of inband bar attribute.
+
+Revision 1.6 2012/11/15 20:15:01 mfred
+Update the hwp to take real address from attribute and modify value for BAR register.
+
+Revision 1.5 2012/11/06 17:11:36 mfred
+Procedure now gets the BAR value from the attribute.
+
+Revision 1.4 2012/10/24 15:32:27 mfred
+Temporarilly hardcode the BAR value until the attribute is ready.
+
+Revision 1.3 2012/10/11 14:36:24 mfred
+Updated code to write to MCS MCFGPR Regsiter.
+
+Revision 1.2 2012/10/10 21:11:15 mfred
+Check in some updates to two new procedures.
+
+
+*/
+
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H
new file mode 100644
index 000000000..04e82b312
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H
@@ -0,0 +1,74 @@
+/* IBM_PROLOG_BEGIN_TAG */
+/* This is an automatically generated prolog. */
+/* */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H $ */
+/* */
+/* IBM CONFIDENTIAL */
+/* */
+/* COPYRIGHT International Business Machines Corp. 2012 */
+/* */
+/* p1 */
+/* */
+/* Object Code Only (OCO) source materials */
+/* Licensed Internal Code Source Materials */
+/* IBM HostBoot Licensed Internal Code */
+/* */
+/* The source code for this program is not published or otherwise */
+/* divested of its trade secrets, irrespective of what has been */
+/* deposited with the U.S. Copyright Office. */
+/* */
+/* Origin: 30 */
+/* */
+/* IBM_PROLOG_END_TAG */
+// $Id: proc_cen_set_inband_addr.H,v 1.2 2012/11/30 15:33:55 mfred Exp $
+// $Source: /afs/awd.austin.ibm.com/proj/p9/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_set_inband_addr.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE : proc_cen_set_inband_addr.H
+// *! DESCRIPTION : Set the inband base address in the MCS unit MCFGPR registers
+// *!
+// *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_CEN_SET_INBAND_ADDR_H_
+#define _PROC_CEN_SET_INBAND_ADDR_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_cen_set_inband_addr_FP_t)(const fapi::Target &);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+/**
+ * @brief proc_cen_set_inband_addr procedure. The purpose of this procedure is to set the inband base address in the MCS unit MCFGPR registers
+ *
+ * @param[in] i_target Reference to pu.mcs target
+ *
+ * @return ReturnCode
+ */
+
+ fapi::ReturnCode proc_cen_set_inband_addr(const fapi::Target & i_target);
+ // Target is pu.mcs
+
+} // extern "C"
+
+#endif // _PROC_CEN_SET_INBAND_ADDR_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml
new file mode 100644
index 000000000..75870e0c0
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml
@@ -0,0 +1,38 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml $ -->
+<!-- -->
+<!-- IBM CONFIDENTIAL -->
+<!-- -->
+<!-- COPYRIGHT International Business Machines Corp. 2012 -->
+<!-- -->
+<!-- p1 -->
+<!-- -->
+<!-- Object Code Only (OCO) source materials -->
+<!-- Licensed Internal Code Source Materials -->
+<!-- IBM HostBoot Licensed Internal Code -->
+<!-- -->
+<!-- The source code for this program is not published or otherwise -->
+<!-- divested of its trade secrets, irrespective of what has been -->
+<!-- deposited with the U.S. Copyright Office. -->
+<!-- -->
+<!-- Origin: 30 -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<!-- proc_setup_bars_mmio_attributes.xml -->
+<attributes>
+ <!-- ********************************************************************* -->
+ <attribute>
+ <id>ATTR_MCS_INBAND_BASE_ADDRESS</id>
+ <targetType>TARGET_TYPE_MCS_CHIPLET</targetType>
+ <description>Base address to set in MCFGPR for inband SCOM access
+ creator: platform
+ consumer: proc_cen_set_inband_addr
+ </description>
+ <valueType>uint64</valueType>
+ <platInit/>
+ <persistRuntime/>
+ </attribute>
+ <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index dd47f32cb..2ddcedd7e 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -95,7 +95,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml \
hwp/runtime_attributes/pm_attributes_all_plat.xml \
hwp/runtime_attributes/pm_attributes_all_hwp.xml \
- hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
+ hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml \
+ hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml
#------------------------------------------------------------------------------
# Initfiles
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 4d9d673b7..fc28a5c53 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -3957,8 +3957,11 @@
</uint64_t>
</simpleType>
<persistency>non-volatile</persistency>
- <!-- Link to ATTR_PROC_INBAND_MCFGPRQ_BASE_ADDRESS (@todo RTC:42177) -->
<readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_MCS_INBAND_BASE_ADDRESS</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
</attribute>
<attribute>
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index 741fd9d2b..22b9e1c6c 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -72,7 +72,8 @@ FAPI_ATTR_SOURCES = \
activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml \
runtime_attributes/pm_attributes_all_hwp.xml \
runtime_attributes/pm_attributes_all_plat.xml \
- nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
+ nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml \
+ dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml
XMLTOHB_GENERIC_XML = generic.xml
diff --git a/src/usr/targeting/common/xmltohb/vbu.system.xml b/src/usr/targeting/common/xmltohb/vbu.system.xml
index b6d08ffd2..147a222c0 100644
--- a/src/usr/targeting/common/xmltohb/vbu.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu.system.xml
@@ -490,6 +490,10 @@
<id>CHIP_UNIT</id>
<default>4</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E08000000000</default>
+ </attribute>
</targetInstance>
<targetInstance>
@@ -508,6 +512,10 @@
<id>CHIP_UNIT</id>
<default>5</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0A000000000</default>
+ </attribute>
</targetInstance>
<targetInstance>
@@ -526,6 +534,10 @@
<id>CHIP_UNIT</id>
<default>6</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0C000000000</default>
+ </attribute>
</targetInstance>
<targetInstance>
@@ -544,6 +556,10 @@
<id>CHIP_UNIT</id>
<default>7</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0E000000000</default>
+ </attribute>
</targetInstance>
<!-- Murano n0p0 PCI units -->
diff --git a/src/usr/targeting/xmltohb/TULETA.mrw.xml b/src/usr/targeting/xmltohb/TULETA.mrw.xml
index 243e0df3a..6b58e5fe0 100755..100644
--- a/src/usr/targeting/xmltohb/TULETA.mrw.xml
+++ b/src/usr/targeting/xmltohb/TULETA.mrw.xml
@@ -20,7 +20,7 @@
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
-<!-- Source path = /gsa/ausgsa-h2/02/vanlee/sb/102512M/obj/ppc/mrw/xml/data -->
+<!-- Source path = /esw/fips810/Builds/b1113t_1247.810/obj/ppc/mrw/xml/data -->
<attributes>
<!-- TULETA System with new values-->
@@ -586,6 +586,10 @@
<id>CHIP_UNIT</id>
<default>4</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0800000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -615,6 +619,10 @@
<id>CHIP_UNIT</id>
<default>5</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0A00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -644,6 +652,10 @@
<id>CHIP_UNIT</id>
<default>6</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0C00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -673,6 +685,10 @@
<id>CHIP_UNIT</id>
<default>7</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E0E00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1251,6 +1267,10 @@
<id>CHIP_UNIT</id>
<default>4</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E1800000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1280,6 +1300,10 @@
<id>CHIP_UNIT</id>
<default>5</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E1A00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1309,6 +1333,10 @@
<id>CHIP_UNIT</id>
<default>6</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E1C00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1338,6 +1366,10 @@
<id>CHIP_UNIT</id>
<default>7</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E1E00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1916,6 +1948,10 @@
<id>CHIP_UNIT</id>
<default>4</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E4800000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1945,6 +1981,10 @@
<id>CHIP_UNIT</id>
<default>5</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E4A00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -1974,6 +2014,10 @@
<id>CHIP_UNIT</id>
<default>6</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E4C00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -2003,6 +2047,10 @@
<id>CHIP_UNIT</id>
<default>7</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E4E00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -2581,6 +2629,10 @@
<id>CHIP_UNIT</id>
<default>4</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E5800000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -2610,6 +2662,10 @@
<id>CHIP_UNIT</id>
<default>5</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E5A00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -2639,6 +2695,10 @@
<id>CHIP_UNIT</id>
<default>6</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E5C00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
@@ -2668,6 +2728,10 @@
<id>CHIP_UNIT</id>
<default>7</default>
</attribute>
+ <attribute><id>IBSCOM_MCS_BASE_ADDR</id>
+ <!-- baseAddr = 0x0003E00000000000, 128GB per MCS -->
+ <default>0x0003E5E00000000</default>
+ </attribute>
<!-- TODO When MRW provides the information, these two attributes
should be included. values of X come from MRW.
<attribute>
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