diff options
| -rw-r--r-- | src/include/usr/hwpf/hwp/procMemConsts.H | 8 | ||||
| -rw-r--r-- | src/usr/hwpf/plat/fapiPlatAttributeService.C | 36 |
2 files changed, 39 insertions, 5 deletions
diff --git a/src/include/usr/hwpf/hwp/procMemConsts.H b/src/include/usr/hwpf/hwp/procMemConsts.H index 9a1282b04..9aab51ef0 100644 --- a/src/include/usr/hwpf/hwp/procMemConsts.H +++ b/src/include/usr/hwpf/hwp/procMemConsts.H @@ -58,6 +58,14 @@ const uint64_t PCIE_BAR0_SIZE = 0x0000001000000000ULL; const uint64_t PCIE_BAR1_SIZE = 0x0000000080000000ULL; const uint64_t PCIE_BAR2_SIZE = 0x0000000000001000ULL; +// 4 PHB per chip, 4chips per node, max 4 nodes +const uint64_t PCIE_BAR0_OFFSET_MASK = ((PCIE_BAR0_SIZE*4*4*4)-1); +const uint64_t PCIE_BAR1_OFFSET_MASK = ((PCIE_BAR1_SIZE*4*4*4)-1); +const uint64_t SAPPHIRE_PCIE_BAR0_BASE = 0x00003B0000000000; +const uint64_t SAPPHIRE_PCIE_BAR1_BASE = 0x00003FE000000000; + + + // PHB Register Address Space - line 90 Overall Map // size is 1_MB const uint64_t PHB_REGS_SIZE = 0x0000000000100000ULL; diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C index 7567a7bd0..25e2a50c1 100644 --- a/src/usr/hwpf/plat/fapiPlatAttributeService.C +++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C @@ -933,14 +933,40 @@ fapi::ReturnCode fapiPlatGetProcPcieBarBaseAddr ( l_pProcTarget->tryGetAttr<TARGETING::ATTR_PHB_BASE_ADDRS>( l_phbRegs); - // BAR # 0 are the PCIE mem 64 - // BAR # 1 are the PCIE mem 32 + // BAR # 0 are the PCIE mem 64, 64GB window + // BAR # 1 are the PCIE mem 32, 2GB window // BAR # 2 are the PHB REGS + + //If we are in sapphire mode we need to shift the PCI + //Mem addresses down below the 48 bit limit for an NVIDA + //adapter. This is a workaround for GA1 so the adapter + //can be supported. Largest (theoretically dimm) is 1TB, + //so max mem is ~32TB for non brazos system. + + //Place mem64 @ 59TB-63TB (0x00003B0000000000) + //Place mem32 @ 63.875TB-64TB (0x00030FE000000000) + + //TODO RTC 100773 -- Fix this the correct way by + //having base addresses per payload type + + //We will change the base addr down 4 bits, but need to keep + //the proc/node offsets the same for ( uint8_t u=0; u < 3; u++ ) { - o_pcieBarBase[u][0] = l_pciMem64[u]; - o_pcieBarBase[u][1] = l_pciMem32[u]; - o_pcieBarBase[u][2] = l_phbRegs[u]; + if(TARGETING::is_sapphire_load()) + { + o_pcieBarBase[u][0] = SAPPHIRE_PCIE_BAR0_BASE | + (l_pciMem64[u] & PCIE_BAR0_OFFSET_MASK); + o_pcieBarBase[u][1] = SAPPHIRE_PCIE_BAR1_BASE | + (l_pciMem32[u] & PCIE_BAR1_OFFSET_MASK); + } + else + { + o_pcieBarBase[u][0] = l_pciMem64[u]; + o_pcieBarBase[u][1] = l_pciMem32[u]; + } + + o_pcieBarBase[u][2] = l_phbRegs[u]; FAPI_DBG( "fapiPlatGetProcPcieBarBaseAddr: Unit %d : %p %p %p", u, |
