diff options
6 files changed, 257 insertions, 72 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index 10877ae54..14e778ae0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -26,18 +26,21 @@ /// @file p9_pm_pstate_gpe_init.C /// @brief Stop, reset and initalize/start the Pstate GPE /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP BackupHWP Owner: Amit Kumar <akumar3@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: FSP:HS +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS // ----------------------------------------------------------------------------- // Includes // ----------------------------------------------------------------------------- #include <p9_pm_pstate_gpe_init.H> #include <p9_pm_hcd_flags.h> +#include <p9_ppe_defs.H> +#include <p9_ppe_utils.H> +#include <vector> // ----------------------------------------------------------------------------- // Constants @@ -74,13 +77,13 @@ fapi2::ReturnCode pstate_gpe_init( fapi2::buffer<uint64_t> l_ivpr; uint32_t l_xsr_halt_condition = 0; uint32_t l_timeout_counter = TIMEOUT_COUNT; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET_Type l_ivpr_offset = 0; fapi2::ATTR_VDD_AVSBUS_BUSNUM_Type l_avsbus_number = 0; fapi2::ATTR_VDD_AVSBUS_RAIL_Type l_avsbus_rail = 0; fapi2::ATTR_SYSTEM_PSTATES_MODE_Type l_pstates_mode = 0; - + std::vector<uint64_t> l_pgpe_base_addr; + l_pgpe_base_addr.push_back( PGPE_BASE_ADDRESS ); FAPI_IMP(">> pstate_gpe_init......"); @@ -152,7 +155,6 @@ fapi2::ReturnCode pstate_gpe_init( FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_GPETSEL_SCOM, l_data64)); // Program XCR to ACTIVATE PGPE - // @todo RTC 146665 Operations to PPEs should use a p9ppe namespace FAPI_INF(" Starting the PGPE..."); l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1, 3); FAPI_TRY(putScom(i_target, PU_GPE2_PPE_XIXCR, l_xcr)); @@ -192,18 +194,19 @@ fapi2::ReturnCode pstate_gpe_init( ((l_xsr_halt_condition == p9hcd::DEBUG_HALT || l_xsr_halt_condition == p9hcd::DBCR_HALT) )), fapi2::PSTATE_GPE_INIT_DEBUG_HALT() - .set_CHIP(i_target), + .set_CHIP(i_target) + .set_PGPE_BASE_ADDRESS(l_pgpe_base_addr) + .set_PGPE_STATE_MODE(HALT), "Pstate GPE Debug Halt detected"); - // @todo 146665 Need to collect PGPE state. Operations to PPEs should - // use a p9ppe namespace class when created - // When PGPE fails to boot, assert out FAPI_ASSERT((l_timeout_counter != 0 && l_occ_scratch2.getBit<p9hcd::PGPE_ACTIVE>() == 1 && l_xsr_iar.getBit<p9hcd::HALTED_STATE>() != 1), fapi2::PSTATE_GPE_INIT_TIMEOUT() - .set_CHIP(i_target), + .set_CHIP(i_target) + .set_PGPE_BASE_ADDRESS(l_pgpe_base_addr) + .set_PGPE_STATE_MODE(HALT), "Pstate GPE Init timeout"); if(l_occ_scratch2.getBit<p9hcd::PGPE_ACTIVE>()) @@ -245,7 +248,6 @@ fapi2::ReturnCode pstate_gpe_init( FAPI_INF(" PGPE booting is disabled and is NOT running!!!!"); } - fapi_try_exit: FAPI_IMP("<< pstate_gpe_init......"); return fapi2::current_err; @@ -267,20 +269,18 @@ fapi2::ReturnCode pstate_gpe_reset( fapi2::buffer<uint64_t> l_data64; uint32_t l_timeout_in_MS = 100; + std::vector<uint64_t> l_pgpe_base_addr; + l_pgpe_base_addr.push_back( PGPE_BASE_ADDRESS ); FAPI_IMP(">> pstate_gpe_reset..."); // Program XCR to HALT PGPE - // @todo This should be replaced by a call to a common PPE service class - // ppe<PPE_TYPE_GPE>GPE2(3); - // GPE2.hard_reset(); FAPI_INF(" Send HALT command via XCR..."); l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); FAPI_TRY(putScom(i_target, PU_GPE2_PPE_XIXCR, l_data64)); // Now wait for PGPE to be halted. - // @todo This loop should be replace by a call to a common PPE service class // FAPI_TRY(GPE2.is_halted(&b_halted_state, // timeout_value_ns, // timeout_value_simcycles)); @@ -297,8 +297,10 @@ fapi2::ReturnCode pstate_gpe_reset( // When PGPE fails to halt, then assert ot FAPI_ASSERT((l_timeout_in_MS != 0), fapi2::PSTATE_GPE_RESET_TIMEOUT() - .set_CHIP(i_target), - "PSTATE GPE Init timeout"); + .set_CHIP(i_target) + .set_PGPE_BASE_ADDRESS(l_pgpe_base_addr) + .set_PGPE_STATE_MODE(SNAPSHOT), + "PSTATE GPE Reset timeout"); FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_data64)); FAPI_INF(" Clear PGPE_ACTIVE in OCC Flag Register..."); @@ -339,7 +341,7 @@ fapi2::ReturnCode p9_pm_pstate_gpe_init( fapi2::PSTATE_GPE_PBA_INIT_FAILED() .set_CHIP(i_target) .set_MODE(p9pm::PM_INIT), - "PBA setup failed"); + "PBA Setup Failed" ); } // Reset the PSTATE GPE @@ -351,7 +353,6 @@ fapi2::ReturnCode p9_pm_pstate_gpe_init( // Unsupported Mode else { - FAPI_ERR("Unknown mode %x passed to p9_pstate_gpe_init.", i_mode); FAPI_ASSERT(false, fapi2::PSTATE_GPE_BAD_MODE() .set_BADMODE(i_mode), diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.H index c6c4636cf..f308fed8a 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.H @@ -26,12 +26,12 @@ /// @file p9_pm_pstate_gpe_init.H /// @brief Initialize the STOP GPE Engine in the OCC /// -// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP BackupHWP Owner: Amit Kumar <akumar3@us.ibm.com> -// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 2 -// *HWP Consumed by: FSP:HS +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : Rahul Batra <rbatra@us.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS /// /// High-level procedure flow: /// @verbatim diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C index a4bec9442..9920b0962 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C @@ -25,12 +25,12 @@ /// @file p9_pm_stop_gpe_init.C /// @brief Initialize the Stop GPE and related functions -// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> -// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> -// *HWP Team : PM -// *HWP Level : 1 -// *HWP Consumed by : HS +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : David Du <daviddu@us.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS /// /// High-level procedure flow: @@ -56,11 +56,21 @@ // Includes // ----------------------------------------------------------------------------- +#include <vector> +#include <algorithm> #include <p9_hcd_common.H> #include <p9_pm_stop_gpe_init.H> #include <p9_pm_pba_init.H> #include <p9_pm_pfet_init.H> #include <p9_pm_hcd_flags.h> +#include <p9_ppe_defs.H> +#include <p9_ppe_utils.H> +#include <p9_eq_clear_atomic_lock.H> +#include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> +#include <p9_misc_scom_addresses.H> +#include <p9_misc_scom_addresses_fld.H> + //#include <p9_ppe_state.H> @todo RTC 147996 to incorporate PPE state removing strings. @@ -78,8 +88,6 @@ static const uint32_t SGPE_POLLTIME_MS = 20; // Guess at this time static const uint32_t SGPE_POLLTIME_MCYCLES = 2; // Guess at this time static const uint32_t TIMEOUT_COUNT = SGPE_TIMEOUT_MS / SGPE_POLLTIME_MS; -static const uint64_t GPE3_BASE_ADDRESS = 0x00066010; -static const uint64_t SGPE_BASE_ADDRESS = GPE3_BASE_ADDRESS; @@ -96,6 +104,10 @@ fapi2::ReturnCode stop_gpe_reset( fapi2::ReturnCode stop_corecache_setup( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); +fapi2::ReturnCode get_functional_chiplet_info( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target , + std::vector<uint64_t>& o_ppe_addr_list, + std::vector< fapi2::Target<fapi2::TARGET_TYPE_EQ > >& o_eq_target_list ); // ----------------------------------------------------------------------------- // Function definitions // ----------------------------------------------------------------------------- @@ -113,7 +125,7 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const p9pm::PM_FLOW_MODE i_mode) { - FAPI_IMP("> p9_pm_stop_gpe_init"); + FAPI_IMP(">> p9_pm_stop_gpe_init"); const char* PM_MODE_NAME_VAR; //Defines storage for PM_MODE_NAME FAPI_INF("Executing p9_stop_gpe_init in mode %s", PM_MODE_NAME(i_mode)); @@ -316,7 +328,7 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( } fapi_try_exit: - FAPI_INF("< p9_pm_stop_gpe_init"); + FAPI_INF("<< p9_pm_stop_gpe_init"); return fapi2::current_err; } @@ -342,8 +354,13 @@ fapi2::ReturnCode stop_gpe_init( fapi2::buffer<uint64_t> l_slave_cfg; uint32_t l_ivpr_offset; uint32_t l_timeout_in_MS = TIMEOUT_COUNT; + std::vector<uint64_t> l_ppe_base_addr_list; + std::vector< fapi2::Target<fapi2::TARGET_TYPE_EQ> > l_eq_list; + + FAPI_IMP(">> stop_gpe_init"); - FAPI_IMP(">> stop_gpe_init......"); + FAPI_TRY( get_functional_chiplet_info( i_target, l_ppe_base_addr_list, l_eq_list ), + "Failed to get PPE Base Address List and Func EQ List" ); // First check if SGPE_ACTIVE is not set in OCCFLAG register FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCFLG_SCOM, l_occ_flag)); @@ -368,7 +385,6 @@ fapi2::ReturnCode stop_gpe_init( FAPI_TRY(putScom(i_target, PU_GPE3_GPEIVPR_SCOM, l_ivpr)); // Program XCR to ACTIVATE SGPE - // @todo 146665 Operations to PPEs should use a p9ppe namespace when created l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1 , 3); FAPI_TRY(putScom(i_target, PU_GPE3_PPE_XIXCR, l_xcr)); l_xcr.flush<0>().insertFromRight(p9hcd::TOGGLE_XSR_TRH, 1 , 3); @@ -393,7 +409,7 @@ fapi2::ReturnCode stop_gpe_init( l_iar, l_ir, l_timeout_in_MS); - fapi2::delay(SGPE_POLLTIME_MS * 1000 * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000); + fapi2::delay(SGPE_POLLTIME_MS * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000); } while((!((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() == 1) && (l_xsr.getBit<p9hcd::HALTED_STATE>() == 0))) && @@ -404,15 +420,31 @@ fapi2::ReturnCode stop_gpe_init( FAPI_INF("SGPE was activated successfully!!!!"); } - // @todo 146665 Operations to PPEs should use a p9ppe namespace when created - FAPI_ASSERT((l_timeout_in_MS != 0), - fapi2::STOP_GPE_INIT_TIMEOUT() - .set_CHIP(i_target), - "STOP GPE Init timeout"); + if( 0 == l_timeout_in_MS ) + { + // SGPE failed to boot or one more CME failed to boot. + // We need to collec the FFDC. Let us clear the atomic + // lock first to enable collection of CME's FFDC. + + for( auto eq : l_eq_list ) + { + p9_clear_atomic_lock( eq ); + } + + FAPI_ASSERT( false, + fapi2::STOP_GPE_INIT_TIMEOUT() + .set_CHIP(i_target) + .set_OCC_FLAG_REG_VAL( l_occ_flag ) + .set_XSR_REG_VAL( l_xsr ) + .set_PPE_STATE_MODE(HALT) + .set_PPE_BASE_ADDRESS_LIST(l_ppe_base_addr_list), + "STOP GPE Init Timeout"); + } + fapi_try_exit: - FAPI_IMP("<< stop_gpe_init......"); + FAPI_IMP("<< stop_gpe_init"); return fapi2::current_err; } @@ -433,33 +465,46 @@ fapi2::ReturnCode stop_gpe_reset( fapi2::buffer<uint64_t> l_data64; uint32_t l_timeout_in_MS = 100; + std::vector<uint64_t> l_ppe_base_addr_list; + std::vector< fapi2::Target<fapi2::TARGET_TYPE_EQ> > l_eq_list; FAPI_IMP(">> stop_gpe_reset..."); + FAPI_TRY( get_functional_chiplet_info( i_target, l_ppe_base_addr_list, l_eq_list ), + "Failed to get PPE Base Address List and Func EQ List" ); // Program XCR to HALT SGPE - // @todo This should be replace by a call to a common PPE service class - // ppe<PPE_TYPE_GPE>gpe3(3); - // gpe3.hard_reset(); FAPI_INF(" Send HALT command via XCR..."); l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); FAPI_TRY(putScom(i_target, PU_GPE3_PPE_XIXCR, l_data64)); //Now wait for SGPE to be halted. - // @todo This loop should be replace by a call to a common PPE service class - // FAPI_TRY(gpe3.is_halted(&b_halted_state, timeout_value_ns, timeout_value_simcycles)); FAPI_INF(" Poll for HALT State via XSR..."); do { FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_data64)); - fapi2::delay(SGPE_POLLTIME_MS * 1000 * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000); + fapi2::delay(SGPE_POLLTIME_MS * 1000, SGPE_POLLTIME_MCYCLES * 1000 * 1000); } while((l_data64.getBit<p9hcd::HALTED_STATE>() == 0) && (--l_timeout_in_MS != 0)); - FAPI_ASSERT((l_timeout_in_MS != 0), - fapi2::STOP_GPE_RESET_TIMEOUT() - .set_CHIP(i_target), - "STOP GPE Init timeout"); + if( 0 == l_timeout_in_MS ) + { + // SGPE Reset Failed. + // We need to collect the FFDC. Let us clear the atomic + // lock first to enable collection of CME's FFDC. + + for( auto eq : l_eq_list ) + { + p9_clear_atomic_lock( eq ); + } + + FAPI_ASSERT( false, + fapi2::STOP_GPE_RESET_TIMEOUT() + .set_CHIP(i_target) + .set_PPE_STATE_MODE(HALT) + .set_PPE_BASE_ADDRESS_LIST(l_ppe_base_addr_list), + "STOP Reset Timeout"); + } FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register..."); l_data64.flush<0>().setBit<p9hcd::SGPE_ACTIVE>(); @@ -501,3 +546,56 @@ fapi2::ReturnCode stop_corecache_setup( return fapi2::current_err; } + +// @brief Returns target for all functional EQ and base address of SGPE and all functional CMEs +// @param[in] i_target fapi2 target for P9 chip +// @param[out] o_ppe_addr_list list of base addresses for CMEs and SGPE +// @param[out] o_eq_target_list list of EQ target +// @return fapi2 return code +// @note instead of getting functional status from platform targeting, for better reliability +// we shall use value of QCSR register. +fapi2::ReturnCode get_functional_chiplet_info( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + std::vector<uint64_t>& o_ppe_addr_list, + std::vector< fapi2::Target<fapi2::TARGET_TYPE_EQ > >& o_eq_target_list ) +{ + + FAPI_INF(">> get_functional_chiplet_info"); + + fapi2::buffer<uint64_t> l_qcsrBuf; + uint8_t l_exPos = 0; + + auto l_ex_vector = i_target.getChildren<fapi2::TARGET_TYPE_EX>( fapi2::TARGET_STATE_PRESENT ); + FAPI_TRY(getScom(i_target, PU_OCB_OCI_QCSR_SCOM, l_qcsrBuf)); + FAPI_INF( "QCS Val 0x%16llX", l_qcsrBuf ); + + o_ppe_addr_list.push_back( SGPE_BASE_ADDRESS ); + + for ( auto ex : l_ex_vector ) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, ex, l_exPos )); + + if( l_qcsrBuf.getBit( l_exPos ) ) + { + FAPI_INF("Func EX %d ", l_exPos ); + o_ppe_addr_list.push_back( getCmeBaseAddress( l_exPos ) ); + fapi2::Target< fapi2::TARGET_TYPE_EQ > l_parentEq = ex.getParent<fapi2::TARGET_TYPE_EQ>(); + std::vector< fapi2::Target< fapi2::TARGET_TYPE_EQ > >::iterator l_eq; + l_eq = std::find ( o_eq_target_list.begin(), o_eq_target_list.end(), l_parentEq ); + + if ( l_eq != o_eq_target_list.end() ) + { + continue; + } + + FAPI_INF("Func EQ %d ", (l_exPos >> 1 ) ); + o_eq_target_list.push_back( l_parentEq ); + } + + } + +fapi_try_exit: + FAPI_INF("<< get_functional_chiplet_info"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.H index 905830bdb..9f484267a 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,12 +26,12 @@ /// @file p9_pm_stop_gpe_init.H /// @brief Initialize the STOP GPE Engine in the OCC /// -// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> -// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com> -// *HWP Team: PM -// *HWP Level: 1 -// *HWP Consumed by: FSP:HS +// *HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP Backup Owner : David Du <daviddu@us.ibm.com> +// *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 3 +// *HWP Consumed by : HS /// ///----------------------------------------------------------------------------- @@ -44,10 +44,6 @@ #include <p9_pm.H> #include <fapi2.H> -#include <p9_quad_scom_addresses.H> -#include <p9_quad_scom_addresses_fld.H> -#include <p9_misc_scom_addresses.H> -#include <p9_misc_scom_addresses_fld.H> // function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_pm_stop_gpe_init_FP_t) ( diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml index f4a92a764..4afc2d06a 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml @@ -22,8 +22,15 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - <!-- Error definitions for p9_pm_pstate_gpe_init procedure --> +<!-- + *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> + *HWP Backup Owner : Rahul Batra <rbatra@us.ibm.com> + *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> + *HWP Team : PM + *HWP Level : 3 + *HWP Consumed by : HS +--> <hwpErrors> <!-- ******************************************************************** --> <hwpError> @@ -42,11 +49,16 @@ <description> Pstate GPE init timed out while waiting for PGPE Active in OCC SCRATCH2. </description> + <ffdc>CHIP</ffdc> + <ffdc>PGPE_BASE_ADDRESS</ffdc> + <ffdc>PGPE_STATE_MODE</ffdc> <collectRegisterFfdc> <id>PGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, PGPE_STATE_MODE, PGPE_BASE_ADDRESS</collectFfdc> <callout> <target>CHIP</target> <priority>LOW</priority> @@ -78,11 +90,18 @@ <description> Pstate GPE init detected a Debug Halt condition. This should only assert in a development debug environment. </description> + <ffdc>CHIP</ffdc> + <ffdc>PGPE_BASE_ADDRESS</ffdc> + <ffdc>PGPE_STATE_MODE</ffdc> + <collectRegisterFfdc> <id>PGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, PGPE_STATE_MODE, PGPE_BASE_ADDRESS</collectFfdc> + <callout> <target>CHIP</target> <priority>LOW</priority> @@ -97,11 +116,18 @@ <rc>RC_PSTATE_GPE_RESET_TIMEOUT</rc> <description> Pstate GPE init timed out while waiting for HALT status in XSR register. </description> + <ffdc>CHIP</ffdc> + <ffdc>PGPE_BASE_ADDRESS</ffdc> + <ffdc>PGPE_STATE_MODE</ffdc> + <collectRegisterFfdc> <id>PGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, PGPE_STATE_MODE, PGPE_BASE_ADDRESS</collectFfdc> + <callout> <procedure>CODE</procedure> <priority>LOW</priority> @@ -114,10 +140,11 @@ <!-- ******************************************************************** --> <hwpError> <rc>RC_PSTATE_GPE_PBA_INIT_FAILED</rc> - <description> Pstate GPE called to p9_pm_pba_init failed. + <description>p9_pm_pba_init failed in PM_INIT mode. </description> - <ffdc>TARGET</ffdc> <ffdc>MODE</ffdc> + <ffdc>CHIP</ffdc> + <callout> <procedure>CODE</procedure> <priority>LOW</priority> @@ -131,6 +158,7 @@ <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + </hwpError> <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml index 414996d13..278e5b56a 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml @@ -22,6 +22,15 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- Error definitions for p9_pm_stop_gpe_init procedure --> +<!-- + *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> + *HWP Backup Owner : David Du <daviddu@us.ibm.com> + *HWP FW Owner : Prem S Jha <premjha2@in.ibm.com> + *HWP Team : PM + *HWP Level : 3 + *HWP Consumed by : HS +--> <hwpErrors> <!-- ******************************************************************** --> <hwpError> @@ -29,6 +38,10 @@ <description>Unknown mode passed to p9_pm_stop_gpe_init. </description> <ffdc>BADMODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -60,22 +73,53 @@ <rc>RC_STOP_GPE_INIT_TIMEOUT</rc> <description> Stop GPE init timed out while waiting for SGPE Active in OCCFLG register. </description> + + <ffdc>CHIP</ffdc> + <ffdc>PPE_STATE_MODE</ffdc> + <ffdc>OCC_FLAG_REG_VAL</ffdc> + <ffdc>XSR_REG_VAL</ffdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, PPE_STATE_MODE, PPE_BASE_ADDRESS_LIST</collectFfdc> + <collectRegisterFfdc> <id>SGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>LOW</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <rc>RC_STOP_GPE_RESET_TIMEOUT</rc> <description> Stop GPE init timedout while waiting for HALT status in XSR register. </description> + <ffdc>CHIP</ffdc> + <ffdc>PPE_STATE_MODE</ffdc> + <collectRegisterFfdc> <id>SGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + + <collectFfdc>p9_collect_ppe_state, CHIP, PPE_STATE_MODE, PPE_BASE_ADDRESS_LIST</collectFfdc> + + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -83,11 +127,20 @@ <description> Stop GPE called to p9_pm_pfet_init failed. </description> <ffdc>MODE</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>SGPE_FFDC_REGISTERS</id> <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> @@ -95,6 +148,7 @@ <description> Stop GPE called to p9_pm_pba_init failed. </description> <ffdc>MODE</ffdc> + <ffdc>CHIP</ffdc> <collectRegisterFfdc> <id>PBA_FFDC_REGISTERS</id> <target>CHIP</target> @@ -105,6 +159,14 @@ <target>CHIP</target> <targetType>TARGET_TYPE_PROC_CHIP</targetType> </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> |
