diff options
| -rw-r--r-- | src/import/chips/p9/initfiles/p9n.mcs.scom.initfile | 9 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C | 2 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile index 50de9d185..8b032fa7e 100644 --- a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile @@ -168,6 +168,15 @@ espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PREFETCH_PROMOTE [when=S && ATTR_CHIP_EC_ ON; } +# Dis Spec Ops for DCBFs (HW414958) dd1 and dd2 +ispy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_SPEC_OP [when=S] { + spyv; + # Bit 45 of 33:51 field is DCBF type + # 3333333444444444455 + # 3456789012345678901 + 0b0000000000001000000; +} + ################# # DD2 WORKAROUNDS ################# diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C index 124bf7bb1..4fa0017d3 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C @@ -35,6 +35,7 @@ constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_8 = 8; constexpr uint64_t literal_25 = 25; constexpr uint64_t literal_0b001111 = 0b001111; +constexpr uint64_t literal_0b0000000000001000000 = 0b0000000000001000000; constexpr uint64_t literal_0b0001100000000 = 0b0001100000000; constexpr uint64_t literal_1350 = 1350; constexpr uint64_t literal_1000 = 1000; @@ -110,6 +111,7 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0 constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE1_DISABLE_FP_M_BIT_ON = 0x1; l_scom_buffer.insert<10, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE1_DISABLE_FP_M_BIT_ON ); + l_scom_buffer.insert<33, 19, 45, uint64_t>(literal_0b0000000000001000000 ); FAPI_TRY(fapi2::putScom(TGT0, 0x5010812ull, l_scom_buffer)); } { |
