diff options
| author | Adam Muhle <armuhle@us.ibm.com> | 2013-03-07 15:58:06 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-04-09 14:34:19 -0500 |
| commit | fc990817b98c3bb16c369e365a274ef63a0586c5 (patch) | |
| tree | c5ef3e2eb9664b10b05507ac4f5c320ea43dbda1 /src | |
| parent | 63b344dd0fcbd2318a8fd46978970a08f3eb9ca9 (diff) | |
| download | talos-hostboot-fc990817b98c3bb16c369e365a274ef63a0586c5.tar.gz talos-hostboot-fc990817b98c3bb16c369e365a274ef63a0586c5.zip | |
First pass of OCC Procedures in Hostboot
This is a first-pass implementation of the OCC procedures
in Hostboot. OCC is not enabled with this commit.
Change-Id: Id8dcd49ee4a54f208e95d43e6f1f7a1d22e6742c
RTC: 51076
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3643
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
38 files changed, 12521 insertions, 4 deletions
diff --git a/src/include/usr/hwpf/hwp/occ.H b/src/include/usr/hwpf/hwp/occ.H new file mode 100644 index 000000000..fd59137d4 --- /dev/null +++ b/src/include/usr/hwpf/hwp/occ.H @@ -0,0 +1,35 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/include/usr/hwpf/hwp/occ.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef OCC_H_ +#define OCC_H_ + +namespace OCC { + + errlHndl_t loadnStartOcc(uint64_t i_homer_addr, + uint64_t i_common_addr, + TARGETING::Target* i_target); + + +} //end OCC namespace + +#endif diff --git a/src/include/usr/vmmconst.h b/src/include/usr/vmmconst.h index 1c5ae6d01..29e82c48d 100644 --- a/src/include/usr/vmmconst.h +++ b/src/include/usr/vmmconst.h @@ -134,4 +134,16 @@ enum BlockPriority #define DUMP_TEST_MEMORY_SIZE (4*MEGABYTE) +//TODO RTC: 35752 - Merge SLW and OCC into simgle HOMER Offset +//Note: OCC base image must be at 4MB offset, COMMON data must be at 8MB offset. +/** Physical Memory for OCC images - 1MB/chip * 4 chips */ +#define VMM_OCC_IMAGE_BASE_ADDR (72*MEGABYTE) +#define VMM_OCC_IMAGE_BASE_SIZE (4*MEGABYTE) + +/** Physical Memory for OCC common space - 8MB total */ +#define VMM_OCC_COMMON_ADDR (80*MEGABYTE) +#define VMM_OCC_COMMON_SIZE (8*MEGABYTE) + + + #endif /* _VMMCONST_H */ diff --git a/src/makefile b/src/makefile index 36edf7724..89b04ba2a 100644 --- a/src/makefile +++ b/src/makefile @@ -55,7 +55,7 @@ EXTENDED_MODULES = targeting ecmddatabuffer fapi hwp plat \ mdia mbox prdf bus_training \ activate_powerbus build_winkle_images \ core_activate dram_initialization edi_ei_initialization \ - establish_system_smp \ + establish_system_smp occ\ nest_chiplets start_payload thread_activate slave_sbe \ attn runtime ibscom dump @@ -83,8 +83,7 @@ include ${ROOTPATH}/src/usr/diag/prdf/common/prd_ruletable.mk hbicore_DATA_MODULES = sample.if p8.dmi.scom.if cen.dmi.scom.if \ p8.fbc.scom.if mbs_def.if mba_def.if cen_ddrphy.if \ p8.pe.phase1.scom.if p8.pe.phase2.scom.if \ - dimmspd.dat centaur.sbe_pnor.bin procmvpd.dat \ - ${PRDR_RULE_TABLE_TARGETS} \ + centaur.sbe_pnor.bin ${PRDR_RULE_TABLE_TARGETS} \ p8.abus.scom.if p8.xbus.scom.if p8.mcs.scom.if \ p8.as.scom.if p8.nx.scom.if p8.dmi.custom.scom.if \ cen.dmi.custom.scom.if p8.abus.custom.scom.if \ diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile index 034c8bc71..2e8d7357e 100644 --- a/src/usr/hwpf/hwp/makefile +++ b/src/usr/hwpf/hwp/makefile @@ -47,7 +47,7 @@ OBJS = fapiTestHwp.o \ SUBDIRS = dmi_training.d sbe_centaur_init.d mc_config.d \ dram_training.d activate_powerbus.d build_winkle_images.d \ core_activate.d dram_initialization.d edi_ei_initialization.d \ - establish_system_smp.d bus_training.d \ + establish_system_smp.d bus_training.d occ.d\ nest_chiplets.d start_payload.d thread_activate.d slave_sbe.d include mvpd_accessors/mvpd.mk diff --git a/src/usr/hwpf/hwp/occ/makefile b/src/usr/hwpf/hwp/occ/makefile new file mode 100644 index 000000000..d4a8fe78d --- /dev/null +++ b/src/usr/hwpf/hwp/occ/makefile @@ -0,0 +1,74 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/hwpf/hwp/occ/makefile $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2013 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG +ROOTPATH = ../../../../.. + +MODULE = occ + +## support for Targeting and fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp + +## pointer to common HWP files +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include + +## pointer to already consumed procedures. +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar + +## NOTE: add the base istep dir here. +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ + +## Include sub dirs +## NOTE: add a new EXTRAINCDIR when you add a new HWP +## EXAMPLE: +## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ/<HWP_dir> +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ/occ_procedures + + +## NOTE: add new object files when you add a new HWP +OBJS = occ.o \ + p8_pba_init.o \ + p8_pm_init.o \ + p8_pcbs_init.o \ + p8_pmc_init.o \ + p8_poregpe_init.o \ + p8_oha_init.o \ + p8_ocb_init.o \ + p8_pss_init.o \ + p8_occ_control.o \ + p8_occ_sram_init.o \ + p8_pm_firinit.o \ + p8_pm_oha_firinit.o \ + p8_pm_pcbs_firinit.o \ + p8_pm_occ_firinit.o \ + p8_pm_pba_firinit.o \ + p8_pm_pmc_firinit.o + +## NOTE: add a new directory onto the vpaths when you add a new HWP +## EXAMPLE: +# VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/occ/<HWP_dir> +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/occ/occ_procedures + + +include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/occ/occ.C b/src/usr/hwpf/hwp/occ/occ.C new file mode 100644 index 000000000..07a270cbe --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ.C @@ -0,0 +1,225 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include <stdint.h> + +#include <initservice/taskargs.H> +#include <errl/errlentry.H> + +#include <devicefw/userif.H> +#include <sys/misc.h> +#include <sys/mm.h> +#include <vmmconst.h> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +// fapi support +#include <fapi.H> +#include <fapiPlatHwpInvoker.H> +#include <hwpf/plat/fapiPlatTrace.H> +#include <hwpf/hwpf_reasoncodes.H> + +// Procedures +#include <p8_pba_init.H> +#include <p8_occ_control.H> +#include <p8_pba_bar_config.H> +#include <p8_pm_init.H> +#include <p8_pm_firinit.H> + +extern trace_desc_t* g_fapiTd; + +namespace OCC +{ + + errlHndl_t loadOCCImageToHomer(uint64_t i_homer_addr ) + { + errlHndl_t l_errl = NULL; + + do { + //RTC: 51076 - Implement DMA message passing to + // get OCC image from FSP. + + }while(0); + + return l_errl; + } + + errlHndl_t loadnStartOcc(uint64_t i_homer_addr, + uint64_t i_common_addr, + TARGETING::Target* i_target) + { + errlHndl_t l_errl = NULL; + + TRACDCOMP( g_fapiTd, + "loadnStartOcc entry" ); + + + do { + + // cast OUR type of target to a FAPI type of target. + const fapi::Target l_fapiTarg(fapi::TARGET_TYPE_PROC_CHIP, + (const_cast<TARGETING::Target*>(i_target))); + + + //============================== + //Setup for OCC Load + //============================== + + //TODO: put this const in the common location with HOMER struct + //RTC: 50987 + // BAR0 is the Entire HOMER (start of HOMER contains OCC base Image) + // Bar size is in MB, obtained value of 4MB from Greg Still + const uint32_t bar0_size_MB = 4; + FAPI_INVOKE_HWP( l_errl, + p8_pba_bar_config, + l_fapiTarg, + 0, i_homer_addr, bar0_size_MB, + PBA_CMD_SCOPE_NODAL ); + + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"Bar0 config failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + + //TODO: put this const in the common location with HOMER struct + //RTC: 50987 + // BAR3 is the OCC Common Area + // Bar size is in MB, obtained value of 8MB from Tim Hallett + const uint32_t bar3_size_MB = 8; + FAPI_INVOKE_HWP( l_errl, + p8_pba_bar_config, + l_fapiTarg, + 3, i_common_addr, bar3_size_MB, + PBA_CMD_SCOPE_NODAL ); + + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"Bar3 config failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + + //TODO: This flow needs to be updated along with procedure refresh + //RTC: 68461 + // Config path + // p8_pm_init.C enum: PM_CONFIG + FAPI_INVOKE_HWP( l_errl, + p8_pm_init, + l_fapiTarg, + PM_CONFIG ); + + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"p8_pm_init, config failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + + // Init path + // p8_pm_init.C enum: PM_INIT + FAPI_INVOKE_HWP( l_errl, + p8_pm_init, + l_fapiTarg, + PM_INIT ); + + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"p8_pm_init, init failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + TRACFCOMP( g_fapiImpTd, + INFO_MRK"OCC Finished: p8_pm_init.C enum: PM_INIT" ); + + // Firinit + // p8_pm_firinit.C + FAPI_INVOKE_HWP( l_errl, + p8_pm_firinit, + l_fapiTarg ); + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"p8_pm_firinit, failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + + //============================== + //Load the OCC HOMER image + //============================== + l_errl = loadOCCImageToHomer( i_homer_addr ); + if( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, ERR_MRK"loading images failed!" ); + break; + } + + //TODO RTC:50987 - Fill in OCC data areas in HOMER. See Story + // 49595 for details. + + //============================== + //Start the OCC image + //============================== + FAPI_INVOKE_HWP( l_errl, + p8_occ_control, + l_fapiTarg, + PPC405_RESET_OFF, + PPC405_BOOT_MEM ); + + if ( l_errl != NULL ) + { + TRACFCOMP( g_fapiImpTd, + ERR_MRK"occ_control failed!" ); + l_errl->collectTrace(FAPI_TRACE_NAME,256); + l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + + break; + } + + } while(0); + + TRACDCOMP( g_fapiTd, + "loadnStartOcc Exit" ); + + return l_errl; + } + +} //end OCC namespace diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C new file mode 100755 index 000000000..c85979e01 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C @@ -0,0 +1,605 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_ocb_init.C,v 1.3 2012/10/11 13:49:00 jimyac Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_ocb_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Jim Yacynych Email: jimyac@us.ibm.com +// *! + +/// \file p8_ocb_init.C +/// \brief Setup and configure OCB channels +/// +/// \todo add support for linear window mode +/// +/// High-level procedure flow: +/// \verbatim +/// o if mode = PM_CONFIG +/// o placeholder - currently do nothing +/// o if mode = PM_INIT +/// o placeholder - currently do nothing +/// o if mode = PM_RESET +/// o reset each register in each OCB channel to its scan0-flush state +/// o if mode = PM_SETUP_PIB or PM_SETUP_ALL +/// o process parameters passed to procedure +/// o Set up channel control/status register based on passed parameters (OCBCSRn) +/// o Set Base Address Register +/// o linear streaming & non-streaming => OCBARn +/// o push queue => OCBSHBRn (only if PM_SETUP_ALL) +/// o pull queue => OCBSLBRn (only if PM_SETUP_ALL) +/// o Set up queue control and status register (only if PM_SETUP_ALL) +/// o push queue => OCBSHCSn +/// o pull queue => OCBSLCSn +/// +/// Procedure Prereq: +/// o System clocks are running +/// \endverbatim +//------------------------------------------------------------------------------ + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_ocb_init.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- +ReturnCode proc_ocb_reset(const Target& i_target); + +ReturnCode proc_ocb_setup(const Target& i_target, const uint8_t i_ocb_chan, + const uint8_t i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_upd_reg, + const uint8_t i_ocb_q_len, + const uint8_t i_ocb_ouflow_en, + const uint8_t i_ocb_itp_type); + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- +/// \param[in] i_target => Chip Target +/// \param[in] i_mode => PM_CONFIG, PM_RESET, PM_INIT, or PM_SETUP +/// \param[in] i_ocb_chan => select channel 0-3 to set up +/// \param[in] i_ocb_type => 0=indirect 1=linear stream 2=circular push 3=circular pull +/// \param[in] i_ocb_bar => 32-bit channel base address (29 bits + "000") +/// \param[in] i_ocb_q_len => 0-31 length of push or pull queue in (queue_length + 1) * 8B +/// \param[in] i_ocb_ouflow_en => 0=disabled 1=enabled +/// \param[in] i_ocb_itp_type => 0=full 1=not full 2=empty 3=not empty +/// \retval FAPI_RC_SUCCESS +/// \retval ERROR defined in xml + +ReturnCode +p8_ocb_init(const Target& i_target, const uint32_t i_mode, + const uint8_t i_ocb_chan, + const uint8_t i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const uint8_t i_ocb_ouflow_en, + const uint8_t i_ocb_itp_type) +{ + ReturnCode rc; + uint8_t upd_reg = OCB_UPD_PIB_REG; + + FAPI_INF("Executing p8_ocb_init ...."); + + // ------------------------------------------------------------------------------- + // Config : perform translation of any Platform Attributes into Feature Attributes + // that are applied during Initalization + // ------------------------------------------------------------------------------- + if (i_mode == PM_CONFIG) { + FAPI_INF(" *** Configuring OCB Indirect Channels 0-3"); + } + + // -------------------------------------------------------------- + // Init : perform order or dynamic operations to initialize + // the PMC using necessary Platform or Feature attributes. + // -------------------------------------------------------------- + else if (i_mode == PM_INIT) { + FAPI_INF(" *** Initializing OCB Indirect Channels 0-3"); + } + + // -------------------------------------------------------------- + // Reset : perform order or dynamic operations to initialize + // the PMC using necessary Platform or Feature attributes. + // -------------------------------------------------------------- + else if (i_mode == PM_RESET) { + FAPI_INF(" *** Resetting OCB Indirect Channels 0-3"); + rc = proc_ocb_reset(i_target); + } + + // -------------------------------------------------------------- + // Setup : perform user setup of an indirect channel + // -------------------------------------------------------------- + else if (i_mode == PM_SETUP_PIB || i_mode == PM_SETUP_ALL ) { + FAPI_INF(" *** Setup OCB Indirect Channel %d",i_ocb_chan); + + if (i_mode == PM_SETUP_ALL) + upd_reg = OCB_UPD_PIB_OCI_REG; + + // call function to setup ocb channel + rc = proc_ocb_setup(i_target , i_ocb_chan, + i_ocb_type, + i_ocb_bar, + upd_reg, + i_ocb_q_len, + i_ocb_ouflow_en, + i_ocb_itp_type); + } + else { + FAPI_ERR("Unknown mode passed to proc_ocb_init. Mode %x ....\n", i_mode); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_MODE); + } + + FAPI_INF("Completing p8_ocb_init ...."); + + return rc; +} + +// --------------------- +// function definintions +// --------------------- +/// \brief Setup specified channel to type specified +/// \param[in] i_target => Chip Target +/// \param[in] i_ocb_chan => select channel 0-3 to set up +/// \param[in] i_ocb_type => 0=indirect 1=linear stream 2=circular push 3=circular pull +/// \param[in] i_ocb_bar => 32-bit channel base address (29 bits + "000") +/// \param[in] i_ocb_upd_reg => 0=update PIB registers only 1=update PIB & OCI registers +/// \param[in] i_ocb_q_len => 0-31 length of push or pull queue in (queue_length + 1) * 8B +/// \param[in] i_ocb_ouflow_en => 0=disabled 1=enabled +/// \param[in] i_ocb_itp_type => 0=full 1=not full 2=empty 3=not empty + +ReturnCode proc_ocb_setup(const Target& i_target, const uint8_t i_ocb_chan, + const uint8_t i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_upd_reg, + const uint8_t i_ocb_q_len, + const uint8_t i_ocb_ouflow_en, + const uint8_t i_ocb_itp_type) +{ + ReturnCode rc; + uint32_t l_ecmdRc = 0; + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask_or(64); + ecmdDataBufferBase mask_and(64); + + uint32_t OCBASE = 0x0; + + // -------------------------------------------- + // verify paramater values for queues are valid + // -------------------------------------------- + if (i_ocb_type == OCB_TYPE_PUSHQ || i_ocb_type == OCB_TYPE_PULLQ) { + + // check queue_len + if (i_ocb_q_len > 31) { + FAPI_ERR("Bad Queue Length Passed to Procedure => %d", i_ocb_q_len); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_Q_LENGTH_PARM); + return rc; + } + + // check queue_itp_type + if (!(i_ocb_itp_type <= OCB_Q_ITPTYPE_NOTEMPTY)) { + FAPI_ERR("**** ERROR : Bad Interrupt Type Passed to Procedure => %d", i_ocb_itp_type); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_ITP_TYPE_PARM); + return rc; + } + + // check queue_overunderflow_en + if (i_ocb_ouflow_en != OCB_Q_OUFLOW_NULL && i_ocb_ouflow_en != OCB_Q_OUFLOW_EN && i_ocb_ouflow_en != OCB_Q_OUFLOW_DIS) { + FAPI_ERR("**** ERROR : Bad Queue Over/Under Flow Enable Passed to Procedure => %d", i_ocb_ouflow_en); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_Q_OVER_UNDERFLOW_PARM); + return rc; + } + } + + // check channel number + if (i_ocb_chan > OCB_CHAN3) { + FAPI_ERR("**** ERROR : Bad Channel Number Passed to Procedure => %d", i_ocb_chan); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_CHAN_NUM_PARM); + return rc; + } + + // check valid channel type for channel3 + if (i_ocb_chan == OCB_CHAN3 && !(i_ocb_type == OCB_TYPE_LIN || i_ocb_type == OCB_TYPE_LINSTR) ) { + FAPI_ERR("**** ERROR : Bad Channel Type for Channel 3 Passed to Procedure => %d", i_ocb_type); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_CHAN3_TYPE_PARM); + return rc; + } + + // -------------------------------------------------------------------- + // Setup Status and Control Register (OCBCSRn, OCBCSRn_AND, OCBCSRn_OR) + // bit 2 => pull_read_underflow_en (0=disabled 1=enabled) + // bit 3 => push_write_overflow_en (0=disabled 1=enabled) + // bit 4 => ocb_stream_mode (0=disabled 1=enabled) + // bit 5 => ocb_stream_type (0=linear 1=circular) + // -------------------------------------------------------------------- + l_ecmdRc |= mask_or.flushTo0(); + l_ecmdRc |= mask_and.flushTo1(); + + if (i_ocb_type == OCB_TYPE_LIN) { // linear non-streaming + l_ecmdRc |= mask_and.clearBit(4); + l_ecmdRc |= mask_and.clearBit(5); + } + else if (i_ocb_type == OCB_TYPE_LINSTR) { // linear streaming + l_ecmdRc |= mask_or.setBit(4); + l_ecmdRc |= mask_and.clearBit(5); + } + else if (i_ocb_type == OCB_TYPE_CIRC) { // circular + l_ecmdRc |= mask_or.setBit(4); + l_ecmdRc |= mask_or.setBit(5); + } + else if (i_ocb_type == OCB_TYPE_PUSHQ) { // push queue + l_ecmdRc |= mask_or.setBit(4); + l_ecmdRc |= mask_or.setBit(5); + + if (i_ocb_ouflow_en == OCB_Q_OUFLOW_EN) { + l_ecmdRc |= mask_or.setBit(3); + } + else if (i_ocb_ouflow_en == OCB_Q_OUFLOW_DIS) { + l_ecmdRc |= mask_and.clearBit(3); + } + + } + else if (i_ocb_type == OCB_TYPE_PULLQ) { // pull queue + l_ecmdRc |= mask_or.setBit(4); + l_ecmdRc |= mask_or.setBit(5); + + if (i_ocb_ouflow_en == OCB_Q_OUFLOW_EN) { + l_ecmdRc |= mask_or.setBit(2); + } + else if (i_ocb_ouflow_en == OCB_Q_OUFLOW_DIS) { + l_ecmdRc |= mask_and.clearBit(2); + } + + } + else { + FAPI_ERR("**** ERROR : Bad Channel Type Passed to Procedure => %d", i_ocb_type); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCBINIT_BAD_CHAN_TYPE_PARM); + return rc; + } + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Status & Control", i_ocb_chan); + + // write using OR mask + rc = fapiPutScom(i_target, OCBCSRn_OR[i_ocb_chan] , mask_or); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel Status & Control"); + return rc; + } + + // write using AND mask + rc = fapiPutScom(i_target, OCBCSRn_AND[i_ocb_chan] , mask_and); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel Status & Control"); + return rc; + } + + // -------------------------------------------------------------------------------------- + // set address base register for linear mode + // bits 0:31 => 32 bit base address + // bits 0:1 => OCI region (00=PBA 01=Registers 10=reserved 11=SRAM) + // bits 29:31 => "000" + // -------------------------------------------------------------------------------------- + if (!(i_ocb_type == OCB_TYPE_NULL || i_ocb_type == OCB_TYPE_CIRC)) { // don't update bar if type null or circular + + if (i_ocb_type == OCB_TYPE_LIN || i_ocb_type == OCB_TYPE_LINSTR) { + OCBASE = OCBARn[i_ocb_chan]; + } + else if (i_ocb_type == OCB_TYPE_PUSHQ) { + OCBASE = OCBSHBRn[i_ocb_chan]; + } else { // else PULL -- FIXME - need Linear Window Type Implemented + OCBASE = OCBSLBRn[i_ocb_chan]; + } + + l_ecmdRc |= data.flushTo0(); + l_ecmdRc |= data.setWord(0, i_ocb_bar); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Base Address", i_ocb_chan); + + rc = fapiPutScom(i_target, OCBASE , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel Base Address"); + return rc; + } + + } + // ------------------------------------- + // set up push queue control register + // bits 4:5 => push interrupt action + // 00=full + // 01=not full + // 10=empty + // 11=not empty + // bits 6:8 => push queue length + // bit 31 => push queue enable + // ------------------------------------- + if (i_ocb_type == OCB_TYPE_PUSHQ && i_ocb_upd_reg == OCB_UPD_PIB_OCI_REG) { + l_ecmdRc |= data.flushTo0(); + l_ecmdRc |= data.insertFromRight(i_ocb_q_len,6,5); + l_ecmdRc |= data.insertFromRight(i_ocb_itp_type,4,2); + l_ecmdRc |= data.setBit(31); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Push Control/Status Address", i_ocb_chan); + + rc = fapiPutScom(i_target, OCBSHCSn[i_ocb_chan] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel Push Address"); + return rc; + } + + } + + // ------------------------------------- + // set up pull queue control register + // bits 4:5 => pull interrupt action + // 00=full + // 01=not full + // 10=empty + // 11=not empty + // bits 6:8 => pull queue length + // bit 31 => pull queue enable + // ------------------------------------- + if (i_ocb_type == OCB_TYPE_PULLQ && i_ocb_upd_reg == OCB_UPD_PIB_OCI_REG) { + l_ecmdRc |= data.flushTo0(); + l_ecmdRc |= data.insertFromRight(i_ocb_q_len,6,5); + l_ecmdRc |= data.insertFromRight(i_ocb_itp_type,4,2); + l_ecmdRc |= data.setBit(31); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Pull Control/Status Address", i_ocb_chan); + + rc = fapiPutScom(i_target, OCBSLCSn[i_ocb_chan] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel Pull Address"); + return rc; + } + + } + + // -------------------------------- + // Print Channel Configuration Info + // -------------------------------- + FAPI_IMP("-----------------------------------------------------"); + FAPI_IMP("OCB Channel Configuration "); + FAPI_IMP("-----------------------------------------------------"); + FAPI_IMP(" channel number => %d ", i_ocb_chan); + FAPI_IMP(" channel type => %d ", i_ocb_type); + + if (i_ocb_type == OCB_TYPE_PUSHQ || i_ocb_type == OCB_TYPE_PULLQ) { + FAPI_IMP(" queue length => %d ", i_ocb_q_len); + FAPI_IMP(" interrupt type => %d ", i_ocb_itp_type); + + if (i_ocb_type == OCB_TYPE_PUSHQ) { + FAPI_IMP(" push write overflow enable => %d ", i_ocb_ouflow_en); + } + else { + FAPI_IMP(" pull write overflow enable => %d ", i_ocb_ouflow_en); + } + + } + + FAPI_IMP(" channel base address => 0x%08X ", i_ocb_bar); + FAPI_IMP("-----------------------------------------------------"); + + return rc; +} // end proc_ocb_setup + + +/// \brief Reset OCB Channels to default state (ie. scan-0 flush state) +/// \param[in] i_target => Chip Target + +ReturnCode proc_ocb_reset(const Target& i_target) { + ReturnCode rc; + uint32_t l_ecmdRc = 0; + + ecmdDataBufferBase data(64); + uint8_t i = 0; + + // --------------------------------------- + // Loop over PIB Registers in Channels 0-3 + // --------------------------------------- + for (i = 0; i <= 3; i++) { + l_ecmdRc |= data.flushTo0(); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + // clear out OCBAR + rc = fapiPutScom(i_target, OCBARn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d BAR Register", i); + return rc; + } + + // clear out OCBCSR + // - clear out using AND + // - set bit 5 (circular mode) using OR (for channels 0-2) + // - set bit 4 (stream mode) using OR (for channel 3) + rc = fapiPutScom(i_target, OCBCSRn_AND[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Control & Status AND Register", i); + return rc; + } + + if (i == 3) + l_ecmdRc |= data.setBit(4); + else + l_ecmdRc |= data.setBit(5); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiPutScom(i_target, OCBCSRn_OR[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Control & Status OR Register", i); + return rc; + } + + l_ecmdRc |= data.flushTo0(); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + // clear out Error Status + rc = fapiPutScom(i_target, OCBESRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Error Status Register", i); + return rc; + } + }// end for loop + + // --------------------------------------- + // Loop over OCI Registers in Channels 0-2 + // --------------------------------------- + for (i = 0; i <= 2; i++) { + l_ecmdRc |= data.flushTo0(); + + // clear out Pull Base + rc = fapiPutScom(i_target, OCBSLBRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Pull Base Register", i); + return rc; + } + + // clear out Push Base + rc = fapiPutScom(i_target, OCBSHBRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Push Base Register", i); + return rc; + } + + // clear out Pull Control & Status + rc = fapiPutScom(i_target, OCBSLCSn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Pull Control & Status Register", i); + return rc; + } + + // clear out Push Control & Status + rc = fapiPutScom(i_target, OCBSHCSn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Push Control & Status Register", i); + return rc; + } + + // clear out Stream Error Status + rc = fapiPutScom(i_target, OCBSESn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Stream Error Status Register", i); + return rc; + } + + // clear out Untrusted Control + rc = fapiPutScom(i_target, OCBICRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Untrusted Control Register", i); + return rc; + } + + // clear out Linear Window Control + rc = fapiPutScom(i_target, OCBLWCRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Linear Window Control Register", i); + return rc; + } + + // clear out Linear Window Base + // - set bits 2:9 + l_ecmdRc |= data.setWord(0, 0x3FC00000); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiPutScom(i_target, OCBLWSBRn[i] , data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCB Channel %d Linear Window Base Register", i); + return rc; + } + } // end for loop + + return rc; +} + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H new file mode 100755 index 000000000..ff43dac94 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H @@ -0,0 +1,132 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +#ifndef _P8_OCB_INIT_H_ +#define _P8_OCB_INIT_H_ + +#include <fapi.H> +#include "p8_pm.H" + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_ocb_init_FP_t) (const fapi::Target&, + const uint32_t, + const uint8_t, + const uint8_t, + const uint32_t, + const uint8_t, + const uint8_t, + const uint8_t); + +extern "C" { + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \brief Configure OCB Channels based on mode and parameters passed +/// \param[in] i_target => Chip Target +/// \param[in] i_mode => PM_CONFIG, PM_RESET, PM_INIT, or PM_SETUP +/// \param[in] i_ocb_chan => select channel 0-3 to set up +/// \param[in] i_ocb_type => 0=indirect 1=linear stream 2=circular push 3=circular pull +/// \param[in] i_ocb_bar => 32-bit channel base address (29 bits + "000") +/// \param[in] i_ocb_q_len => 0-31 length of push or pull queue in (queue_length + 1) * 8B +/// \param[in] i_ocb_ouflow_en => 0=disabled 1=enabled +/// \param[in] i_ocb_itp_type => 0=full 1=not full 2=empty 3=not empty + +fapi::ReturnCode p8_ocb_init(const fapi::Target& i_target, + const uint32_t i_mode, + const uint8_t i_ocb_chan, + const uint8_t i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const uint8_t i_ocb_ouflow_en, + const uint8_t i_ocb_itp_type); + +// --------- +// Constants +// --------- +const uint8_t OCB_CHAN0 = 0x00; +const uint8_t OCB_CHAN1 = 0x01; +const uint8_t OCB_CHAN2 = 0x02; +const uint8_t OCB_CHAN3 = 0x03; + +const uint8_t OCB_TYPE_NULL = 0x00; +const uint8_t OCB_TYPE_LIN = 0x01; +const uint8_t OCB_TYPE_LINSTR = 0x02; +const uint8_t OCB_TYPE_LINWIN = 0x03; +const uint8_t OCB_TYPE_CIRC = 0x04; +const uint8_t OCB_TYPE_PUSHQ = 0x05; +const uint8_t OCB_TYPE_PULLQ = 0x06; + +const uint8_t OCB_UPD_PIB_REG = 0x00; +const uint8_t OCB_UPD_PIB_OCI_REG = 0x01; + +const uint8_t OCB_Q_OUFLOW_NULL = 0x00; +const uint8_t OCB_Q_OUFLOW_EN = 0x01; +const uint8_t OCB_Q_OUFLOW_DIS = 0x02; + +const uint8_t OCB_Q_ITPTYPE_NULL = 0x00; +const uint8_t OCB_Q_ITPTYPE_FULL = 0x01; +const uint8_t OCB_Q_ITPTYPE_NOTFULL = 0x02; +const uint8_t OCB_Q_ITPTYPE_EMPTY = 0x03; +const uint8_t OCB_Q_ITPTYPE_NOTEMPTY = 0x04; + +const uint8_t OCB_UNSECMASTER_NULL = 0x00; +const uint8_t OCB_UNSECMASTER_ALLOW = 0x01; +const uint8_t OCB_UNSECMASTER_NOTALLOW = 0x02; + +// channel register arrrays +const uint64_t OCBARn[4] = {OCB0_ADDRESS_0x0006B010, OCB1_ADDRESS_0x0006B030, OCB2_ADDRESS_0x0006B050, OCB3_ADDRESS_0x0006B070 }; +const uint64_t OCBCSRn[4] = {OCB0_STATUS_CONTROL_0x0006B011, OCB1_STATUS_CONTROL_0x0006B031, OCB2_STATUS_CONTROL_0x0006B051, OCB3_STATUS_CONTROL_0x0006B071 }; +const uint64_t OCBCSRn_AND[4] = {OCB0_STATUS_CONTROL_AND_0x0006B012, OCB1_STATUS_CONTROL_AND_0x0006B032, OCB2_STATUS_CONTROL_AND_0x0006B052, OCB3_STATUS_CONTROL_AND_0x0006B072 }; +const uint64_t OCBCSRn_OR[4] = {OCB0_STATUS_CONTROL_OR_0x0006B013, OCB1_STATUS_CONTROL_OR_0x0006B033, OCB2_STATUS_CONTROL_OR_0x0006B053, OCB3_STATUS_CONTROL_OR_0x0006B073 }; +const uint64_t OCBESRn[4] = {OCB0_ERROR_STATUS_0x0006B014, OCB1_ERROR_STATUS_0x0006B034, OCB2_ERROR_STATUS_0x0006B054, OCB3_ERROR_STATUS_0x0006B074 }; +const uint64_t OCBSLBRn[3] = {OCB0_PULL_BASE_0x0006A200, OCB1_PULL_BASE_0x0006A210, OCB2_PULL_BASE_0x0006A220 }; +const uint64_t OCBSHBRn[3] = {OCB0_PULL_STATUS_CONTROL_0x0006A201, OCB1_PULL_STATUS_CONTROL_0x0006A211, OCB2_PULL_STATUS_CONTROL_0x0006A221 }; +const uint64_t OCBSLCSn[3] = {OCB0_PUSH_BASE_0x0006A203, OCB1_PUSH_BASE_0x0006A213, OCB2_PUSH_BASE_0x0006A223 }; +const uint64_t OCBSHCSn[3] = {OCB0_PUSH_STATUS_CONTROL_0x0006A204, OCB1_PUSH_STATUS_CONTROL_0x0006A214, OCB2_PUSH_STATUS_CONTROL_0x0006A224 }; +const uint64_t OCBSESn[3] = {OCB0_STREAM_ERR_STATUS_0x0006A206, OCB1_STREAM_ERR_STATUS_0x0006A216, OCB2_STREAM_ERR_STATUS_0x0006A226 }; + +const uint64_t OCBICRn[3] = {OCB0_UNTRUSTED_CONTROL_0x0006A207, OCB1_UNTRUSTED_CONTROL_0x0006A217, OCB2_UNTRUSTED_CONTROL_0x0006A227 }; // allow unsecure master +const uint64_t OCBLWCRn[3] = {OCB0_LIN_WINDOW_CONTROL_0x0006A208, OCB1_LIN_WINDOW_CONTROL_0x0006A218, OCB2_LIN_WINDOW_CONTROL_0x0006A228 }; // linear window write control +const uint64_t OCBLWSBRn[3] = {OCB0_LIN_WINDOW_BASE_0x0006A20C, OCB1_LIN_WINDOW_BASE_0x0006A21C, OCB2_LIN_WINDOW_BASE_0x0006A22C }; // linear window write base + +} // extern "C" + +#endif + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C new file mode 100755 index 000000000..a74e51013 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C @@ -0,0 +1,258 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_occ_control.C,v 1.1 2012/08/21 16:17:31 jimyac Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_control.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Jim Yacynych Email: jimyac@us.ibm.com +// *! + +/// \file p8_occ_control.C +/// \brief Initialize boot vector registers and control PPC405 reset + +/// \todo +/// +/// High-level procedure flow: +/// \verbatim +/// o process parameters passed to procedure +/// o Initialize boot vector registers in SRAM (SRBV0,1,2,3) if (i_ppc405_boot_ctrl != PPC405_BOOT_NULL) +/// o initialize SRBV0,1,2 with all 0's (illegal instructions) +/// o initialize SRBV0 per passed parameter (i_ppc405_boot_ctrl) +/// o initialize to Branch Absolute 0xFFF80010 if i_ppc405_boot_ctrl = PPC405_BOOT_SRAM +/// o initialize to Branch Absolute 0x00000010 if i_ppc405_boot_ctrl = PPC405_BOOT_MEM +/// o initialize to Branch Relative -16 if i_ppc405_boot_ctrl = PPC405_BOOT_OLD +/// o Write PPC405 reset bit per parameteri_ppc405_reset_ctrl (OCR) +/// o if PPC405_RESET_NULL , do nothing +/// o if PPC405_RESET_OFF , write reset bit to 0 (PPC405 not reset) +/// o if PPC405_RESET_ON , write reset bit to 1 (PPC405 reset) +/// Procedure Prereq: +/// o System clocks are running +/// \endverbatim +//------------------------------------------------------------------------------ + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_occ_control.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +/// \param[in] i_target => Chip Target +/// \param[in] i_ppc405_reset_ctrl => PPC405_RESET_NULL : do nothing PPC405_RESET_OFF : set ppc405 reset=0 PPC405_RESET_ON : set ppc405 reset=1 +/// \param[in] i_ppc405_boot_ctrl => PPC405_BOOT_NULL : do nothing PPC405_BOOT_SRAM : boot from sram PPC405_BOOT_MEM : boot from memory PPC405_BOOT_OLD : boot from sram (OLD tests) + +/// \retval FAPI_RC_SUCCESS +/// \retval ERROR defined in xml + +fapi::ReturnCode +p8_occ_control(const Target& i_target, const uint8_t i_ppc405_reset_ctrl, const uint8_t i_ppc405_boot_ctrl) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_ecmdRc = 0; + + FAPI_INF("Executing p8_occ_control ...."); + + // ------------------------------------- + // process arguments passed to procedure + // ------------------------------------- + + // check ppc405_reset_ctrl + if (!(i_ppc405_reset_ctrl <= PPC405_RESET_ON) ) { + FAPI_ERR("Bad PPC405 Reset Setting Passed to Procedure => %d", i_ppc405_reset_ctrl); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCC_CONTROL_BAD_405RESET_PARM); + return rc; + } + + // check sram_bv_ctrl + if (!(i_ppc405_boot_ctrl <= PPC405_BOOT_OLD) ) { + FAPI_ERR("Bad Boot Vector Setting Passed to Procedure => %d", i_ppc405_boot_ctrl); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCC_CONTROL_BAD_405BOOT_PARM); + return rc; + } + + // ------------------------------------------------ + // Set up Boot Vector Registers in SRAM + // - set bv0-2 to all 0's (illegal instructions) + // - set bv3 to proper branch instruction + // - boot vector registers + // - OCC_SRAM_BOOT_VEC0_0x00066004 + // - OCC_SRAM_BOOT_VEC1_0x00066005 + // - OCC_SRAM_BOOT_VEC2_0x00066006 + // - OCC_SRAM_BOOT_VEC3_0x00066007 + // ------------------------------------------------- + + l_ecmdRc |= data.flushTo0(); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + // write 0's to bv0-2 + if (i_ppc405_boot_ctrl != PPC405_BOOT_NULL) { + + FAPI_DBG("Writing to Boot Vector0 Register"); + + rc = fapiPutScom(i_target, OCC_SRAM_BOOT_VEC0_0x00066004, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to SRAM Boot Vector0 Register"); + return rc; + } + + FAPI_DBG("Writing to Boot Vector1 Register"); + + rc = fapiPutScom(i_target, OCC_SRAM_BOOT_VEC1_0x00066005, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to SRAM Boot Vector1 Register"); + return rc; + } + + FAPI_DBG("Writing to Boot Vector2 Register"); + + rc = fapiPutScom(i_target, OCC_SRAM_BOOT_VEC2_0x00066006, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to SRAM Boot Vector2 Register"); + return rc; + } + + // write branch instruction to bv3 + if (i_ppc405_boot_ctrl == PPC405_BOOT_SRAM) { + l_ecmdRc |= data.setWord(0, PPC405_BRANCH_SRAM_INSTR); // Branch Absolute 0xFFF80010 => ba 0xfff80010 (boot from sram) + } + else if (i_ppc405_boot_ctrl == PPC405_BOOT_MEM) { + l_ecmdRc |= data.setWord(0, PPC405_BRANCH_MEM_INSTR); // Branch Absolute 0x00000010 => ba 0x00000010 (boot from memory) + } + else { + l_ecmdRc |= data.setWord(0, PPC405_BRANCH_OLD_INSTR); + } + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing to Boot Vector3 Register"); + + rc = fapiPutScom(i_target, OCC_SRAM_BOOT_VEC3_0x00066007, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to SRAM Boot Vector3 Register"); + return rc; + } + } + + // ---------------------------------------------------------- + // Set or Clear PPC405 reset in OCC Control register ( + // OCC_CONTROL_0x0006B000 + // OCC_CONTROL_AND_0x0006B001 + // OCC_CONTROL_OR_0x0006B002 + // + // - bit 0 => 0= ppc405 not in reset 1= ppc405 in reset + // ---------------------------------------------------------- + + if (i_ppc405_reset_ctrl == PPC405_RESET_OFF) { + l_ecmdRc |= data.flushTo1(); + l_ecmdRc |= data.clearBit(0); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing OCC Control Register to clear bit 0 (core_reset)"); + + rc = fapiPutScom(i_target, OCC_CONTROL_AND_0x0006B001, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Control Register => OCC_CONTROL_AND_0x0006B001"); + return rc; + } + } + + if (i_ppc405_reset_ctrl == PPC405_RESET_ON) { + l_ecmdRc |= data.flushTo0(); + l_ecmdRc |= data.setBit(0); + + if (l_ecmdRc) { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Writing OCC Control Register to set bit 0 (core_reset)"); + + rc = fapiPutScom(i_target, OCC_CONTROL_OR_0x0006B002, data); + if (!rc.ok()) { + FAPI_ERR("**** ERROR : Unexpected error encountered in write to OCC Control Register => OCC_CONTROL_OR_0x0006B002"); + return rc; + } + } + + FAPI_INF("Completing p8_occ_control ...."); + + return rc; +} + +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H new file mode 100755 index 000000000..a96336002 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H @@ -0,0 +1,77 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +#ifndef _P8_OCC_CONTROL_H_ +#define _P8_OCC_CONTROL_H_ + +#include <fapi.H> + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_occ_control_FP_t) (const fapi::Target&, + const uint8_t, + const uint8_t); + +extern "C" { + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + +fapi::ReturnCode p8_occ_control(const fapi::Target& i_target, + const uint8_t i_ppc405_reset_ctrl, + const uint8_t i_ppc405_boot_ctrl); +// --------- +// Constants +// --------- +const uint8_t PPC405_RESET_NULL = 0x00; +const uint8_t PPC405_RESET_OFF = 0x01; +const uint8_t PPC405_RESET_ON = 0x02; + +const uint8_t PPC405_BOOT_NULL = 0x00; +const uint8_t PPC405_BOOT_SRAM = 0x01; +const uint8_t PPC405_BOOT_MEM = 0x02; +const uint8_t PPC405_BOOT_OLD = 0x03; + +const uint32_t PPC405_BRANCH_SRAM_INSTR = 0x4BF80012; // Branch Absolute 0xFFF80010 => ba 0xfff80010 (boot from sram) +const uint32_t PPC405_BRANCH_MEM_INSTR = 0x48000012; // Branch Absolute 0x00000010 => ba 0x00000010 (boot from memory) +const uint32_t PPC405_BRANCH_OLD_INSTR = 0x4BFFFFF0; // Branch Relative -16 (boot from sram) + +} // extern "C" + +#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C new file mode 100755 index 000000000..ca6f1e787 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C @@ -0,0 +1,153 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_occ_sram_init.C,v 1.2 2012/10/04 03:41:35 jimyac Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Jim Yacynych Email: ajimyac@us.ibm.com +// *! +// *! General Description: +// *! +// *! The purpose of this procedure is to initialize the OCC SRAM +// *! +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_occ_sram_init.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +// \param[in] i_target Chip target +/// \param[in] mode Control mode for the procedure +/// (PM_CONFIG, PM_INIT, PM_RESET) + +/// \retval PM_SUCCESS if something good happens, +/// \retval PM_OCCSRAM_CODE_BAD* otherwise + +fapi::ReturnCode +p8_occ_sram_init(const Target& i_target, uint32_t mode) +{ + fapi::ReturnCode rc; + //ecmdDataBufferBase data; + //ecmdDataBufferBase mask; + + + FAPI_INF(""); + FAPI_INF("Executing p8_occ_sram_init in mode %x ....\n", mode); + + /// ------------------------------- + /// Configuration: perform translation of any Platform Attributes into Feature Attributes + /// that are applied during Initalization + if (mode == PM_CONFIG) + { + + FAPI_INF("OCC SRAM configuration...\n"); + + FAPI_INF("---> None defined...\n"); + + } + + /// ------------------------------- + /// Initialization: perform order or dynamic operations to initialize + /// the OCC SRAM using necessary Platform or Feature attributes. + else if (mode == PM_INIT) + { + + FAPI_INF("OCC SRAM initialization...\n"); + + } + + /// ------------------------------- + /// Reset: perform reset of OCC SRAM so that it can reconfigured and + /// reinitialized + else if (mode == PM_RESET) + { + + FAPI_INF("OCC SRAM reset...\n"); + + } + + /// ------------------------------- + /// Unsupported Mode + else + { + + FAPI_ERR("Unknown mode passed to p8_occ_sram_init. Mode %x ....\n", mode); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCCSRAM_CODE_BAD_MODE); + + } + + return rc; + +} + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H new file mode 100755 index 000000000..e7cfd9e4a --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_occ_sram_init.H,v 1.1 2012/08/23 16:35:37 jimyac Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_occ_sram_init.H +// *! DESCRIPTION : Initialize the SRAM in the OCC +// *! +// *! OWNER NAME : Jim Yacynych Email: jimyac@us.ibm.com +// *! BACKUP NAME : Greg Still Email: stillgs@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _P8_OCC_SRAM_INIT_H_ +#define _P8_OCC_SRAM_INIT_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_occ_sram_init_FP_t) (const fapi::Target&, uint32_t); + +extern "C" { + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Parameter structure definitions +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \param[in] i_target Chip target +/// \param[in] mode Control mode for the procedure (PM_CONFIG, PM_INIT, PM_RESET) + +/// \retval ECMD_SUCCESS if something good happens, +/// \retval BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_occ_sram_init(const fapi::Target& i_target, uint32_t mode); + + +} // extern "C" + +#endif // _P8_OCC_SRAM_INIT_H_ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C new file mode 100755 index 000000000..c57e9a717 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C @@ -0,0 +1,724 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_oha_init.C,v 1.3 2012/10/04 10:23:00 rmaier Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_oha_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +// *! General Description: +// *! +// *! The purpose of this procedure is to do a initial setup of OHA +// *! +// *! Procedure Prereq: +// *! o completed istep procedure +// *! +//------------------------------------------------------------------------------ +/// \file p8_oha_init.C +/// \brief Setup OHA ( AISS_HANG_DETECT_TIMER, Power Proxy Trace Timer and Low Activity detect range) +/// +/// +/// +/// +/// \version +/// \version -------------------------------------------------------------------------- +/// \version 1.3 rmaier 10/04/12 Replacing genHex*Str function +/// \version -------------------------------------------------------------------------- +/// \version 1.1 rmaier 08/23/12 Renaming proc_ to p8_ +/// \version -------------------------------------------------------------------------- +/// \version 1.13 rmaier 08/02/12 Included review feedback Set 6 +/// \version -------------------------------------------------------------------------- +/// \version 1.12 rmaier 07/17/12 Included review feedback Set 5 +/// \version -------------------------------------------------------------------------- +/// \version 1.11 rmaier 07/17/12 Included review feedback Set 4 +/// \version -------------------------------------------------------------------------- +/// \version 1.10 rmaier 07/13/12 Included new review feedback +/// \version -------------------------------------------------------------------------- +/// \version 1.9 rmaier 05/24/12 Included review feedback +/// \version -------------------------------------------------------------------------- +/// \version 1.8 rmaier 05/15/12 Changed Error return code handling for SCOM access +/// \version -------------------------------------------------------------------------- +/// \version 1.7 rmaier 05/09/12 Removed global variables +/// \version -------------------------------------------------------------------------- +/// \version 1.6 rmaier 04/24/12 Updated Config-mode +/// \version -------------------------------------------------------------------------- +/// \version 1.5 rmaier 03/20/12 Added AISS-reset +/// \version -------------------------------------------------------------------------- +/// \version 1.4 rmaier 03/13/12 Added modes-structure +/// \version -------------------------------------------------------------------------- +/// \version 1.0 rmaier 12/01/11 Initial Version +/// \version --------------------------------------------------------------------------- +/// +/// +/// +/// +/// +/// +/// +/// +/// High-level procedure flow: +/// +/// \verbatim +/// +/// Procedure Prereq: +/// - completed istep procedure +/// +/// +/// loop over all valid chiplets { +/// +/// Setup aiss hang time in oha_mode_reg +/// set aiss_timeout to max -- oha_mode_reg (11:14) , ADR 1002000D (SCOM) +/// -- 9 => longest time 512 ms +/// Setup low activity in oha_low_activity_detect_mode_reg +/// -- oha_low_activity_detect_mode_reg, ADR 10020003 (SCOM) +/// \todo when should we enable the low activity detection or just setup the ranges?? +/// set lad_enable = 1?? +/// set lad_entry = 16 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval +/// set lad_exit = 17 -- bit index of a 24 bit counter based on base counter 0: longest, 23: shortest interval +/// +/// +/// Setup Power Proxy Trace in activity_sample_mode_reg +/// set ppt_int_timer_select -- activity_sample_mode_reg (36:37) ADR 10020000 (SCOM) +/// -- select precounter for ppt timer ( 0=0.25us, 1=0.5us, 2=1us, 3=2us ) +/// +/// if PM_CONFIG { +/// +/// convert_ppt_time() - Convert Power Proxy Trace Time to Power Proxy Trace Time Select and Match feature attributes +/// With ATTR_PM_POWER_PROXY_TRACE_TIMER (binary in nanoseconds) to produce ATTR_PM_PPT_TIMER_MATCH_VALUE and ATTR_PM_PPT_TIMER_TICK +/// 0=0.25us , 1=0.5us, 2=1us, and 3=2us +/// +/// else if PM_INIT { +/// +/// Timer settings if not able to be done in the init file +/// - PPT timer +/// - AISS hang timer +/// +/// } else if PM_RESET { +/// +/// AISS reset +/// +/// } //end PM_RESET -mode +/// +/// + +/// \endverbatim +/// +//------------------------------------------------------------------------------ +//---------------------------------------------------------------------- +// eCMD Includes +//---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_pm.H" +#include "p8_scom_addresses.H" +#include "p8_oha_init.H" + + + + +extern "C" { + + + +using namespace fapi; + + //------------------------------------------------------------------------------ + //Start scan zero value + //------------------------------------------------------------------------------ + + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +typedef struct { + int8_t AISS_HANG_DETECT_TIMER_SEL; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal + int8_t PPT_TIMER_SELECT; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us + int8_t LAD_ENTRY; + int8_t LAD_EXIT; +} struct_i_oha_val_init_type; + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +// Reset function +fapi::ReturnCode p8_oha_init_reset (const Target &i_target, uint32_t i_mode); +// Config function +fapi::ReturnCode p8_oha_init_config (const fapi::Target& i_target) ; +// INIT +fapi::ReturnCode p8_oha_init_init (const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) ; + + +// ---------------------------------------------------------------------- +// p8_oha_init wrapper to fetch the attributes and pass it on to p8_oha_init_core +// ---------------------------------------------------------------------- + +fapi::ReturnCode +p8_oha_init(const fapi::Target &i_target, uint32_t i_mode) +{ + fapi::ReturnCode rc; + + + + + + if ( i_mode == PM_CONFIG ) { + + FAPI_DBG("*************************************"); + FAPI_INF("MODE: CONFIG , Calling: p8_oha_init_config"); + FAPI_DBG("*************************************"); + rc=p8_oha_init_config(i_target); + + if (rc) { + FAPI_ERR(" p8_oha_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else if ( i_mode == PM_INIT ) { + + + FAPI_DBG("*************************************"); + FAPI_INF("MODE: INIT , Calling: p8_oha_init_init"); + FAPI_DBG("*************************************"); + + // ****************************************************************** + /// \todo should this values be attributes?? The get those attributes here + //#ifndef ATTRIBUTES_AVAIL + + //Declare parms struct + struct_i_oha_val_init_type i_oha_val_init; + + //Assign values to parms in struct + // should come from MRWB + i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal + i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us + i_oha_val_init.LAD_ENTRY = 16; + i_oha_val_init.LAD_EXIT = 17; + + + //#else + // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO + + //#endif + + // ****************************************************************** + + + + rc=p8_oha_init_init(i_target, i_oha_val_init); + + if (rc) { + FAPI_ERR(" p8_oha_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + } else if ( i_mode == PM_RESET ) { + FAPI_DBG("*************************************"); + FAPI_INF("MODE: RESET"); + FAPI_DBG("*************************************"); + + + + + //Declare parms struct + struct_i_oha_val_init_type i_oha_val_init; + + //Assign values to parms in struct + // should come from MRWB + i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal + i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us + i_oha_val_init.LAD_ENTRY = 16; + i_oha_val_init.LAD_EXIT = 17; + + // ****************************************************************** + /// \todo should this values be attributes?? The get those attributes here + + #ifndef ATTRIBUTES_AVAIL + + + #else + // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO + + #endif + + // ****************************************************************** + + + + + //FAPI_DBG("*************************************"); + FAPI_INF("Calling: p8_oha_init_reset"); + //FAPI_DBG("*************************************"); + rc = p8_oha_init_reset( i_target, i_mode); + + if (rc) { + FAPI_ERR(" p8_oha_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else { + //FAPI_DBG("*************************************"); + FAPI_ERR("Unknown mode passed to p8_oha_init. Mode %x ....\n", i_mode); + FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BAD_MODE); + //FAPI_DBG("*************************************"); + }; + + + + return rc; + +} + + + +fapi::ReturnCode +p8_oha_init_config(const fapi::Target& i_target) +{ + fapi::ReturnCode rc; + + uint8_t attr_pm_aiss_timeout; + uint32_t attr_pm_power_proxy_trace_timer; + uint32_t attr_pm_ppt_timer_tick; + uint32_t attr_pm_ppt_timer_match_value; + + + // ****************************************************************** + // Get Attributes for OHA Timers Delay + // ****************************************************************** + // set defaults if not available + + attr_pm_ppt_timer_tick = 2; // Default 2: 1us + + + + /// \todo PLAT attr ... not there yet + attr_pm_aiss_timeout = 5; // Default 5: 32ms + // rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } + // + + /// \todo PLAT attr ... not there yet + attr_pm_power_proxy_trace_timer = 64000; // Default 1us,,, 32us...64ms + // rc = FAPI_ATTR_GET(ATTR_PM_POWER_PROXY_TRACE_TIMER, &i_target, attr_pm_power_proxy_trace_timer); + // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_POWER_PROXY_TRACE_TIMER with rc = 0x%x", (uint32_t)rc); return rc; } + + + + + // ****************************************************************** + // Calculate OHA timer settings + // ****************************************************************** + //FAPI_DBG("*************************************"); + FAPI_DBG("Calculate OHA timer settings"); + //FAPI_DBG("*************************************"); + //FAPI_DBG("*************************************"); + FAPI_DBG("Calculate:"); + FAPI_DBG(" ATTR_PM_PPT_TIMER_MATCH_VALUE"); + FAPI_DBG(" ATTR_PM_PPT_TIMER_TICK"); + FAPI_DBG("using:"); + FAPI_DBG(" ATTR_PM_POWER_PROXY_TRACE_TIMER"); + //FAPI_DBG("**************************************************************************"); + FAPI_DBG(" Set ATTR_PM_AISS_TIMEOUT to 5 (32ms)"); + //FAPI_DBG("**************************************************************************"); + + + + + // + attr_pm_ppt_timer_match_value = attr_pm_power_proxy_trace_timer / 32 ; //time in us / 32us + + + + + + FAPI_DBG("*************************************"); + FAPI_DBG("attr_pm_aiss_timeout : %X", attr_pm_aiss_timeout); + FAPI_DBG("attr_pm_ppt_timer_match_value : %X", attr_pm_ppt_timer_match_value); + FAPI_DBG("*************************************"); + + + // ****************************************************************** + // Set Attributes for OHA timers + // ****************************************************************** + + // rc = FAPI_ATTR_SET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return; } + + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } + + + + return rc; + +} //end CONFIG + + + + + + +fapi::ReturnCode +p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) +{ + fapi::ReturnCode rc; + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + std::vector<fapi::Target> l_chiplets; + std::vector<Target>::iterator itr; + + + // Variables +//TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; + uint32_t l_rc; + + + uint8_t attr_pm_aiss_timeout; + uint32_t attr_pm_ppt_timer_tick; + uint32_t attr_pm_ppt_timer_match_value; + + FAPI_INF(""); + //FAPI_DBG("********* ******************* *********"); + FAPI_INF("Executing ....p8_oha_init"); + //FAPI_DBG("********* ******************* *********"); + FAPI_INF(""); + + + + + rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); + + + + + //FAPI_DBG("***********************************************"); + FAPI_INF(" Welcome to p8_oha_init INIT-mode "); + //FAPI_DBG("***********************************************"); + + + + // ****************************************************************** + // Get Attributes for OHA Timers Delay + // ****************************************************************** + #ifndef ATTRIBUTES_AVAIL + // ****************************************************************** + // set defaults if not available + attr_pm_ppt_timer_tick = 2; // Default 2: 1us + attr_pm_ppt_timer_match_value = 0x7FF; // Default 0x7FF: 64ms + attr_pm_aiss_timeout = 5; // Default 5: 32ms + #else +/// \todo PLAT attr ... not there yet + //rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + //if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } + #endif + + + + // ****************************************************************** + // initialize all oha_reg with scan-zero values upfront + // ****************************************************************** + + + + for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ + + + FAPI_DBG("Content Loop Variable C : %d ", c); + + + + // ****************************************************************** + // AISS hang timer setup + // ****************************************************************** + // ****************************************************************** + + // - set aiss_timeout to max time + // ****************************************************************** + //FAPI_DBG("**********************************************"); + FAPI_INF(" Setup aiss hang time in oha_mode_reg 1002000D"); + //FAPI_DBG("**********************************************"); + + // Read register content + rc = fapiGetScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); + if (rc) {FAPI_ERR("fapiGetScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + FAPI_DBG ("Content of EX_OHA_MODE_REG_0x1002000D : %016llX", data.getDoubleWord(0)); + + + + + //data.flushTo0(); + l_rc = data.insertFromRight(attr_pm_aiss_timeout ,11,4); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); + if (rc) { + FAPI_ERR("fapiPutScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + + + // ****************************************************************** + // Low Activity Detect (LAD) setup + // ****************************************************************** + // ****************************************************************** + // - enable LAD + // - set LAD for entry + // - set LAD for exit + // ****************************************************************** + //FAPI_DBG("**********************************************************************************************"); + FAPI_INF(" Setup Low Activity Detect (LAD) in oha_low_activity_detect_mode_reg 10020003, but NOT ENABLED"); + //FAPI_DBG("**********************************************************************************************"); + + // Read register content + //if (VERBOSE) { + rc = fapiGetScom( (*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + if (rc) { FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + FAPI_DBG(" Pre write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); + //} + + // + l_rc = data.setByte(0, i_oha_val_init.LAD_ENTRY); // 16 + l_rc |= data.setByte(1, i_oha_val_init.LAD_EXIT); // 17 + l_rc |= data.shiftRight(1); // LAD entry/exit starts at bit 1 + l_rc |= data.clearBit(0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + //FAPI_DBG(" !!!!!!!!!!!!!!!!!!!!!!returncode : %d", rc); + + + + + + rc = fapiPutScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003, data); if (rc) return rc; + // FAPI_DBG(" Post write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF ("Done LAD setup. LAD Disabled " ); + + + + // ****************************************************************** + // Power Proxy Trace (PPT) setup + // ****************************************************************** + // ****************************************************************** + // - set ppt_timer_select + // - set ppt_trace_timer_match_val + // ****************************************************************** + //FAPI_DBG("********************************************************************************"); + FAPI_INF(" Setup Power Proxy Trace (PPT) in oha_activity_sample_mode_reg 10020000"); + //FAPI_DBG("********************************************************************************"); + + // Read register content + rc = fapiGetScom( (*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + FAPI_DBG(" Pre write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); + + + // set ppt_int_timer_select to longest interval "11" = 2us + //l_rc = data.setBit(36); + //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } + //l_rc = data.setBit(37); + //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } + + l_rc = data.insertFromRight(attr_pm_ppt_timer_match_value ,24,11); + l_rc |= data.insertFromRight(attr_pm_ppt_timer_tick ,36,2); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + + rc = fapiPutScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + // if debug mode read back + //if (VERBOSE) { + rc = fapiGetScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000, data); if (rc) return rc; + FAPI_DBG(" Post write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF ("Done PPT timer setup." ); + } + + + + return rc; + +} //end INIT + + + + +ReturnCode +p8_oha_init_reset(const Target &i_target, uint32_t i_mode) +{ + ReturnCode rc; + +//std::string PROCEDURE = "p8_oha_init"; // procedure name +//std::string REVISION = "$Revision: 1.3 $"; // procedure CVS revision + + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + std::vector<fapi::Target> l_chiplets; + std::vector<Target>::iterator itr; + + + // Variables +//TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; + uint32_t l_rc; + + FAPI_DBG(""); + //FAPI_DBG("********* ******************* *********"); + FAPI_INF("Executing p8_oha_init..."); + //FAPI_DBG("********* ******************* *********"); + FAPI_DBG(""); + + + + + + + // rc = fapiGetExistingChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; + rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); + + + + + + + //FAPI_DBG("***********************************************"); + FAPI_INF(" Welcome to p8_oha_init_reset "); + //FAPI_DBG("***********************************************"); + + +for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ + + + FAPI_DBG("Content Loop Variable C : %d ", c); + + + + + + //FAPI_DBG("*************************************"); + FAPI_INF("Reset AISS "); + FAPI_INF("Write to register OHA_ARCH_IDLE_STATE_REG "); + //FAPI_DBG("*************************************"); + + + + rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + if (rc) { + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + FAPI_DBG(" Pre write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + + l_rc = data.setBit(9); //reset_idle_state_sequencer_in ... reset pulse gets generated. Not unsetting required + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom((*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + // if debug mode read back + //if (VERBOSE) { + rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); if (rc) return rc; + FAPI_DBG(" Post write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + //} + if (rc) { + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + + + + +} + + + + FAPI_INF(""); + FAPI_INF("Executing proc_OHA_init ....\n"); + + + return rc; +} + + + + + + + + + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H new file mode 100755 index 000000000..687320f1c --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H @@ -0,0 +1,79 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ + +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : p8_oha_init.H +// *! DESCRIPTION : Initialize OHA +// *! +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +// *! +//------------------------------------------------------------------------------ +// + + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_oha_init_FP_t) (const fapi::Target&, uint32_t); + + + +extern "C" +{ + + + /// \brief Initialize OHA + /// + /// \param[in] &i_target Chip target + /// \param[in] i_mode Mode 1: CONFIG-Mode + /// Mode 2: RESET-Mode + /// Mode 3: INIT-Mode + +fapi::ReturnCode p8_oha_init (const fapi::Target& i_target, uint32_t i_mode); + + + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C new file mode 100755 index 000000000..6c4048ace --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C @@ -0,0 +1,916 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pba_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pba_init.C,v 1.7 2012/10/25 11:59:45 kgungl Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Klaus P. Gungl Email: kgungl@de.ibm.com +// *! +// *! +/// \file p8_pba_init.C +/// \brief Initialize PBA registers for modes PM_INIT, PM_RESET and PM_CONFIG +// *! +// *! Functional description: setup the PBA registers depending on mode +// *! calling parameters: +// *! : Target i_target // target according to calling conventions +// *! uint64_t mode // mode according to power_up spec: PM_CONFIG, PM_INIT, PM_RESET +// *! +// *! high level flow: +// *! if (mode == PM_CONFIG) { +// *! rc = p8_pba_init_PM_CONFIG(i_target); +// *! } else { +// *! if (mode == PM_INIT) { +// *! rc = p8_pba_init_PM_INIT(i_target); +// *! } else { +// *! if (mode == PM_RESET) { +// *! rc = p8_pba_init_PM_RESET(i_target); +// *! } else { +// *! FAPI_SET_HWP_ERROR(rc,RC_P8_PBA_INIT_INCORRECT_MODE); +// *! } +// *! } +// *! } // endif +// *! } // endif +// *! +// *! +// *! list of changes +// *! 2012/10/11 applied changes and error corrections according to Terry Opie and reformatting if-else +// *! 2012/10/11 applied changes according to Terry Opie +// *! 2012/07/26 applied the changes as recommended by Greg's second review, pbax attributes included, +// *! 2012/07/18 applied the changes as recommended by Greg, attribute coding, TODO: correct constants +// *! 2012/05/09 global variables removed, "mode" used according to common rules. +// *! 2012/05/17 temporary commented out the accesses assumed wrong address +// *! +//------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pba_init.H" +#include "pba_firmware_register.H" +#include "p8_pm.H" +#include <ecmdDataBufferBase.H> + +// get the constants from here +// #include "pgp_pba.h" +// #include "pgp_common.h" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- +// constant definitions are currently in the *.h files, need to consolidate? + +// move the following to p8_scom_addresses.H +// CONST_UINT64_T( PBAXSNDTX_00064020 , ULL(0x00064020) ); +// CONST_UINT64_T( PBAXCFG_00064021 , ULL(0x00064021) ); +// CONST_UINT64_T( PBAXSHBR0_00064026 , ULL(0x00064026) ); +// CONST_UINT64_T( PBAXSHBR1_0006402A , ULL(0x0006402A) ); + + // from "pgp_pba.h" "pgp_common.h" +//////////////////////////////////// +// Macros for fields of PBA_SLVCTLn +//////////////////////////////////// + +// PBA write Ttypes + +#define PBA_WRITE_TTYPE_DMA_PR_WR 0x0 /// DMA Partial Write +#define PBA_WRITE_TTYPE_LCO_M 0x1 /// L3 LCO, Tsize denotes chiplet +#define PBA_WRITE_TTYPE_ATOMIC_RMW 0x2 /// Atomic operations +#define PBA_WRITE_TTYPE_CACHE_INJECT 0x3 /// ? +#define PBA_WRITE_TTYPE_CI_PR_W 0x4 /// Cache-inhibited partial write for Centaur putscom(). + +#define PBA_WRITE_TTYPE_DC PBA_WRITE_TTYPE_DMA_PR_WR // Don't care + +#define PBA_OCI_REGION 0 + +#define PBA_BCE_OCI_TRANSACTION_32_BYTES 0 +#define PBA_BCE_OCI_TRANSACTION_64_BYTES 1 +#define PBA_BCE_OCI_TRANSACTION_8_BYTES 2 + +#define PBA_OCI_MARKER_BASE 0x40070000 + +#define PBA_SLAVE_PORE_GPE 0 /* GPE0/1, but only 1 can access mainstore */ +#define PBA_SLAVE_OCC 1 /* 405 I- and D-cache */ +#define PBA_SLAVE_PORE_SLW 2 +#define PBA_SLAVE_OCB 3 + +#define OCI_MASTER_ID_PORE_GPE 0 +#define OCI_MASTER_ID_PMC 1 +#define OCI_MASTER_ID_PBA 2 +#define OCI_MASTER_ID_UNUSED 3 +#define OCI_MASTER_ID_PORE_SLW 4 +#define OCI_MASTER_ID_OCB 5 +#define OCI_MASTER_ID_OCC_ICU 6 +#define OCI_MASTER_ID_OCC_DCU 7 + +// PBA write gather timeouts are defined in terms of the number of 'pulses'. A +// pulse occurs every 64 OCI cycles. The timing of the last write of a +// sequence is variable, so the timeout will occur somewhere between (N - 1) * +// 64 and N * 64 OCI cycles. If write gather timeouts are disabled, the PBA +// holds the data until some condition occurs that causes it to disgorge the +// data. Slaves using cache-inhibited partial write never gather write +// data. Note from spec. : "Write gather timeouts must NOT be disabled if +// multiple masters are enabled to write through the PBA". The only case +// where write gather timeouts will be disabled is for the IPL-time injection +// of data into the L3 caches. + +#define PBA_WRITE_GATHER_TIMEOUT_DISABLE 0x0 +#define PBA_WRITE_GATHER_TIMEOUT_2_PULSES 0x4 +#define PBA_WRITE_GATHER_TIMEOUT_4_PULSES 0x5 +#define PBA_WRITE_GATHER_TIMEOUT_8_PULSES 0x6 +#define PBA_WRITE_GATHER_TIMEOUT_16_PULSES 0x7 + +/// PBA write gather timeout don't care assignment +#define PBA_WRITE_GATHER_TIMEOUT_DC PBA_WRITE_GATHER_TIMEOUT_2_PULSES + + +// PBA read Ttype + +#define PBA_READ_TTYPE_CL_RD_NC 0x0 /// Cache line read +#define PBA_READ_TTYPE_CI_PR_RD 0x1 /// Cache-inhibited partial read for Centaur getscom(). + +/// PBA read TTYPE don't care assignment +#define PBA_READ_TTYPE_DC PBA_READ_TTYPE_CL_RD_NC + + +// PBA read prefetch options + +#define PBA_READ_PREFETCH_AUTO_EARLY 0x0 /// Aggressive prefetch +#define PBA_READ_PREFETCH_NONE 0x1 /// No prefetch +#define PBA_READ_PREFETCH_AUTO_LATE 0x2 /// Non-aggressive prefetch + +/// PBA read prefetch don't care assignment +#define PBA_READ_PREFETCH_DC PBA_READ_PREFETCH_NONE + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- +// mandated: do not use global variables + +// ---------------------------------------------------------------------- +// local Function definitions / prototypes +// ---------------------------------------------------------- +ReturnCode p8_pba_init_PM_CONFIG ( const Target& i_target ); +ReturnCode p8_pba_init_PM_INIT ( const Target& i_target ); +ReturnCode p8_pba_init_PM_RESET ( const Target& i_target ); + +ReturnCode pba_slave_setup_init ( const Target& i_target ); +ReturnCode pba_slave_setup_reset ( const Target& i_target ); + + // from pgp_pba.h +int pba_slave_reset(int id); + + +// ********************************************************************************************** +// ----------------------------------------------- p8_pba_init -------------------------------- +// function: +// set the pba registers depending on "mode", no default mode +// returns: fapi return codes +ReturnCode +p8_pba_init(const Target& i_target, + uint64_t mode + ) +{ +ReturnCode rc; +// calling the selected function from here + + if (mode == PM_CONFIG) { + rc = p8_pba_init_PM_CONFIG(i_target); + } else { + if (mode == PM_INIT) { + rc = p8_pba_init_PM_INIT(i_target); + } else { + if (mode == PM_RESET) { + rc = p8_pba_init_PM_RESET(i_target); + } else { + FAPI_SET_HWP_ERROR(rc,RC_P8_PBA_INIT_INCORRECT_MODE); + } // endif + } // endif + } // endif + + return rc; +} + +// ********************************************************************************************** + // ******************************************************** mode = PM_RESET ******************** + +ReturnCode + p8_pba_init_PM_RESET(const Target& i_target) + { + + ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_rc; // local returncode + + + // if (mode == PM_RESET) { + FAPI_INF("mode = PM_RESET..\n"); + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + + + // For reset phase, write these with 0x0 + // No content for config or init phase as all initialization is done by OCC FW + rc = fapiPutScom(i_target, PBA_BCDE_CTL_0x00064010 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCDE_CTL_0x00064010 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCDE_CTL_0x00064010 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCDE_SET_0x00064011 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_SET_0x00064011 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCDE_SET_0x00064011 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCDE_STAT_0x00064012 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_STAT_0x00064012 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCDE_STAT_0x00064012 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCDE_PBADR_0x00064013 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_PBADR_0x00064013 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCDE_PBADR_0x00064013 \n "); + } + + rc = fapiPutScom(i_target, PBA_BCDE_OCIBAR_0x00064014 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCDE_OCIBAR_0x00064014 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCDE_OCIBAR_0x00064014 \n "); + } + + rc = fapiPutScom(i_target, PBA_BCUE_CTL_0x00064015 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_CTL_0x0006401 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCUE_CTL_0x00064015 \n "); + } + + rc = fapiPutScom(i_target, PBA_BCUE_SET_0x00064016 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_SET_0x00064016 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCUE_SET_0x00064016 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCUE_STAT_0x00064017 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCUE_STAT_0x00064017 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCUE_STAT_0x00064017 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCUE_PBADR_0x00064018 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBA_BCUE_PBADR_0x00064018 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCUE_PBADR_0x00064018 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_BCUE_OCIBAR_0x00064019 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_BCUE_OCIBAR_0x00064019 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_BCUE_OCIBAR_0x00064019 \n "); + } // end if-else + + // For reset, written with 0x0s to restore to fresh value. + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_SLVCTL0_0x0006400 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_SLVCTL1_0x00064005 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_SLVCTL2_0x00064006 \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_SLVCTL3_0x00064007 \n "); + } // end if-else + + // Clear the PBA FIR (Reset) only + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_DBG("Done with PBA_FIR_0x02010840 \n "); + } // end if-else + + // For reset, this register should be written with the value from figtree to restore the initial hardware state. + // Therefore fix this constant: + // For init, needs detailing for performance and/or CHSW enable/disable + // reset case + // data still 0 + rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with, PBA_CONFIG_0x0201084B \n "); + } // end if-else + + // pba slave register handling for PM_RESET + rc = pba_slave_setup_reset(i_target); + if (rc) + { + FAPI_ERR("pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with, pba_slave_setup_reset \n "); + } // end if-else + + // For reset, written with 0x0s to restore to fresh value. + rc = fapiPutScom(i_target, PBA_ERR_RPT0_0x0201084C , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_ERR_RPT0_0x0201084C ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_ERR_RPT0_0x0201084C \n "); + } // end if-else + // the following operations are not required, keep this in mind, don't erase them here + // l_rc = fapiPutScom(i_target, PBA_ERR_RPT1_0x0201084D , data); + // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } + // else {FAPI_INF("Done with PBA_ERR_RPT1_0x0201084D \n ") }; + + // l_rc = fapiPutScom(i_target, PBA_ERR_RPT2_0x0201084E , data); + // if(l_rc) { FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_INIT_PUTSCOM_FAILED); return l_rc; } + // else {FAPI_INF("Done with PBA_ERR_RPT2_0x0201084E \n ") }; + + + // The following apply to Reset mode ( + rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001 , data); + if (rc) { FAPI_ERR("fapiPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + else {FAPI_INF("Done with PBA_SLVRST_0x00064001 \n "); } + + // last step: pba slave setup for reset + rc = pba_slave_setup_reset (i_target); + if (rc) { FAPI_ERR("fapi pba_slave_setup_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; } + else {FAPI_INF("Done with fapi pba_slave_setup_reset \n "); } + + return rc; + + } // endif (mode == PM_RESET) + + + + // *********************************************************************************************** + // ************************************************************ mode = PM_INIT ******************* + // call pba_slave_setup + ReturnCode + p8_pba_init_PM_INIT(const Target& i_target) + { + + ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_rc; // local returncode + + uint8_t ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value = 0 ; + uint8_t ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value = 0 ; + + pbaxcfg_t pbaxcfg_setup ; + + // if (mode == PM_INIT) { + FAPI_INF("mode = PM_INIT..\n"); + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + // For reset, this register should be written with the value from figtree to restore the + // initial hardware state. + // For init, needs detailing for performance and/or CHSW enable/disable TODO + // init case + rc = fapiPutScom(i_target, PBA_CONFIG_0x0201084B , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_CONFIG_0x0201084B ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with, PBA_CONFIG_0x0201084B \n "); + } // end if-else + + // Clear the PBA FIR (Reset) only + // data still 0 + rc = fapiPutScom(i_target, PBA_FIR_0x02010840 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_FIR_0x02010840 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_DBG("Done with PBA_FIR_0x02010840 \n "); + } // end if-else + + // The following registers are ROX, hence need not be touched: + // PBA_RBUFVAL0_0x02010850 + // PBA_RBUFVAL1_0x02010851 + // PBA_RBUFVAL2_0x02010852 + // PBA_RBUFVAL3_0x02010853 + // PBA_RBUFVAL4_0x02010854 + // PBA_RBUFVAL5_0x02010855 + // PBA_WBUFVAL0_0x02010858 + // PBA_WBUFVAL1_0x02010859 + + // These PowerBus Overcommit regs are read-only, therefore no action required: + // PBA_PBOCR0_0x00064020 + // PBA_PBOCR1_0x00064021 + // PBA_PBOCR2_0x00064022 + // PBA_PBOCR3_0x00064023 + // PBA_PBOCR4_0x00064024 + // PBA_PBOCR5_0x0006402 + + // The PBA BARs and their associated Masks are done outside of this FAPI set. Thus, during + // a reset, the BARS/MASKS are retained. this applies to + // PBA_BAR0_0x02013F00 + // PBA_BARMSK0_0x02013F04 + // PBA_BARMSK1_0x02013F05 + // PBA_BAR1_0x02013F01 + // PBA_BAR2_0x02013F02 + // PBA_BAR3_0x02013F03 + // PBA_TRUSTMODE_0x02013F08 + + // any checkreads => NO + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_RCV_RESERV_TIMEOUT ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE , &i_target, ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABL ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RETRY_THRESHOLD , &i_target, ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RETRY_THRESHOLD ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } // end if + + rc = FAPI_ATTR_GET ( ATTR_PM_PBAX_SND_RESERV_TIMEOUT , &i_target, ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value ); + if (rc) + { + FAPI_ERR("fapi_attr_get( ATTR_PM_PBAX_SND_RESERV_TIMEOU ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } // end if + + // assemble the attributes + // 20:24, ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value + // 27; ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value + // 28:35; ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value + // 36:40 ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value + pbaxcfg_setup.fields.ATTR_PM_PBAX_RCV_RESERV_TIMEOUT = ATTR_PM_PBAX_RCV_RESERV_TIMEOUT_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE = ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RETRY_THRESHOLD = ATTR_PM_PBAX_SND_RETRY_THRESHOLD_value; + pbaxcfg_setup.fields.ATTR_PM_PBAX_SND_RESERV_TIMEOUT = ATTR_PM_PBAX_SND_RESERV_TIMEOUT_value; + + // put the attribute values into PBAXCFG + l_rc = data.setDoubleWord(0, pbaxcfg_setup.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBAXCFG_00064021 , data); + if (rc) + { + FAPI_ERR("fapiPutScom(PBAXCFG_00064021) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with attr_pbaxsndtx_value "); + } // end if-else + + // last step: pba slave setup for init + rc = pba_slave_setup_init (i_target); + if (rc) + { + FAPI_ERR("fapi pba_slave_setup_init failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with api_pba_slave_init \n "); + } // end if-else + + return rc; + + } // end PM_INIT + + + // ************************************************************************************************* + // ************************************************************* mode = PM_CONFIG ****************** + // + /// Configuration: perform translation of any Platform Attributes into + /// Feature Attributes that are applied during Initalization of PBAX + ReturnCode + p8_pba_init_PM_CONFIG(const Target& i_target) + { + ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t l_rc; // local returncode + FAPI_INF("mode = PM_CONFIG..\n"); + l_rc = data.setDoubleWord(0, 0x0); + if (l_rc) { FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + FAPI_INF("PBAX configuration..."); + FAPI_INF("Getting PBAX configuration values via attribute settings."); + + return rc; +}; + + +// ************************************************************************************************ +// **************************************************** pba_slave_setup *************************** +/// PgP PBA Setup +/// +/// The PBA is 'set up' twice. The first set up is via scan-0 settings or +/// SBE-IPL code to enable the Host Boot image to be injected into the cache +/// of the IPL core. +/// +/// This procedure documents the second setup that will normally be done by a +/// FAPI procedure prior to releasing the OCC from reset. This setup serves +/// both for the initial boot of OCC as well as for the OCC (GPE), SLW and FSP +/// runtime. This procedure documents how the PBA should be set up the second +/// time. +/// +/// PBA slave 0 is reserved to the GPE engines, which must be able to switch +/// modes to read from mainstore or Centaur inband SCOM spaces, and write +/// Centaur inband SCOMs and also write into mainstore using IMA to support +/// the Power Proxy Trace application. +/// +/// PBA slave 1 is dedicated to the 405 ICU/DCU. This PBA slave is used for +/// the initial boot, and for the initial runtime code that manages the OCC +/// applet table. Once OCC has initialzied applets, OCC FW will remove all +/// TLB mappings associated with mainstore, effectively disabling this slave. +/// +/// PBA Slave 2 is dedicated to the PORE-SLW. Since 24x7 performance +/// monitoring code now runs on PORE-SLW, the PORE-SLW is no longer a +/// read-only master, but instead serves as a generic read-write master like +/// all of the others. +/// +/// PBA Slave 3 is mapped to the OCB in order to service FSP direct read/write +/// of mainstore. +/// +/// The design of PBA allows read buffers to be dedicated to a particular +/// slave, and requires that a slave have a dedicated read buffer in order to +/// do aggressive prefetching. In the end there is little reason to partition +/// the resources. The PORE-SLW will be running multiple applications that +/// read and write main memory so we want to allow PORE-SLW access to all +/// resources. It also isn't clear that aggressive prefetching provides any +/// performacne boost. Another wrinkle is that the BCDE claims read buffer C +/// whenever it runs, and the 405 I + D sides never run after the initial OCC +/// startup. For these reasons all slaves are programmed to share all +/// resources. +/// +/// \bug Need to disable slave prefetch for now for all shared buffers until a +/// mode bit gets added too the PBA logic. +/// +/// \bug The dis_slvmatch_order bit is going away + +ReturnCode +pba_slave_setup_init(const Target& i_target) +{ + pba_mode_t pm; + pba_slvctln_t ps; + ReturnCode rc; + uint32_t l_rc; // local returncode + ecmdDataBufferBase data(64); + + // Set the PBA_MODECTL register. It's not yet clear how PBA BCE + // transaction size will affect performance - for now we go with the + // largest size. The HTM marker space is enabled and configured. Slave + // fairness is enabled. The setting 'dis_slvmatch_order' ensures that PBA + // will correctly flush write data before allowing a read of the same + // address from a different master on a different slave. The second write + // buffer is enabled. + // prepare the value to be set: + pm.value = 0; + pm.fields.pba_region = PBA_OCI_REGION; + pm.fields.bcde_ocitrans = PBA_BCE_OCI_TRANSACTION_64_BYTES; + pm.fields.bcue_ocitrans = PBA_BCE_OCI_TRANSACTION_64_BYTES; + pm.fields.en_marker_ack = 1; + pm.fields.oci_marker_space = (PBA_OCI_MARKER_BASE >> 16) & 0x7; + pm.fields.en_slave_fairness = 1; + pm.fields.dis_slvmatch_order = 1; + pm.fields.en_second_wrbuf = 1; + + l_rc = data.setDoubleWord(0, pm.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } + + // write the prepared value + rc = fapiPutScom(i_target, PBA_MODE_0x00064000 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + + // Slave 0 (PORE-GPE). This is a read/write slave. We only do 'static' + // setup here. Dynamic setup will be done by each GPE program that needs + // to access mainstore, before issuing any trasactions targeting the PBA + // bridge. + + // pba_slave_reset(PBA_SLAVE_PORE_GPE); + ps.value = 0; + ps.fields.enable = 1; + ps.fields.mid_match_value = OCI_MASTER_ID_PORE_GPE; + ps.fields.mid_care_mask = 0x7; + ps.fields.buf_alloc_a = 1; + ps.fields.buf_alloc_b = 1; + ps.fields.buf_alloc_c = 1; + ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + // Slave 1 (405 ICU/DCU). This is a read/write slave. Write gethering is + // allowed, but with the shortest possible timeout. This slave is + // effectively disabled soon after IPL. + + // pba_slave_reset(PBA_SLAVE_OCC); + ps.value = 0; + ps.fields.enable = 1; + ps.fields.mid_match_value = OCI_MASTER_ID_OCC_ICU & OCI_MASTER_ID_OCC_DCU; + ps.fields.mid_care_mask = OCI_MASTER_ID_OCC_ICU & OCI_MASTER_ID_OCC_DCU; + ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC; + ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE; + ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR; + ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES; + ps.fields.buf_alloc_a = 1; + ps.fields.buf_alloc_b = 1; + ps.fields.buf_alloc_c = 1; + ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + + // Slave 2 (PORE-SLW). This is a read/write slave. Write gathering is + // allowed, but with the shortest possible timeout. The slave is set up + // to allow normal reads and writes at initialization. The 24x7 code may + // reprogram this slave for IMA writes using special code sequences that + // restore normal DMA writes after each IMA sequence. + + // pba_slave_reset(PBA_SLAVE_PORE_SLW); + ps.value = 0; + ps.fields.enable = 1; + ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW; + ps.fields.mid_care_mask = 0x7; + ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC; + ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE; + ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR; + ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES; + ps.fields.buf_alloc_a = 1; + ps.fields.buf_alloc_b = 1; + ps.fields.buf_alloc_c = 1; + ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + + // Slave 3 (OCB). This is a read/write slave. Write gathering is + // allowed, but with the shortest possible timeout. + + // pba_slave_reset(PBA_SLAVE_OCB); + ps.value = 0; + ps.fields.enable = 1; + ps.fields.mid_match_value = OCI_MASTER_ID_OCB; + ps.fields.mid_care_mask = 0x7; + ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC; + ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE; + ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR; + ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES; + ps.fields.buf_alloc_a = 1; + ps.fields.buf_alloc_b = 1; + ps.fields.buf_alloc_c = 1; + ps.fields.buf_alloc_w = 1; + l_rc = data.setDoubleWord(0, ps.value); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + return rc; +} // end pba_slave_setup_init + + +// for reset, set all register contents to zero +ReturnCode +pba_slave_setup_reset(const Target& i_target) +{ + ReturnCode rc; + uint32_t l_rc; // local returncode + ecmdDataBufferBase data(64); + + l_rc= data.setDoubleWord(0, 0x00000000); + if (l_rc) + { + FAPI_ERR("data.setDoubleWord ( ) failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; + } // end if + + rc = fapiPutScom(i_target, PBA_MODE_0x00064000 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_MODE_0x00064000 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL0_0x00064004 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL0_0x00064004 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL1_0x00064005 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL1_0x00064005 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL2_0x00064006 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL2_0x00064006 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + rc = fapiPutScom(i_target, PBA_SLVCTL3_0x00064007 , data); + if (rc) + { + FAPI_ERR("fapiPutScom( PBA_SLVCTL3_0x00064007 ) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } else + { + FAPI_INF("Done with PBA_MODE \n "); + } // end if-else + + return rc; + +} // end pba_slave_setup_reset + + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C new file mode 100755 index 000000000..2dba473e6 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C @@ -0,0 +1,2155 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pcbs_init.C,v 1.6 2012/10/12 15:33:19 rmaier Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +// *! General Description: +// *! +// *! The purpose of this procedure is to establish the safe setting for PCBSLV +// *! o set psafe value +// *! o set PMIN clip/Pmax clip +// *! o PMCR default values +// *! o PMICR default values +// *! +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ +/// \file p8_pcbs_init.C +/// \brief Establish the Pstate 0 frequency from VPD +/// +/// +/// +/// \version -------------------------------------------------------------------------- +/// \version 1.6 rmaier 10/12/12 Removed not needed scan0 writes to EX_PCBS_Pstate_Step_Target_Register EX_PCBS_OCC_Heartbeat_Reg +/// \version -------------------------------------------------------------------------- +/// \version 1.5 rmaier 10/10/12 Changed value of EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0 +/// \version -------------------------------------------------------------------------- +/// \version 1.4 rmaier 10/08/12 Removed genBinStr and <string> function +/// \version -------------------------------------------------------------------------- +/// \version 1.3 rmaier 10/04/12 Replacing genHex*Str function +/// \version -------------------------------------------------------------------------- +/// \version 1.2 rmaier 09/20/12 Updated with new PCBS-addressing method +/// \version -------------------------------------------------------------------------- +/// \version 1.1 rmaier 08/23/12 Renaming proc_ to p8_ +/// \version -------------------------------------------------------------------------- +/// \version 1.15 rmaier 08/15/12 Included review feedback Set7 (removed conditional compile statements ) +/// \version -------------------------------------------------------------------------- +/// \version 1.14 rmaier 08/03/12 Included review feedback Set4 +/// \version -------------------------------------------------------------------------- +/// \version 1.13 rmaier 08/02/12 Included review feedback Set4 partial +/// \version -------------------------------------------------------------------------- +/// \version 1.12 rmaier 07/30/12 Included review feedback Set3 partial +/// \version -------------------------------------------------------------------------- +/// \version 1.11 rmaier 07/23/12 Included review feedback Set2 partial +/// \version -------------------------------------------------------------------------- +/// \version 1.10 rmaier 07/17/12 Included review feedback Set1 +/// \version -------------------------------------------------------------------------- +/// \version 1.7 rmaier 05/24/12 Included review feedback +/// \version -------------------------------------------------------------------------- +/// \version 1.6 rmaier 03/27/12 Coded CONFIG mode +/// \version -------------------------------------------------------------------------- +/// \version 1.5 rmaier 03/20/12 Coded INIT mode +/// \version -------------------------------------------------------------------------- +/// \version 1.4 rmaier 03/13/12 Added modes-structure +/// \version -------------------------------------------------------------------------- +/// \version 1.3 rmaier 01/11/12 Removed PFET values +/// \version -------------------------------------------------------------------------- +/// \version 1.2 rmaier 12/05/11 Hardcoded valid chiplets ... need to be removed again fapiGetExistingChiplets => fapiGetChildChiplets +/// \version -------------------------------------------------------------------------- +/// \version 1.1 rmaier 11/30/11 eCMD 12.2 adaptions. fapiGetExistingChiplets => fapiGetChildChiplets , Scan0 values set +/// \version -------------------------------------------------------------------------- +/// \version 1.0 rmaier 10/17/11 Initial Version - RESET mode +/// \version --------------------------------------------------------------------------- +/// +/// +/// +/// +/// +/// +/// \todo command order +/// \todo next -- > initialize all pm_reg with scan-zero values upfront +/// \todo Clear definition/doc of parms and attributes required at the beginning. +/// \todo GP3 Changes Winkle fence changes +/// \todo Review +/// +/// +/// High-level procedure flow: +/// +/// \verbatim +/// +/// Procedure Prereq: +/// - completed istep procedure +/// - completed multicast setup +/// +/// +/// if PM_CONFIG { +/// PState translation +/// convert_safe_freq() +/// Resonant Clocking settings (band definitions from frequency to Pstate) +/// convert_resclk_freqs_to_pstates() +/// PFET Sequencing Delays +/// convert_pfet_delays() +/// +/// else if PM_INIT { +/// +/// set CPM_FILTER_ENABLE = 0 -- #110f0152, DPLL_CPM_PARM_REG[10] = 0 +/// -- PMGP1_REG WOX_OR 150f0105 +/// ATTR_PM_SLEEP_ENTRY (Assisted or Hardware) bit0 0=assisted +/// ATTR_PM_SLEEP_EXIT (Assisted or Hardware) bit1 0=assisted +/// ATTR_PM_SLEEP_TYPE (Deep or Fast) bit2 0=fast +/// ATTR_PM_WINKLE_ENTRY (Assisted or Hardware) bit3 +/// ATTR_PM_WINKLE_EXIT (Assisted or Hardware) bit4 +/// ATTR_PM_WINKLE_TYPE (Deep or Fast) bit5 +/// +/// set PMCR[0:39] = 0 -- PMCR default value adjustment +/// -- (Hardware flush 0 -> restore to 0 for reset case) +/// -- #110f0159, PCBS_POWER_MANAGEMENT_CONTROL_REG +/// +/// pm_spr_override_en must be set to write this reg!! +/// set PMICR[0:47] = 0 -- PMICR default value adjustment +/// -- (Hardware flush 0 -> restore to TBD for reset case) +/// -- #110f0158, PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG +/// +/// +/// +/// } else if PM_RESET { +/// +/// loop over all valid chiplets { +/// +/// -- TODO check about +/// -- initialize all pm_reg with scan-zero values upfront +/// +/// // Force safe mode +/// set force_safe_mode = 1 -- Force safe mode (uses Psafe Pstate setting) +/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[12] = 1/// +/// // psafe Pstate achived AND FSM-stable ? +/// if psafePstate achived AND FSM-stable { -- Check PCBS-PM state/status that Psafe (Pstate) as been achieved and +/// -- that FSM are in a stable state +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state +/// } elsif timeout { +/// --BAD RC: timeout - no PsafePstate or FSMs not stable +/// } +/// +/// // DPLL settings +/// set dpll_freq_override_enable = 1 -- PCBS_PM_PMGP1_REG_1[10] = 1 +/// -- only in override mode is a write to FREQ_CTRL_REG possible +/// +/// set minPstate = min(Psafe,global actual pstate) -- PCBS_OCC_Heartbeat_Reg[17..24] Psafe +/// -- PCBS_POWER_MANAGEMENT_STATUS_REG[0..7] global actual pstate +/// set dpll_min = fnom + minPstate(signed) -- FREQ_CTRL_REG[20..27] pstate_dpll_fnom +/// +/// +/// set dpll_fmin -- FREQ_CTRL_REG[0..7] scaninit: 00110010 +/// set dpll_fmax -- FREQ_CTRL_REG[8..15] scaninit: 00110010 +/// +/// set pm_spr_override_en = 1 -- Force OCC SPR Mode +/// -- XXXX multicast PCBS_PM_PMGP1_REG_1[11] = 1 +/// +/// set enable_Pstate_mode = 0 -- PCBSPM_MODE_REG[0] ....multicast +/// +/// set enable_global_pstate_req = 0 -- Force *global_en PState to off to cease interrupts to PMC....multicast +/// -- PCBSPM_MODE_REG[2] +/// +/// -- Reset Pmin and Pmax to wide open...multicast +/// set Pmin_clip = -128 -- PCBS_Power_Management_Bounds_Reg[0..7] 0b10000000 +/// set Pmax_clip = 127 -- PCBS_Power_Management_Bounds_Reg[8..15] 0b01111111 +/// +/// +/// // Settings +/// set resclk_dis = 1 -- Chiplets resonant clocking (via PCBS) disabled +/// -- EH.TPCHIP.NET.PCBSLPREV.GP3_REG[22] +/// -- This is only ROX PCBS_Resonant_Clock_Control_Reg0[0] +/// +/// set occ_heartbeat_enable = 0 -- OCC Heartbeat disable +/// -- PCBS_OCC_Heartbeat_Reg[8] +/// +/// // IVRM Setup +/// get the mrwb attribute ivrms_enabled -- If '0' Salerno, if '1' Venice +/// if ivrms_enabled { +/// set ivrm_fsm_enable = 0 -- PCBS_iVRM_Control_Status_Reg[0] +/// -- ivrm_fsm_enable have be '0' to enable bypass_b writes +/// set bypass_b mode = 0 +/// --ivrm_core_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[4] +/// --ivrm_core_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[6] +/// --ivrm_eco_vdd_bypass_b -- PCBS_iVRM_Control_Status_Reg[8] +/// --ivrm_eco_vcs_bypass_b -- PCBS_iVRM_Control_Status_Reg[10] +/// } +/// +/// -- Undervolting values reset +/// set Kuv = 0 -- PCBS_UNDERVOLTING_REG[16..21] +/// -- Puv_min and Puv_max to disable +/// set Puv_min = -128 -- PCBS_UNDERVOLTING_REG[0..7] +/// set Puv_max = -128 -- PCBS_UNDERVOLTING_REG[8..15] +/// +/// set enable_LPFT_function = 0 -- Local Pstate Frequency Target mechanism disabled +/// -- PCBS_Local_Pstate_Frequency_Target_Control_Register[20] +/// +/// // Issue reset to PCBS-PM +/// set endp_reset_pm_only = 1 -- Issue reset to PCBS-PM +/// -- PMGP1_REG[9] +/// -- unset off reset in the next cycle?? +/// set endp_reset_pm_only = 0 -- PMGP1_REG[9] +/// +/// ] --end loop over all valid chiplets +/// +/// } //end PM_RESET -mode +/// +/// +/// \endverbatim + +/// HostBoot_IPL_Flow_v93_occ.odt + +/// RESET +/// +///-Force safe mode (uses Psafe Pstate setting) in EX chiplet (multicastable) (for safety) (with removal of MIN functions (design change)) +///-Check PCBS-PM state/status that Psafe (Pstate) as been achieved and that FSM are in a stable state. +/// -If timeout, indicate that restart of OCC is to not occur (means are TBD) +/// -Write DPLL Frequ Control Reg with the frequency (not PState!) that represents the minimum of Psafe or Global Actual as seen in the PCBS. +///-Chiplets forced (via PCBS) into DPLL Override / PState disabled mode (whatever the above PState turned out to be) +///-The frequency value determined by Psafe/Vsafe is locked from changes by the PState mechanism. This allows the PCBS to be re-initialized. +///-Force OCC SPR Mode in EX chiplet (multicastable) +///-Force *global_en PState to off to cease interrupts to PMC (Global, AutoOverride, Idle) in EX chiplet (multicable) +///-Reset Pmin and Pmax to "wide open in EX chiplet (multicastable) +///-Chiplets resonant clocking (via PCBS) disabled +///-This allows the PCBS to be re-initialized blindly +///-It is debatable whether this is necessary as resonant clock can continue to operate while the OCC reset is being performed and while the chiplet is running at Psafe). +///-OCC Heartbeat disable +///-Will be enabled by OCCFW (not FAPI) +///-If Venice, Chiplet IVRMs put into bypass mode and then disabled +///-This allows the initfiles and procedures to reload the Local PState and VDS Tables +///-Undervolting values reset: Kuv to 0; Puv_min and Puv_max each set to -128 each (to disable) +///-Local Pstate Frequency Target mechanism disabled +///-OCCFW will enable it +///-Issue reset to PCBS-PM (dial endp_reset_pm_only) +///-DPLL Frequ Control Reg is NOT reset +///-(Scan only value would be (tentative) 1GHz) +/// +/// +/// CONFIG +/// +/// PState translation +/// convert_safe_freq() - With ATTR_PM_SAFE_FREQUENCY (binary in MHz) and ATTR_PM_PSTATE0_FREQUENCY (binary in Mhz) produce ATTR_PM_SAFE_PSTATE +/// Resonant Clocking settings (band definitions from frequency to Pstate) +/// convert_resclk_freqs_to_pstates() - Convert the following frequency platform attributes (binary in MHz) to feature Pstate attributes. The conversion uses ATTR_PM_PSTATE0_FREQUENCY. +/// Input platform attributes +/// ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY +/// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY +/// output feature attributes +/// ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE +/// ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE +/// ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE +/// ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE +/// ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE +/// PFET Sequencing Delays +/// convert_pfet_delays() - Convert the following delays from platform attributes (binary in nanoseconds) to PFET delay value feature attributes. The conversion uses ATTR_PROC_NEST_FREQUENCY. +/// Input platform attributes +/// ATTR_PM_PFET_POWERUP_CORE_DELAY0 +/// ATTR_PM_PFET_POWERUP_CORE_DELAY1 +/// ATTR_PM_PFET_POWERUP_ECO_DELAY0 +/// ATTR_PM_PFET_POWERUP_ECO_DELAY1 +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 +/// output feature attributes +/// ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE +/// ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE +/// ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE +/// ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE +/// ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE +/// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE +/// ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE +/// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE +/// ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT +/// +/// +/// +/// INIT +/// +/// -Resets DPLL_CPM_PARM_REG.cpm_filter_enable +/// +/// - Sleep configuration +/// -ATTR_PM_SLEEP_TYPE (Deep or Fast) +/// -ATTR_PM_SLEEP_ENTRY (Assisted or Hardware) - depends on di/dt charateristics of the system (Assisted if power off serialization is needed, Hardware if the system can handle the unrelated powering off between cores. Hardware decreases entry latency ) +/// -ATTR_PM_SLEEP_EXIT (Assisted or Hardware) - set to Assisted (for both Fast and Deep). Fast for di/dt management; Deep as this necessary for restore. Setting to Hardware is a test mode for Fast only. +/// - Winkle configuration +/// -ATTR_PM_WINKLE_TYPE (Deep or Fast) +/// -ATTR_PM_WINKLE_ENTRY (Assisted or Hardware) +/// -ATTR_PM_WINKLE_EXIT (Assisted or Hardware) - set to Assisted (for both Fast and Deep). Fast for di/dt management; Deep as this necessary for restore. Setting to Hardware is a test mode for Fast only. +/// - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for reset case) +/// -For reset case, disable all "global_en" bits in PMCR and PMICR; this keeps Global Pstate Request from occuring to the PMC until it has been initialized. OCCFW to be do this. +/// - PMICR default value adjustment (Hardware flush 0 -> restore to TBD for reset ) +/// -How does policy influence the PMICR Pstate values? +/// -Base: run at the turbo value fixed +/// -Enhancement: run at the highest Pstate value on the chip. (needs power projection to judge worth). +/// -latency enable +/// -Not planned at this time. +/// OLD-DOC - Sleep / Winkle -> Fast / Deep configuration +/// OLD-DOC - Restore to Deep Sleep and Deep Winkle upon reset +/// OLD-DOC - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for reset case) SCAN0 +/// OLD-DOC -For reset case, disable all “global_en” bits in PMCR and PMICR; this keeps Global Pstate Request from occuring to the PMC until it has been initialized. OCCFW to be do this +/// OLD-DOC - PMICR default value adjustment (Hardware flush 0 -> restore to 0 for reset ) SCAN0 + + + +/// \todo add to required proc ENUM requests +/// + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pcbs_init.H" +#include "p8_pm.H" + +//---------------------------------------------------------------------- +// eCMD Includes +//---------------------------------------------------------------------- +#include <ecmdDataBufferBase.H> + + + + + + +extern "C" { + + + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- +// Address definition for chiplet EX01 with base address 0x10000000 +// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 +// CONST_UINT64_T( GP3_REG_0x100F0012 , ULL(0x100F0012) ); +// CONST_UINT64_T( FREQ_CTRL_REG_0x100F0151 , ULL(0x100F0151) ); +// CONST_UINT64_T( PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 , ULL(0x100F0153) ); +// CONST_UINT64_T( PCBS_iVRM_Control_Status_Reg_0x100F0154 , ULL(0x100F0154) ); +// CONST_UINT64_T( PCBSPM_MODE_REG_0x100F0156 , ULL(0x100F0156) ); +// CONST_UINT64_T( PCBS_UNDERVOLTING_REG_0x100F015B , ULL(0x100F015B) ); +// CONST_UINT64_T( PCBS_Power_Management_Bounds_Reg_0x100F015D , ULL(0x100F015D) ); +// CONST_UINT64_T( PCBS_OCC_Heartbeat_Reg_0x100F0164 , ULL(0x100F0164) ); +// CONST_UINT64_T( PCBS_Resonant_Clock_Control_Reg0_0x100F0165 , ULL(0x100F0165) ); +// CONST_UINT64_T( PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 , ULL(0x100F0168) ); + +// CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); +// CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); +// CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); +// CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); +// CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); +// CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); + + //------------------------------------------------------------------------------ + //Start scan zero value + //------------------------------------------------------------------------------ +/// \todo Review scan0 values + + CONST_UINT64_T( PMGP0_REG_0x100F0100_scan0 , ULL(0x8030010C21000000) ); + CONST_UINT64_T( PMGP1_REG_0x100F0103_scan0 , ULL(0x6C00000000000000) ); + CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106_scan0 , ULL(0x0A00000000000000) ); + CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E_scan0 , ULL(0xFFF0FFF080800000) ); //1000 0000 1000 000 + CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C_scan0 , ULL(0x80000000)); //1 + CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_FREQCNTL_0x100F0151_scan0 , ULL(0x32320000)); // "0011 0010 0011 0010 000000000000" ; + CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152_scan0 , ULL(0x00000200)); // "0000 0000 0000 0000 0000 0010 0000000" ; + CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156_scan0 , ULL(0x01000000)); //"0000 0001 0000 0000 00" ; + CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159_scan0 , ULL(0x00000000)) ; + CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0 , ULL(0x807F0000)); + CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0 , ULL(0x00000000)) ; + CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160_scan0 , ULL(0x00000000)) ; + CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0 , ULL(0x4000000000000000)) ; //"0100 00000000000000000000000000000000000000" ; + CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0 , ULL(0x00000000)); + CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0 , ULL(0x00000000)); + + //End scan zero value + + + + + + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +//fapi::ReturnCode rc; + +//uint32_t SIM_CYCLE_POLL_DELAY = 200000; // simulation cycle delay between status register polls +//uint32_t MAX_POLL_ATTEMPTS = 5; // maximum number of status poll attempts to make before giving up + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + +//ReturnCode p8_pcbs_init_core(Target &i_target, uint64_t mode, struct_pcbs_val_init_type pcbs_val_init); +//ReturnCode pgp_initializeMulticast( Target &i_target, bool VERBOSE ); + +fapi::ReturnCode delay( uint64_t i_nanoSeconds, uint64_t i_simCycles ); + +/// \todo : PSAFE, PUV_MIN, PUV_MAX - Attributes defined as unint8 but should be int8 +typedef struct { + uint8_t ivrms_enabled; // ATTR_IVRMS_ENABLED + uint8_t PSAFE; // ATTR_SAFE_PSTATE PSAFE + uint8_t PUV_MIN; // ATTR_PSTATE_UNDERVOLTING_MINIMUM + uint8_t PUV_MAX; // ATTR_PSTATE_UNDERVOLTING_MAXIMUM + uint32_t MAX_PSAFE_FSM_LOOPS; // max number of times PCBS-PMSR has been checked + uint32_t MAX_DELAY; // max number of Delay + uint32_t MAX_SIM_CYCLES; // max number of SimCycles (will be used when FSP is target) + int8_t GLOBAL_ACTUAL_PSTATE; // Global Actual PSTATE + int8_t MIN_PSTATE; // + int8_t FNOM; // + uint8_t DPLL_FMIN; // + uint8_t DPLL_FMAX; // + int8_t PMIN_CLIP; // + int8_t PMAX_CLIP; // + uint8_t KUV; // +} struct_pcbs_val_init_type; + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +// Reset function +fapi::ReturnCode p8_pcbs_init_reset (const fapi::Target& i_target, uint32_t i_mode, struct_pcbs_val_init_type pcbs_val_init); +// Config function +fapi::ReturnCode p8_pcbs_init_config (const fapi::Target& i_target) ; +// INIT +fapi::ReturnCode p8_pcbs_init_init (const fapi::Target& i_target) ; + + + + + +// ---------------------------------------------------------------------- +// p8_pcbs_init wrapper to fetch the attributes and pass it on to p8_pcbs_init_core +// ---------------------------------------------------------------------- +//ReturnCode p8_pcbs_init( Target &i_target, std::list<uint32_t> &args ) +fapi::ReturnCode p8_pcbs_init( + const Target& i_target, + uint32_t i_mode) +{ + fapi::ReturnCode rc; + + + + //Declare parms struct + struct_pcbs_val_init_type pcbs_val_init; + + + FAPI_DBG(""); + FAPI_DBG("*************************************"); + FAPI_INF("Executing p8_pcbs_init"); + FAPI_DBG("*************************************"); + FAPI_DBG(""); + + FAPI_INF("\t MODE: %d ", i_mode); + + + + + if ( i_mode == PM_CONFIG ) { + FAPI_DBG("*************************************"); + FAPI_INF("MODE: CONFIG , Calling: p8_pcbs_init_config "); + FAPI_DBG("*************************************"); + + rc=p8_pcbs_init_config(i_target); + if (rc) { + FAPI_ERR(" p8_pcbs_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else if ( i_mode == PM_INIT ) { + FAPI_DBG("*************************************"); + FAPI_INF("MODE: INIT , Calling: p8_pcbs_init_init"); + FAPI_DBG("*************************************"); + + rc=p8_pcbs_init_init(i_target); + if (rc) { + FAPI_ERR(" p8_pcbs_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else if ( i_mode == PM_RESET ) { + FAPI_DBG("*************************************"); + FAPI_INF("MODE: RESET"); + FAPI_DBG("*************************************"); + + + + // ****************************************************************** + + + + //Assign values to parms in struct + // should come from MRWB + // pcbs_val_init.ivrms_enabled = 1; // ATTR_PM_IVRMS_ENABLED VENICE or SALERNO + // pcbs_val_init.PSAFE = -128 ; // ATTR_PM_SAFE_PSTATE PSAFE + // pcbs_val_init.PUV_MIN = -128 ; // ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM + // pcbs_val_init.PUV_MAX = -128 ; // ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM + + + + rc = FAPI_ATTR_GET(ATTR_PM_IVRMS_ENABLED, &i_target, pcbs_val_init.ivrms_enabled); if (rc) return rc; //VENICE or SALERNO + rc = FAPI_ATTR_GET(ATTR_PM_SAFE_PSTATE, &i_target, pcbs_val_init.PSAFE); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &i_target, pcbs_val_init.PUV_MIN); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &i_target, pcbs_val_init.PUV_MAX); if (rc) return rc; + + + + + + // ---------------------------------------------------------------------- + // Assign default values + // ---------------------------------------------------------------------- + + /// \todo CHECK: Review those defaults + pcbs_val_init.MAX_PSAFE_FSM_LOOPS = 20; // max number of times PCBS-PMSR has been checked + pcbs_val_init.MAX_DELAY = 1000000; + pcbs_val_init.MAX_SIM_CYCLES = 1000; + pcbs_val_init.GLOBAL_ACTUAL_PSTATE = -128 ; // Global Actual PSTATE default + pcbs_val_init.MIN_PSTATE = -128 ; // Default + pcbs_val_init.FNOM = 128; // Default + pcbs_val_init.DPLL_FMIN = 50; // + pcbs_val_init.DPLL_FMAX = 50; // Default + pcbs_val_init.PMIN_CLIP = -128 ; // Default + pcbs_val_init.PMAX_CLIP = 127 ; // Default + pcbs_val_init.KUV = 0; // Default + + // ****************************************************************** + + + + + + FAPI_DBG("*************************************"); + FAPI_INF("Calling: p8_pcbs_init_reset"); + FAPI_DBG("*************************************"); + rc = p8_pcbs_init_reset( i_target, i_mode, pcbs_val_init); + + if (rc) { + FAPI_ERR(" p8_pcbs_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + } else { + FAPI_DBG("*************************************"); + FAPI_ERR("Unknown mode passed to p8_pcbs_init. Mode %x ....\n", i_mode); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_BAD_MODE); + FAPI_DBG("*************************************"); + + }; + + + +FAPI_INF("\t MODE: %d ", i_mode); + + return rc; + +} + + + +uint8_t convert_delay_to_value (uint32_t i_delay, uint32_t i_attr_proc_nest_frequency) +{ + uint8_t pfet_delay_value; + float dly; + //attr_proc_nest_frequency [MHz] + //delay [ns] + //pfet_delay_value = 15 - log2( i_delay * i_attr_proc_nest_frequency/1000); + // since log2 function is not available, this is done manual + //pfet_delay_value = 15 - log2( dly ); + dly = ( i_delay * i_attr_proc_nest_frequency/1000); + + if (dly <= 1.4 ) { pfet_delay_value = 15 - 0 ; } + else if ( ( 1.4 < dly ) && ( dly <= 2.8 ) ) { pfet_delay_value = 15 - 1 ; } + else if ( ( 2.8 < dly ) && ( dly <= 5.6 ) ) { pfet_delay_value = 15 - 2 ; } + else if ( ( 5.6 < dly ) && ( dly <= 11.5 ) ) { pfet_delay_value = 15 - 3 ; } + else if ( ( 11.5 < dly ) && ( dly <= 23 ) ) { pfet_delay_value = 15 - 4 ; } + else if ( ( 23 < dly ) && ( dly <= 46 ) ) { pfet_delay_value = 15 - 5 ; } + else if ( ( 46 < dly ) && ( dly <= 92 ) ) { pfet_delay_value = 15 - 6 ; } + else if ( ( 92 < dly ) && ( dly <= 182 ) ) { pfet_delay_value = 15 - 7 ; } + else if ( ( 182 < dly ) && ( dly <= 364 ) ) { pfet_delay_value = 15 - 8 ; } + else if ( ( 364 < dly ) && ( dly <= 728 ) ) { pfet_delay_value = 15 - 9 ; } + else if ( ( 728 < dly ) && ( dly <= 1456 ) ) { pfet_delay_value = 15 - 10 ; } + else if ( ( 1456 < dly ) && ( dly <= 2912 ) ) { pfet_delay_value = 15 - 11 ; } + else if ( ( 2912 < dly ) && ( dly <= 5824 ) ) { pfet_delay_value = 15 - 12 ; } + else if ( ( 5824 < dly ) && ( dly <= 11648 ) ) { pfet_delay_value = 15 - 13 ; } + else if ( ( 11648 < dly ) && ( dly <= 23296 ) ) { pfet_delay_value = 15 - 14 ; } + else if ( 23296 < dly ) { pfet_delay_value = 15 - 15 ; } + else { pfet_delay_value = 15 - 15 ; } ; + + + + + return (pfet_delay_value); +} + + +// Transform Platform Attribute for PCBS to Feature Attributes +fapi::ReturnCode +p8_pcbs_init_config(const Target& i_target) +{ + fapi::ReturnCode rc; + + /// PState translation + /// convert_safe_freq() - With ATTR_PM_SAFE_FREQUENCY (binary in MHz) and ATTR_PM_PSTATE0_FREQUENCY (binary in Mhz) produce ATTR_PM_SAFE_PSTATE + /// Resonant Clocking settings (band definitions from frequency to Pstate) + /// convert_resclk_freqs_to_pstates() - Convert the following frequency platform attributes (binary in MHz) to feature Pstate attributes. The conversion uses ATTR_PM_PSTATE0_FREQUENCY. + /// Input platform attributes + /// ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY + /// ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY + /// ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY + /// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY + /// ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY + /// output feature attributes + /// ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE + /// ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE + /// ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE + /// ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE + /// ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE + /// PFET Sequencing Delays + /// convert_pfet_delays() - Convert the following delays from platform attributes (binary in nanoseconds) to PFET delay value feature attributes. The conversion uses ATTR_PROC_NEST_FREQUENCY. + /// Input platform attributes + /// ATTR_PM_PFET_POWERUP_CORE_DELAY0 + /// ATTR_PM_PFET_POWERUP_CORE_DELAY1 + /// ATTR_PM_PFET_POWERUP_ECO_DELAY0 + /// ATTR_PM_PFET_POWERUP_ECO_DELAY1 + /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 + /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 + /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 + /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 + /// output feature attributes + /// ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE + /// ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE + /// ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT + /// ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE + /// ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE + /// ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT + /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE + /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE + /// ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT + /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE + /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE + /// ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT + + // ****************************************************************** + // attributes variables + uint32_t attr_proc_refclk_frequency ; + //uint32_t attr_pm_pstate0_frequency; + //uint8_t attr_pm_safe_pstate; + //uint32_t attr_pm_safe_frequency; + + uint32_t attr_pm_pfet_powerup_core_delay0; + uint32_t attr_pm_pfet_powerup_core_delay1; + uint32_t attr_pm_pfet_powerdown_core_delay0; + uint32_t attr_pm_pfet_powerdown_core_delay1; + uint32_t attr_pm_pfet_powerup_eco_delay0; + uint32_t attr_pm_pfet_powerup_eco_delay1; + uint32_t attr_pm_pfet_powerdown_eco_delay0; + uint32_t attr_pm_pfet_powerdown_eco_delay1; + + uint8_t attr_pm_pfet_powerup_core_delay0_value; + uint8_t attr_pm_pfet_powerup_core_delay1_value; + uint32_t attr_pm_pfet_powerup_core_sequence_delay_select; + uint8_t attr_pm_pfet_powerdown_core_delay0_value; + uint8_t attr_pm_pfet_powerdown_core_delay1_value; + uint32_t attr_pm_pfet_powerdown_core_sequence_delay_select; + uint8_t attr_pm_pfet_powerup_eco_delay0_value; + uint8_t attr_pm_pfet_powerup_eco_delay1_value; + uint32_t attr_pm_pfet_powerup_eco_sequence_delay_select; + uint8_t attr_pm_pfet_powerdown_eco_delay0_value; + uint8_t attr_pm_pfet_powerdown_eco_delay1_value; + uint32_t attr_pm_pfet_powerdown_eco_sequence_delay_select; + + + + // ****************************************************************** + // Get Attributes for pFET Delay + // ****************************************************************** + // ****************************************************************** + // set defaults if not available + /// \todo refclk ATTR_PROC_REFCLK_FREQUENCY OR ATTR_PROC_NEST_FREQUENCY ???? + attr_proc_refclk_frequency = 225; + // attr_pm_pfet_powerup_core_delay0 = 100; + // attr_pm_pfet_powerup_core_delay1 = 100; + // attr_pm_pfet_powerdown_core_delay0 = 100; + // attr_pm_pfet_powerdown_core_delay1 = 100; + // attr_pm_pfet_powerup_eco_delay0 = 100; + // attr_pm_pfet_powerup_eco_delay1 = 100; + // attr_pm_pfet_powerdown_eco_delay0 = 100; + // attr_pm_pfet_powerdown_eco_delay1 = 100; + + + + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_CORE_DELAY0, &i_target, attr_pm_pfet_powerup_core_delay0); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_CORE_DELAY1, &i_target, attr_pm_pfet_powerup_core_delay1); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY0, &i_target, attr_pm_pfet_powerdown_core_delay0); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY1, &i_target, attr_pm_pfet_powerdown_core_delay1); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_ECO_DELAY0, &i_target, attr_pm_pfet_powerup_eco_delay0); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERUP_ECO_DELAY1, &i_target, attr_pm_pfet_powerup_eco_delay1); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY0, &i_target, attr_pm_pfet_powerdown_eco_delay0); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY1, &i_target, attr_pm_pfet_powerdown_eco_delay1); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 with rc = 0x%x", (uint32_t)rc); return rc; } + + + + + + // ****************************************************************** + // Calculates Delay values out of pFET Delays + // ****************************************************************** + FAPI_DBG("*************************************"); + FAPI_DBG("Calculates Delay values out of pFET Delays"); + FAPI_DBG("*************************************"); + FAPI_DBG("*************************************"); + FAPI_DBG("Calculate:"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE"); + FAPI_DBG("using:"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY0"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_CORE_DELAY1"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY0"); + FAPI_DBG(" ATTR_PM_PFET_POWERUP_ECO_DELAY1"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY0"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_CORE_DELAY1"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY0"); + FAPI_DBG(" ATTR_PM_PFET_POWERDOWN_ECO_DELAY1"); + FAPI_DBG("**************************************************************************"); + FAPI_DBG(" Set ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); + FAPI_DBG(" Set ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); + FAPI_DBG(" Set ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); + FAPI_DBG(" Set ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT to 0 (choosing always pfetdelay0 )"); + FAPI_DBG("**************************************************************************"); + + + + + //value = 15 - log2(delay * refclk); + attr_pm_pfet_powerup_core_delay0_value = convert_delay_to_value(attr_pm_pfet_powerup_core_delay0, attr_proc_refclk_frequency); + attr_pm_pfet_powerup_core_delay1_value = convert_delay_to_value(attr_pm_pfet_powerup_core_delay1, attr_proc_refclk_frequency); + attr_pm_pfet_powerdown_core_delay0_value = convert_delay_to_value(attr_pm_pfet_powerdown_core_delay0 , attr_proc_refclk_frequency); + attr_pm_pfet_powerdown_core_delay1_value = convert_delay_to_value(attr_pm_pfet_powerdown_core_delay1 , attr_proc_refclk_frequency); + attr_pm_pfet_powerup_eco_delay0_value = convert_delay_to_value(attr_pm_pfet_powerup_eco_delay0 , attr_proc_refclk_frequency); + attr_pm_pfet_powerup_eco_delay1_value = convert_delay_to_value(attr_pm_pfet_powerup_eco_delay1 , attr_proc_refclk_frequency); + attr_pm_pfet_powerdown_eco_delay0_value = convert_delay_to_value(attr_pm_pfet_powerdown_eco_delay0 , attr_proc_refclk_frequency); + attr_pm_pfet_powerdown_eco_delay1_value = convert_delay_to_value(attr_pm_pfet_powerdown_eco_delay1 , attr_proc_refclk_frequency); + + attr_pm_pfet_powerup_core_sequence_delay_select = 0; // Choosing always delay0 + attr_pm_pfet_powerdown_core_sequence_delay_select = 0; + attr_pm_pfet_powerup_eco_sequence_delay_select = 0; + attr_pm_pfet_powerdown_eco_sequence_delay_select = 0; + + + + + + + FAPI_DBG("*************************************"); + FAPI_DBG("attr_pm_pfet_powerup_core_delay0_value : %X", attr_pm_pfet_powerup_core_delay0_value); + FAPI_DBG("attr_pm_pfet_powerup_core_delay1_value : %X", attr_pm_pfet_powerup_core_delay1_value); + FAPI_DBG("attr_pm_pfet_powerup_core_sequence_delay_select : %X", attr_pm_pfet_powerup_core_sequence_delay_select); + FAPI_DBG("attr_pm_pfet_powerdown_core_delay0_value : %X", attr_pm_pfet_powerdown_core_delay0_value); + FAPI_DBG("attr_pm_pfet_powerdown_core_delay1_value : %X", attr_pm_pfet_powerdown_core_delay1_value); + FAPI_DBG("attr_pm_pfet_powerdown_core_sequence_delay_select : %X", attr_pm_pfet_powerdown_core_sequence_delay_select); + FAPI_DBG("attr_pm_pfet_powerup_eco_delay0_value : %X", attr_pm_pfet_powerup_eco_delay0_value); + FAPI_DBG("attr_pm_pfet_powerup_eco_delay1_value : %X", attr_pm_pfet_powerup_eco_delay1_value); + FAPI_DBG("attr_pm_pfet_powerup_eco_sequence_delay_select : %X", attr_pm_pfet_powerup_eco_sequence_delay_select); + FAPI_DBG("attr_pm_pfet_powerdown_eco_delay0_value : %X", attr_pm_pfet_powerdown_eco_delay0_value); + FAPI_DBG("attr_pm_pfet_powerdown_eco_delay1_value : %X", attr_pm_pfet_powerdown_eco_delay1_value); + FAPI_DBG("attr_pm_pfet_powerdown_eco_sequence_delay_select : %X", attr_pm_pfet_powerdown_eco_sequence_delay_select); + FAPI_DBG("*************************************"); + + + + // ****************************************************************** + // Set Attributes for PFET delays + // ****************************************************************** + + + /// \todo DOUBLE Check ... Shouldn't the DELAY_SELECT -values be only readable??? read above and not written here??? + /// \todo ATTR_PM_PFET_POWERUP/DOWN_CORE/ECO_DELAY0/1_VALUE are defined in the spreadsheet as not writeable ???? + /// ---------------------------------------------------------- + /* rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE, &i_target, attr_pm_pfet_powerup_core_delay0_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE, &i_target, attr_pm_pfet_powerup_core_delay1_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerup_core_sequence_delay_select); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE, &i_target, attr_pm_pfet_powerdown_core_delay0_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE, &i_target, attr_pm_pfet_powerdown_core_delay1_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerdown_core_sequence_delay_select); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE, &i_target, attr_pm_pfet_powerup_eco_delay0_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE, &i_target, attr_pm_pfet_powerup_eco_delay1_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerup_eco_sequence_delay_select); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE, &i_target, attr_pm_pfet_powerdown_eco_delay0_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE, &i_target, attr_pm_pfet_powerdown_eco_delay1_value); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE with rc = 0x%x", (uint8_t)rc); return rc; } + + /// ---------------------------------------------------------- + rc = FAPI_ATTR_SET(ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT, &i_target, attr_pm_pfet_powerdown_eco_sequence_delay_select); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + */ + + + + + + + return rc; + +} //end CONFIG + + +fapi::ReturnCode +p8_pcbs_init_init(const Target& i_target) +{ + fapi::ReturnCode rc; + + + uint32_t l_rc; // local returncode + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + + // Variables + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. + + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + + + uint8_t pm_sleep_type; + uint8_t pm_sleep_entry ; + uint8_t pm_sleep_exit ; + uint8_t pm_winkle_type ; + uint8_t pm_winkle_entry ; + uint8_t pm_winkle_exit ; + + + + + // ****************************************************************** + // Getting Attributes + // ****************************************************************** + // pm_sleep_entry = 0; //0=assisted, 1=HW + // pm_sleep_exit = 0; //0=assisted, 1=HW + // pm_sleep_type = 1; //0=fast, 1=deep +/// \todo missing attributes + pm_winkle_entry = 0; + pm_winkle_exit = 0; + // pm_winkle_type = 1; + + + + rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_TYPE, &i_target, pm_sleep_type); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_TYPE with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_ENTRY, &i_target, pm_sleep_entry); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_ENTRY with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_EXIT, &i_target, pm_sleep_exit); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SLEEP_EXIT with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_WINKLE_TYPE, &i_target, pm_winkle_type); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_TYPE with rc = 0x%x", (uint32_t)rc); return rc; } +// rc = FAPI_ATTR_GET("ATTR_PM_WINKLE_ENTRY", &i_target,(unit8_t) pm_winkle_entry); +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_ENTRY with rc = 0x%x", (uint32_t)rc); return rc; } +// rc = FAPI_ATTR_GET("ATTR_PM_WINKLE_EXIT", &i_target,(unit8_t) pm_winkle_exit); +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_WINKLE_EXIT with rc = 0x%x", (uint32_t)rc); return rc; } + + + + + + + + + + + + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); + + + + + + // For each chiplet + + for (uint8_t c=0; c< l_exChiplets.size(); c++) { + FAPI_DBG("********* ******************* *********"); + FAPI_DBG("\t Loop Variable %d ",c); + FAPI_DBG("********* ******************* *********"); + + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); + return rc; + } else + { + if (l_functional) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("No functional chiplets exist"); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); + return rc; + } + else + { + + FAPI_DBG("Core number = %d", l_ex_number); + + // ****************************************************************** + // + // ****************************************************************** + + FAPI_DBG("**************************** *********"); + FAPI_INF("Reset CPM_FILTER_ENABLE"); + FAPI_DBG("**************************** *********"); + + // if debug mode read before + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of EX_DPLL_CPM_PARM_REG_0x1*0F0152 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + rc = fapiPutScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom Content of EX_DPLL_CPM_PARM_REG_0x1*0F0152, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of EX_DPLL_CPM_PARM_REG_0x1*0F0152 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + FAPI_INF ("Reset CPM_FILTER_ENABLE, clear bit 0 of EX_DPLL_CPM_PARM_REG_0x1*0F0152 " ); + + + + + // ****************************************************************** + // - set PMGP1_REG + // ****************************************************************** + + FAPI_INF("\t-----------------------------------------------------"); + FAPI_INF("\tPMGP1_REG Configuration "); + FAPI_INF("\t-----------------------------------------------------"); + FAPI_INF("\t pm_sleep_entry => %d ", pm_sleep_entry ); + FAPI_INF("\t pm_sleep_exit => %d ", pm_sleep_exit ); + FAPI_INF("\t pm_sleep_type => %d ", pm_sleep_type ); + FAPI_INF("\t pm_winkle_entry => %d ", pm_winkle_entry ); + FAPI_INF("\t pm_winkle_exit => %d ", pm_winkle_exit ); + FAPI_INF("\t pm_winkle_type => %d ", pm_winkle_type ); + FAPI_INF("\t " ); + FAPI_INF("\t " ); + FAPI_INF("\t-----------------------------------------------------"); + + + FAPI_DBG("*************************************"); + FAPI_INF("Write to register PMGP1_REG "); + FAPI_DBG("*************************************"); + + + // if debug mode read before + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of EX_PMGP1_REG_0_RWXx1*0F0103 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + + if (pm_sleep_entry) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WANDx100F0104) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + if (pm_sleep_exit) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(1); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(1); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + if (pm_sleep_type) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(2); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(2); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + if (pm_winkle_entry) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(3); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(3); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + if (pm_winkle_exit) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(4); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(4); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + if (pm_winkle_type) { + l_rc = data.flushTo0(); + l_rc |= data.setBit(5); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + } else { + l_rc = data.flushTo1(); + l_rc |= data.clearBit(5); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000) , data); + if (rc) { FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + }; + + + + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of EX_PMGP1_REG_0_RWXx1*0F0103 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + + + + + + + FAPI_DBG("*************************************"); + FAPI_INF("Write to Power_Management_Control_Reg "); + FAPI_DBG("*************************************"); + + // if debug mode read before + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 , Loop: %d : %s", c, data.getDoubleWord(0) ); + //} + + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom Content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 , Loop: %d : %s", c, data.getDoubleWord(0) ); + //} + FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Control_Reg_0x1*0F0159 " ); + + + + + FAPI_DBG("*************************************"); + FAPI_INF("Write to Power_Management_Idle_Control_Reg "); + FAPI_DBG("*************************************"); + + // if debug mode read before + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 , Loop: %d : %s", c, data.getDoubleWord(0) ); + //} + + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom Content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 , Loop: %d : %s", c, data.getDoubleWord(0) ); + //} + + FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " ); + + + + + } //ELSE IF functional and ATTR_CHIP_UNIT_POS + } else + { + // EX is not functional + FAPI_DBG("Core number = %d is not functional", c); + } //IF functional + }//ELSE IF ATTR_FUNCTIONAL + + } //END FOR + + return rc; + +} //end INIT + + +ReturnCode +p8_pcbs_init_reset(const Target &i_target, uint32_t i_mode, struct_pcbs_val_init_type pcbs_val_init) +{ + fapi::ReturnCode rc; + uint32_t l_rc; // local returncode + + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + + // Variables + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. + + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + uint32_t loopcount = 0; // number of times PCBS-PMSR has been checked + + const uint32_t SCANZERO = 1; // enable scan-zero loading upfront + + + // ****************************************************************** + // Code starts here + // ****************************************************************** + + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); + + + + + // For each chiplet + for (uint8_t c=0; c< l_exChiplets.size(); c++) { + FAPI_DBG("********* ******************* *********"); + FAPI_DBG("\t Loop Variable %d ",c); + FAPI_DBG("********* ******************* *********"); + + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); + return rc; + } else + { + if (l_functional) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("No functional chiplets exist"); + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); + return rc; + } + else + { + + FAPI_DBG("Core number = %d", l_ex_number); + + + + if (SCANZERO) { + // ****************************************************************** + // initialize all pm_reg with scan-zero values upfront + // ****************************************************************** + FAPI_DBG("***********************************************"); + FAPI_INF(" Set all PCBSLV_PM registers to the scan0 value"); + FAPI_DBG("***********************************************"); + + + /// \todo Review if scan0 values can/should be applied + //l_rc = data.setDoubleWord(0, PMGP0_REG_0x100F0100_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } + //rc = fapiPutScom(i_target, EX_PMGP0_0x100F0100 + (l_ex_number * 0x01000000), data ); + //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP0_REG_0_RWXx1*0F0100) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // Set in Multicast section above + //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } + //rc = fapiPutScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data ); + //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_RWXx1*0F0103) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setDoubleWord(0, EX_PFVddCntlStat_REG_0x100F0106_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PFVddCntlStat_REG_0x100F0106 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PFVddCntlStat_REG_0x1*0F0106) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setDoubleWord(0, EX_PFVcsCntlStat_REG_0x100F010E_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PFVcsCntlStat_REG_0x100F010E + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PFVcsCntlStat_REG_0x1*0F010E) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setDoubleWord(0, EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_Resonant_Clock_Control_Reg0_0x1*0F0165) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + l_rc = data.setWord(0, EX_PMErrMask_REG_0x100F010A_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMErrMask_REG_0x100F010A + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PMErrMask_REG_0x1*0F010A) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PMSpcWkupFSP_REG_0x100F010B_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMSpcWkupFSP_REG_0x100F010B + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(EX_PMSpcWkupFSP_REG_0x100F010B) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PMSpcWkupOCC_REG_0x100F010C_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMSpcWkupOCC_REG_0x100F010C + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PMSpcWkupOCC_REG_0x1*0F010C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PMSpcWkupPHYP_REG_0x100F010D_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PMSpcWkupPHYP_REG_0x100F010D + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PMSpcWkupPHYP_REG_0x1*0F010D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + + l_rc = data.setWord(0, EX_CorePFPUDly_REG_0x100F012C_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_CorePFPUDly_REG_0x100F012C + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(CorePFPUDly_REG_0x1*0F012C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_CorePFPDDly_REG_0x100F012D_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_CorePFPDDly_REG_0x100F012D + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(CorePFPDDly_REG_0x1*0F012D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_CorePFVRET_REG_0x100F0130_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_CorePFVRET_REG_0x100F0130 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(CorePFVRET_REG_0x1*0F0130) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + + l_rc = data.setWord(0, EX_ECOPFPUDly_REG_0x100F014C_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_ECOPFPUDly_REG_0x100F014C + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(ECOPFPUDly_REG_0x1*0F014C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_ECOPFPDDly_REG_0x100F014D_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_ECOPFPDDly_REG_0x100F014D + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(ECOPFPDDly_REG_0x1*0F014D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_ECOPFVRET_REG_0x100F0150_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_ECOPFVRET_REG_0x100F0150 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(ECOPFVRET_REG_0x1*0F0150) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + l_rc = data.setWord(0, EX_FREQCNTL_0x100F0151_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG_0x1*0F0151) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_DPLL_CPM_PARM_REG_0x100F0152_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(DPLL_CPM_PARM_REG_0x1*0F0152) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg_0x1*0F0154) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Value_Setting_Reg_0x1*0F0155) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // Scan0 values set per multicast + // l_rc = data.setWord(0, EX_PCBSPM_MODE_REG_0x100F0156_scan0); + // if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } + // rc = fapiPutScom(i_target, EX_PCBSPM_MODE_REG_0x100F0156 + (l_ex_number * 0x01000000), data ); + // if (l_rc) { FAPI_ERR("fapiGetScom(PCBSPM_MODE_REG_0x1*0F0156) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_Power_Management_Control_Reg_0x100F0159_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Control_Reg_0x100F0159 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Control_Reg_0x1*0F0159) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_PMC_VF_CTRL_REG_0x1*0F015A) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_UNDERVOLTING_REG_0x100F015B_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG_0x1*0F015B) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // Scan0 values set per multicast + //l_rc = data.setWord(0, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } + //rc = fapiPutScom(i_target, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + (l_ex_number * 0x01000000), data ); + //if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Bounds_Reg_0x1*0F015D) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_PSTATE_TABLE_CTRL_REG_0x1*0F015E) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //l_rc = data.setWord(0, EX_PCBS_Pstate_Step_Target_Register_0x100F0160_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + //rc = fapiPutScom(i_target, EX_PCBS_Pstate_Step_Target_Register_0x100F0160 + (l_ex_number * 0x01000000), data ); + //if (rc) { FAPI_ERR("fapiGetScom(PCBS_Pstate_Step_Target_Register_0x1*0F0160) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_VID_Control_Reg0_0x1*0F0162) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_VID_Control_Reg1_0x1*0F0163) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //l_rc = data.setWord(0, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + //rc = fapiPutScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data ); + //if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_Heartbeat_Reg_0x1*0F0164) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + l_rc = data.setWord(0, EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + rc = fapiPutScom(i_target, EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_Resonant_Clock_Control_Reg1_0x1*0F0166) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + /// \todo Regcheck error check at latest model + // l_rc = data.setWord(0, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0); + // if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)rc); rc.setEcmdError(l_rc); return rc; } + // rc = fapiPutScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data ); + // if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_Local_Pstate_Frequency_Target_Control_Register_0x1*0F0168) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + + } + + // ****************************************************************** + // Force safe mode + // ****************************************************************** + // ****************************************************************** + // - set PCBS_PM_PMGP1_REG_1 + // [12] force_safe_mode = 1 + // + // ****************************************************************** + + FAPI_DBG("********* ******************* *********"); + FAPI_INF("Force safe mode"); + FAPI_DBG("********* ******************* *********"); + + // Using Write OR to just set bit11 and bit12 + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // set scan0 value + // scan0: 6C00 content after iStep: 4800 + // bit2: 0: Vret (fast sleep) + // 1: Voff (deep sleep) + // bit5: 0: Vret (fast winkle) + // 1: Voff (deep winkle) + /// \todo Review if scan0 values can/should be applied + //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed."); return rc; } + + l_rc = data.setBit(12); //force_safe_mode = 1 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // simaet( "on" ); + rc = fapiPutScom(i_target, EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105, data ); + if (rc) { FAPI_ERR("fapiPutScom multicast (EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //if (VERBOSE) { + // FAPI_DBG("********* ******************* *********"); + // FAPI_DBG("Multicasted to EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 : %s", data.getDoubleWord(0)); + // FAPI_DBG("********* ******************* *********"); + //} + + + // manual debug + // getscom p8 -k0 -n0 -s0 -p00 130F0103 -ixl + // returns the expected values0x4818000000000000 + + //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; + //FAPI_DBG("XXXXXX Content of 0x130F0103 is : %s", data.getDoubleWord(0)); + + + // if debug mode read back + //if (VERBOSE) { + // if (chiplets_valid[c] == 1) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG("Content of PMGP1_REG_0_RWXx1*0F0103 is : %s , Loop: %d ", data.getDoubleWord(0) , c); + // + // //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; + // //FAPI_DBG(" XXX2 Content of 0x130F0103 is : %s", data.getDoubleWord(0)); + // } + // } + + FAPI_INF("Forced Safe Mode"); + + + // ****************************************************************** + // psafe Pstate achived AND FSM-stable ? + // ****************************************************************** + // ****************************************************************** + // - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active + // - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state + // + // ****************************************************************** + FAPI_DBG("**************************** *********"); + FAPI_INF("Psafe Pstate and FSM-stable?"); + FAPI_DBG("**************************** *********"); + + loopcount = 0; + rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + while( data.isBitClear( 33 ) || data.isBitClear( 36 ) ) { // loop until (safe_mode_active AND all_fsms_in_safe_state) + FAPI_DBG("\t loopcount => %d ",loopcount ); + + if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS ) // OR timeout .... set to 20 loops + { + FAPI_ERR( "Gave up waiting for Psafe Pstate and FSM-stable!\n" ); + FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT); + return rc; + } + + + // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content : %016llX", data.getDoubleWord(0)); + // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content bit 33 : %s", data.genBinStr(33,1).c_str()); + // FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content bit 36 : %s", data.genBinStr(36,1).c_str()); + + FAPI_INF("Is Psafe Pstate and FSM-stable ? \n"); + FAPI_DBG("\t Wait DELAY: %d ", pcbs_val_init.MAX_DELAY); + FAPI_DBG("\t Wait SimCycles: %d ", pcbs_val_init.MAX_SIM_CYCLES); + + /// \todo once available .. right now no delay + /// \todo fapiDelay( post_flush_cyc_dly, post_flush_timedly ); // delay for each cycle + + rc = fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES); + if (rc) { FAPI_ERR("fapi::delay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + } + + FAPI_INF("Psafe Pstate and FSM-stable is reached ...\n"); + + + + // ****************************************************************** + // DPLL settings + // ****************************************************************** + // ****************************************************************** + // - enable dpll override + // - PCBS_PM_PMGP1_REG_1[10] dpll_freq_override_enable + // - get Psafe and global actual pstate + // - calculate minPstate + // - calculate dpll_fmin = fnom + minPstate + // - set dpll_fmin + // - set dpll_fmax + // ****************************************************************** + FAPI_DBG("**************************** *********"); + FAPI_INF("DPLL settings"); + FAPI_DBG("**************************** *********"); + + //rc = fapiGetScom( i_target,PMGP1_REG_0_WORx100F00105 + (l_ex_number * 0x01000000) , data ); + //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx100F00105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Pre Write to PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); + //} + + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + l_rc = data.setBit(10); //dpll_freq_override_enable + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx1*0F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post Write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); + //} + + + FAPI_DBG("*************************************"); + FAPI_INF(" Start calculation of DPLL fmin ...."); + FAPI_DBG("*************************************"); + + + //get PSAFE and GLOBAL ACTUAL PSTATE EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + + FAPI_INF("DPLL fmin = %d , DPLL fmax = %d set", pcbs_val_init.DPLL_FMIN, pcbs_val_init.DPLL_FMAX); + + + rc = fapiGetScom( i_target,EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG_0x1*0F0164) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + FAPI_DBG("Read Psafe [17..24] of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 content : %016llX", data.getDoubleWord(0)); + + + + l_rc = data.shiftLeft(17); // Psafe is bit 17..24 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // assign Psafe to variable + pcbs_val_init.PSAFE = data.getByte(0); // + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiGetScom( i_target,EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_POWER_MANAGEMENT_STATUS_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + FAPI_DBG("Read GLOBAL_ACTUAL_PSTATE [0..7] of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content : %016llX", data.getDoubleWord(0)); + + + // assign GLOBAL_ACTUAL_PSTATE to variable + pcbs_val_init.GLOBAL_ACTUAL_PSTATE = data.getByte(0); // GLOBAL_ACTUAL_PSTATE is sbit 0..7 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + FAPI_INF("\t PSAFE => %d ", pcbs_val_init.PSAFE ); + FAPI_INF("\t GLOBAL_ACTUAL_PSTATE => %d ", pcbs_val_init.GLOBAL_ACTUAL_PSTATE ); + + + + // set the min_pstate to the smaller of Psafe and global actual pstate + // minPstate = min(Psafe,global actual pstate) + pcbs_val_init.MIN_PSTATE = pcbs_val_init.PSAFE < pcbs_val_init.GLOBAL_ACTUAL_PSTATE ? pcbs_val_init.PSAFE : pcbs_val_init.GLOBAL_ACTUAL_PSTATE ; + + //if (VERBOSE) { + FAPI_DBG("\t PSAFE => %d ", pcbs_val_init.PSAFE ); + FAPI_DBG("\t GLOBAL_ACTUAL_PSTATE => %d ", pcbs_val_init.GLOBAL_ACTUAL_PSTATE ); + FAPI_DBG("\t => MIN_PSTATE => %x ", pcbs_val_init.MIN_PSTATE ); + //} + + //set dpll_fmin = fnom + minPstate(signed) + /// \todo double check dpll_fmin not dpll_min + pcbs_val_init.DPLL_FMIN = pcbs_val_init.FNOM + pcbs_val_init.MIN_PSTATE ; + + //if (VERBOSE) { + FAPI_DBG("\t DPLL_FMIN = FNOM + MIN_PSTATE " ); + FAPI_DBG("\t DPLL_FMIN => %d ", pcbs_val_init.DPLL_FMIN ); + //} + + FAPI_DBG("*************************************"); + FAPI_INF(" End calculation of DPLL fmin ...."); + FAPI_DBG("*************************************"); + + + // Write calculated values to FREQ_CTRL_REG + rc = fapiGetScom( i_target,EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //if (VERBOSE) { + FAPI_DBG(" Pre write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); + //} + + // Clear buffer + l_rc = data.flushTo0(); + l_rc |= data.setByte(0, pcbs_val_init.DPLL_FMIN); + l_rc |= data.setByte(1, pcbs_val_init.DPLL_FMAX); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(FREQ_CTRL_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_FREQCNTL_0x100F0151 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of FREQ_CTRL_REG_0x1*0F0151 : %016llX", data.getDoubleWord(0)); + //} + + FAPI_INF("DPLL fmin = %d , DPLL fmax = %d set", pcbs_val_init.DPLL_FMIN, pcbs_val_init.DPLL_FMAX); + + + + + + // ****************************************************************** + // OCC SPR Mode + // ****************************************************************** + // ****************************************************************** + // - set PCBS_PM_PMGP1_REG_1 + // [11] PM_SPR_OVERRIDE_EN = 1 + // + // ****************************************************************** + + FAPI_DBG("********* ******************* *********"); + FAPI_INF("Force PM_SPR_OVERRIDE"); + FAPI_DBG("********* ******************* *********"); + + // Using Write OR to just set bit11 and bit12 + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // set scan0 value + // scan0: 6C00 content after iStep: 4800 + // bit2: 0: Vret (fast sleep) + // 1: Voff (deep sleep) + // bit5: 0: Vret (fast winkle) + // 1: Voff (deep winkle) + /// \todo Review if scan0 values can/should be applied + //l_rc = data.setDoubleWord(0, PMGP1_REG_0x100F0103_scan0); + //if (l_rc) { FAPI_ERR("Bit operation failed."); return rc; } + + l_rc = data.setBit(11); //Force OCC SPR Mode = 1 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // simaet( "on" ); + rc = fapiPutScom(i_target, EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105, data ); + if (rc) { FAPI_ERR("fapiPutScom multicast (EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + + //if (VERBOSE) { + FAPI_DBG("********* ******************* *********"); + FAPI_DBG("Multicasted to EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 : %016llX", data.getDoubleWord(0)); + FAPI_DBG("********* ******************* *********"); + //} + + + // manual debug + // getscom p8 -k0 -n0 -s0 -p00 130F0103 -ixl + // returns the expected values0x4818000000000000 + + //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; + //FAPI_DBG("XXXXXX Content of 0x130F0103 is : %016llX", data.getDoubleWord(0)); + + + // if debug mode read back + //if (VERBOSE) { + // if (chiplets_valid[c] == 1) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG("Content of PMGP1_REG_0_RWXx1*0F0103 is : %s , Loop: %016llX ", data.getDoubleWord(0) , c); + // + // //rc = fapiGetScom(i_target, 0x130F0103, data); if (l_rc) return rc; + // //FAPI_DBG(" XXX2 Content of 0x130F0103 is : %016llX", data.getDoubleWord(0)); + // } + //} + + FAPI_INF("Forced OCC SPR Mode"); + + + + + // ****************************************************************** + // - Disable Pstate mode + // - disable Pstate requests + // ****************************************************************** + FAPI_DBG("********* ******************* *********"); + FAPI_INF("Disable Pstate mode and disable Pstate requests"); + FAPI_DBG("********* ******************* *********"); + + //EX_PCBSPM_MODE_REG_0x100F0156_scan0 + /// \todo DoubleCheck: No OR-write available, using scan0 values as base and clearing bit 0 and bit 2 + l_rc = data.setWord(0, EX_PCBSPM_MODE_REG_0x100F0156_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(0); //Disable Pstate mode + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(2); //Disable Pstate requests + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + + rc = fapiPutScom(i_target, EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156, data ); + if (rc) { FAPI_ERR("fapiGetScom(EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + FAPI_DBG("Multicasted to EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 is : %016llX", data.getDoubleWord(0)); + + // if debug mode read back + //if (VERBOSE) { + // if (chiplets_valid[c] == 1) { + // rc = fapiGetScom(i_target, EX_PCBSPM_MODE_REG_0x100F0156 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Content of PCBSPM_MODE_REG_0x1*0F0156 : %016llX", data.getDoubleWord(0)); + // } + //} + FAPI_INF("Disabled Pstate mode"); + + // simaet( "off" ); + + // ****************************************************************** + // - Reset Pmin and Pmax + // ****************************************************************** + FAPI_DBG("********* ******************* *********"); + FAPI_INF("Reset Pmin and Pmax"); + FAPI_DBG("********* ******************* *********"); + // Clear data buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + // Set scan0 values + l_rc = data.setWord(0, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D_scan0); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + // + l_rc = data.setByte(0, pcbs_val_init.PMIN_CLIP); //Pmin_clip = -128 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.setByte(1, pcbs_val_init.PMAX_CLIP); //Pmax_clip = 127 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D, data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_Power_Management_Bounds_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + FAPI_DBG("Multicasted to PCBS_Power_Management_Bounds_Reg is : %016llX", data.getDoubleWord(0)); + + // if debug mode read back + //if (VERBOSE) { + // if (chiplets_valid[c] == 1) { + // rc = fapiGetScom(i_target, EX_PCBS_Power_Management_Bounds_Reg_0x100F015D + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG("Content of PCBS_Power_Management_Bounds_Reg_0x1*0F015D : %016llX", data.getDoubleWord(0)); + // } + //} + FAPI_INF("\t Pmin_clip => %d and Pmax_clip => %d ",pcbs_val_init.PMIN_CLIP,pcbs_val_init.PMAX_CLIP); + + + + + + + // ****************************************************************** + // Settings + // ****************************************************************** + // ****************************************************************** + + // - disable RESCLK + // - OCC Heartbeat disable + // ****************************************************************** + FAPI_DBG("**************************** *********"); + FAPI_INF("Settings about RESCLK"); + FAPI_DBG("**************************** *********"); + + // if debug mode read before + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_GP3_0x100F0012 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of GP3_REG_0_RWXx1*0F0012 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + + /// \todo : Double Check: Bit modifications in GP3... anything to take care here?? + // Using Write OR to just set bit22 + // Clear buffer + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + l_rc = data.setBit(22); //disable RESCLK + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + rc = fapiPutScom(i_target, EX_GP3_OR_0x100F0014 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom Content of GP3_REG_0_WORx1*0F0014, Loop: %d failed. With rc = 0x%x", c, (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_GP3_0x100F0012 + (l_ex_number * 0x01000000) , data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of GP3_REG_0_RWXx1*0F0012 , Loop: %d : %016llX", c, data.getDoubleWord(0) ); + //} + FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " ); + + + + //OCC Heartbeat disable + rc = fapiGetScom( i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + //if (VERBOSE) { + FAPI_DBG(" Pre write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); + //} + + l_rc = data.clearBit(8); //OCC Heartbeat disable + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + + rc = fapiPutScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_OCC_HEARTBEAT_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF ("OCC Heartbeat disabled, cleared bit 8 of PCBS_OCC_HEARTBEAT_REG_0x1*0F0164" ); + + + + + // ****************************************************************** + // IVRM Setup + // ****************************************************************** + // ****************************************************************** + // - if Venice ( ivrms_enabled) + // - disable ivrms + // - set bypass mode + // - reset undervolting values + // - disable LPFT + // ****************************************************************** + FAPI_DBG("**************************** *********"); + FAPI_INF("IVRM Setup"); + FAPI_DBG("**************************** *********"); + + if (pcbs_val_init.ivrms_enabled) { // If Venice + + // + rc = fapiGetScom( i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + //if (VERBOSE) { + FAPI_DBG(" Pre write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); + //} + + l_rc = data.clearBit(0); //disable ivrms + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(4); //ivrm_core_vdd_bypass_b + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(6); //ivrm_core_vcs_bypass_b + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(8); //ivrm_eco_vdd_bypass_b + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.clearBit(10); //ivrm_eco_vcs_bypass_b + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + + rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + // Write twice since ivrm_fsm_enable have to be 0 to enable the set the bypass modes + rc = fapiPutScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_iVRM_Control_Status_Reg) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post write content of PCBS_iVRM_Control_Status_Reg_0x1*0F0154 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF ("This is Venice: iVRMs disabled and in bypass-mode" ); + + + }; + + + + // + rc = fapiGetScom( i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000) , data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + // debug: data.flushTo1(); + //if (VERBOSE) { + FAPI_DBG(" Pre write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); + //} + /// \todo : Double check this bit settings + l_rc = data.setByte(2, pcbs_val_init.KUV); //Kuv = 0 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.shiftLeft(2); //Kuv is 6bit + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.setByte(0, pcbs_val_init.PUV_MIN); //Puv_min = -128 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + l_rc = data.setByte(1, pcbs_val_init.PUV_MAX); //Puv_max = -128 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PCBS_UNDERVOLTING_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + FAPI_DBG("\t PUV_MIN => %d ", pcbs_val_init.PUV_MIN ); + FAPI_DBG("\t PUV_MAX => %d ", pcbs_val_init.PUV_MAX ); + FAPI_DBG("\t KUV => %d ", pcbs_val_init.KUV ); + + //rc = fapiGetScom(i_target, EX_PCBS_UNDERVOLTING_REG_0x100F015B + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + //FAPI_DBG(" Post write content of PCBS_UNDERVOLTING_REG_0x1*0F015B : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF ("Undervolting values reset done" ); + + /// \todo : Debug Register access problems PCBS_LPFT_Control_Register_Reg0 . Already fixed in TPC-LIB chiplevel 8053 + /// \todo : Uncomment the following lines + // + // rc = fapiGetScom( i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000) , data ); + // if (l_rc) { FAPI_ERR("fapiGetScom(PCBS_LPFT_Control_Register_Reg0) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // data.clearBit(20); //Local Pstate Frequency Target mechanism disabled + + // rc = fapiPutScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data ); + // if (l_rc) { FAPI_ERR("fapiPutScom(PCBS_LPFT_Control_Register_Reg0) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + + // if debug mode read back + // if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Content of EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 : %016llX", data.getDoubleWord(0)); + // } + // FAPI_INF ("Local Pstate Frequency Target mechanism disabled" ); + + + // ****************************************************************** + // Issue reset to PCBS-PM + // ****************************************************************** + FAPI_DBG("**************************** *********"); + FAPI_INF("Reset PCBS-PM"); + FAPI_DBG("**************************** *********"); + + // + //rc = fapiGetScom( i_target,PMGP1_REG_0x100F00103 + (l_ex_number * 0x01000000) , data ); if (l_rc) return rc; + //if (l_rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0x100F00103) failed."); return rc; } + /// \todo : Double Check: Is that the right way to set and unset the reset or keep the reset longer and then unset it at the end ? + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Pre write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); + //} + + l_rc = data.flushTo0(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + l_rc = data.setBit(9); //endp_reset_pm_only = 1 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(PMGP1_REG_0_WORx1*0F0105) failed. With rc = 0x%x", (uint32_t)rc); return rc; } + /// \todo : Double check if RESET is effective + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post (set reset) write content of PMGP1_REG_0_RWXx1*0F0103 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF("Set reset to PCBS-PM"); + + l_rc = data.flushTo1(); + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + l_rc = data.clearBit(9); //endp_reset_pm_only = 0 + if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } + + rc = fapiPutScom(i_target, EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000), data ); + if (rc) { FAPI_ERR("fapiGetScom(EX_PMGP1_REG_0_WANDx100F0104) failed. With rc = 0x%x", (uint32_t)l_rc); return rc; } + + // if debug mode read back + //if (VERBOSE) { + // rc = fapiGetScom(i_target, EX_PMGP1_REG_0_RWXx100F0103 + (l_ex_number * 0x01000000), data); if (l_rc) return rc; + // FAPI_DBG(" Post (unset reset) content of EX_PMGP1_REG_0_RWXx100F0103 : %016llX", data.getDoubleWord(0)); + //} + FAPI_INF("Unset reset to PCBS-PM"); + + + + + + + } //ELSE IF functional and ATTR_CHIP_UNIT_POS + } else + { + // EX is not functional + FAPI_DBG("Core number = %d is not functional", c); + } //IF functional + }//ELSE IF ATTR_FUNCTIONAL + + } //END FOR + + + + + + + + + + FAPI_INF(""); + FAPI_INF("Executing p8_pcbs_init ....\n"); + + + return rc; +} // end RESET + + + + + + + + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H new file mode 100755 index 000000000..b60cddab1 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pcbs_init.H,v 1.2 2012/09/20 07:35:31 rmaier Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +// *! The purpose of this procedure is to establish the safe setting for PCBSLV +// *! o set psafe value +// *! o set PMIN clip/Pmax clip +// *! o PMCR default values +// *! o PMICR default values +// *! +// *! include file for pcbs_init with constants, definitions, prototypes +// *! +//------------------------------------------------------------------------------ +// + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pcbs_init_FP_t) (const fapi::Target&, uint32_t); + + +extern "C" { + + + + /// \param[in] &i_target Chip target + /// \param[in] mode Mode 1: CONFIG-Mode + /// Mode 2: RESET-Mode + /// Mode 3: INIT-Mode + + fapi::ReturnCode p8_pcbs_init (const fapi::Target& i_target, uint32_t mode); + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C new file mode 100755 index 000000000..6927d7f66 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C @@ -0,0 +1,211 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_firinit.C,v 1.3 2012/09/11 10:31:30 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com +// *! +/// \file p8_pm_init.C +/// \brief Calls each PM unit firinit procedrues to configure the FIRs to +/// predefined types : +/// +/// +/// +/// +/// +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ +/// +/// \todo Review +/// +/// +/// High-level procedure flow: +/// +/// \verbatim +/// - call p8_pm_pmc_firinit.C *chiptarget +/// - evaluate RC +/// +/// - call p8_pm_pba_firinit.C *chiptarget +/// - evaluate RC +/// +/// +/// \endverbatim +/// +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + + +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_firinit.H" +#include "p8_pm_pmc_firinit.H" +#include "p8_pm_pba_firinit.H" +#include "p8_pm_pcbs_firinit.H" +#include "p8_pm_oha_firinit.H" +#include "p8_pm_occ_firinit.H" + + + + +// #ifdef FAPIECMD +extern "C" { + // #endif + + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- +fapi::ReturnCode p8_pm_firinitlist(Target &i_target); + +// ---------------------------------------------------------------------- +// p8_pm_init +// ---------------------------------------------------------------------- + +fapi::ReturnCode +p8_pm_firinit(const fapi::Target &i_target ) +{ + + fapi::ReturnCode l_rc; + + + + // ****************************************************************** + // PMC_FIRS + // ****************************************************************** + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_rc, p8_pm_pmc_firinit , i_target ); + if (l_rc) + { + FAPI_ERR("ERROR: p8_pm_pmc_firinit detected failed result"); + return l_rc; + } + + + + // ****************************************************************** + // PBA + // ****************************************************************** + + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_rc, p8_pm_pba_firinit , i_target ); + if (l_rc) + { + FAPI_ERR("ERROR: p8_pm_pba_firinit detected failed result"); + return l_rc; + } + + + // ****************************************************************** + // OHA + // ****************************************************************** + + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_rc, p8_pm_oha_firinit , i_target ); + if (l_rc) + { + FAPI_ERR("ERROR: p8_pm_oha_firinit detected failed result"); + return l_rc; + } + + // ****************************************************************** + // PCBS + // ****************************************************************** + + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_rc, p8_pm_pcbs_firinit , i_target ); + if (l_rc) + { + FAPI_ERR("ERROR: p8_pm_pcbs_firinit detected failed result"); + return l_rc; + } + + + // ****************************************************************** + // OCC + // ****************************************************************** + + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_rc, p8_pm_occ_firinit , i_target ); + if (l_rc) + { + FAPI_ERR("ERROR: p8_pm_occ_firinit detected failed result"); + return l_rc; + } + + + + return l_rc; + +} + + + //#ifdef FAPIECMD +} //end extern C +//#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H new file mode 100755 index 000000000..1a2790c63 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H @@ -0,0 +1,121 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_firinit.H,v 1.5 2012/09/18 14:08:57 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_firinit.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_pm_firinit.H +// *! DESCRIPTION : common .H file for all FIRINITS +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// MACRO structure definitions +//------------------------------------------------------------------------------ + + #define SET_FIR_ACTION(b, x, y){ \ + if (x) { \ + e_rc |= action_0.setBit(b); \ + } \ + else \ + { \ + e_rc |= action_0.clearBit(b); \ + } \ + if (y) { \ + e_rc |= action_1.setBit(b); \ + } \ + else \ + { \ + e_rc |= action_1.clearBit(b); \ + }\ + } + + + + + #define SET_FIR_MASK(b,y){ \ + if (y) { \ + e_rc |= mask.setBit(b); \ + } \ + else \ + { \ + e_rc |= mask.clearBit(b); \ + } \ + } + + + +#define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +#define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +#define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +#define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +#define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} + + +typedef fapi::ReturnCode (*p8_pm_firinit_FP_t) (const fapi::Target& ); + + +extern "C" { + +/// \brief Calls each PM unit firinit procedures to configure the FIRs of the chip to predefined types : +/// \calls p8_pm_pmc_firinit +/// \calls p8_pm_pba_firinit +/// \calls p8_pm_pcbs_firinit +/// \calls p8_pm_oha_firinit +/// \calls p8_pm_occ_firinit + + +/// \ input chip_target +fapi::ReturnCode p8_pm_firinit(const fapi::Target& i_target ); + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C new file mode 100755 index 000000000..6cf80087d --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C @@ -0,0 +1,348 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_init.C,v 1.8 2012/10/10 14:33:49 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +/// \file p8_pm_init.C +/// \brief Calls each PM unit initialization procedures with the control +/// parameter to process the respective phase: +/// config: use Platform Attributes to create an effective +/// configuration using relevant Feature Attributes +/// init: use the Feature attributes to initialize the hardware +/// reset: call the "p8_pm_prep_reset" procedure to invoke a +/// reset of the hardware to allow for reinitialization +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ +/// +/// \version ------------------------------------------------------------------- +/// \version 1.0 stillgs 2012/03/06 Initial Version +/// \version ------------------------------------------------------------------- +/// +/// +/// \todo Review +/// +/// +/// High-level procedure flow: +/// +/// \verbatim +/// - call p8_pcbs_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_pmc_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_poreslw_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_poregpe_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_oha_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_pba_init.C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_occ_sram_init.C *chiptarget,mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_ocb_init .C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// - call p8_pss_init .C *chiptarget, mode (PM_CONFIG, PM_INIT, PM_RESET) +/// - evaluate RC +/// +/// \endverbatim +/// +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_pm_init.H" + +//#ifdef FAPIECMD +extern "C" { + //#endif + + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + fapi::ReturnCode p8_pm_list(const Target& i_target, uint32_t mode); + +// ---------------------------------------------------------------------- +// p8_pm_init +// ---------------------------------------------------------------------- + +fapi::ReturnCode +p8_pm_init(const fapi::Target &i_target, uint32_t mode) +{ + + fapi::ReturnCode l_fapi_rc; + + + // ****************************************************************** + + FAPI_INF("Executing p8_pm_init in mode %x ....\n", mode); + + /// ------------------------------- + /// Configuration/Initialation + if (mode == PM_CONFIG || mode == PM_INIT || mode == PM_RESET) + { + + l_fapi_rc = p8_pm_list(i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_list detected failed "); + return l_fapi_rc; + } + + + + } + /// ------------------------------- + /// Unsupported Mode + else + { + + FAPI_ERR("Unknown mode passed to p8_pm_init. Mode %x ....\n", mode); + uint32_t & MODE = mode; + FAPI_SET_HWP_ERROR(l_fapi_rc, RC_PROCPM_PMC_CODE_BAD_MODE); // proc_pmc_errors.xml + + } + + + return l_fapi_rc; +} + + +// ---------------------------------------------------------------------- +// p8_pm_list - process the underlying routines in the prescribed order +// ---------------------------------------------------------------------- + +fapi::ReturnCode +p8_pm_list(const Target& i_target, uint32_t mode) +{ + + fapi::ReturnCode l_fapi_rc; + + // ****************************************************************** + // PCBS_PM + // ****************************************************************** + + + FAPI_INF("Executing: p8_pcbs_init.C in mode %x", mode); + FAPI_EXEC_HWP(l_fapi_rc, p8_pcbs_init, i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PCBS_PM result"); + return l_fapi_rc; + } + + + + // ****************************************************************** + // PMC + // ****************************************************************** + + + FAPI_INF("Executing: p8_pmc_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_pmc_init, i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PMC result"); + return l_fapi_rc; + } + + // ****************************************************************** + // PORE Sleep/Winkle engine + // ****************************************************************** + + FAPI_INF("Executing: p8_poreslw_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_poreslw_init, i_target, mode); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE SLW result"); + return l_fapi_rc; + } + + // ****************************************************************** + // PORE General Purpose Engines + // ****************************************************************** + + FAPI_INF("Executing: p8_poregpe_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_poregpe_init, i_target, mode , GPEALL); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PORE GPE result"); + return l_fapi_rc; + } + + // ****************************************************************** + // OHA + // ****************************************************************** + + FAPI_INF("Executing: p8_oha_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_oha_init, i_target, PM_CONFIG ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OHA result"); + return l_fapi_rc; + } + + + // ****************************************************************** + // OCC-SRAM + // ****************************************************************** + + + FAPI_INF("Executing: p8_occ_sram_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_occ_sram_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCC-SRAM result"); + return l_fapi_rc; + } + + // ****************************************************************** + // OCB + // ****************************************************************** + + FAPI_INF("Executing: p8_ocb_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN0,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN1,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 1"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN2,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 2"); + return l_fapi_rc; + } + + FAPI_EXEC_HWP(l_fapi_rc, p8_ocb_init, i_target, mode,OCB_CHAN3,OCB_TYPE_NULL, 0x10000000, 1 , OCB_Q_OUFLOW_EN , OCB_Q_ITPTYPE_NOTFULL ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed OCB result on channel 0"); + return l_fapi_rc; + } + + // ****************************************************************** + // PSS + // ****************************************************************** + + + FAPI_INF("Executing:p8_pss_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_pss_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PSS result"); + return l_fapi_rc; + } + + + + + // ****************************************************************** + // PBA + // ****************************************************************** + + + FAPI_INF("Executing: p8_pba_init in mode %x", mode); + + FAPI_EXEC_HWP(l_fapi_rc, p8_pba_init, i_target, mode ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_pm_init detected failed PBA result"); + return l_fapi_rc; + } + + return l_fapi_rc; + +} + + + //#ifdef FAPIECMD +} //end extern C +//#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H new file mode 100755 index 000000000..cfb954875 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_init.H,v 1.4 2012/10/10 13:59:26 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com +// *! +// *! General Description: +// *! +// *! include file for p8_pm_effective with constants, definitions, prototypes +// *! +//------------------------------------------------------------------------------ +// + +#include "p8_pcbs_init.H" +#include "p8_pmc_init.H" +#include "p8_poreslw_init.H" +#include "p8_poregpe_init.H" +#include "p8_oha_init.H" +#include "p8_pba_init.H" //FIXME was not compiling check with Klaus +#include "p8_occ_sram_init.H" +#include "p8_ocb_init.H" +#include "p8_pss_init.H" + +/** +* @brief Function pointer typedef. +* +*/ + + + +typedef fapi::ReturnCode (*p8_pm_init_FP_t) (const fapi::Target&, uint32_t); + +extern "C" +{ + + +// enum p8_PM_FLOW_MODE { +// PM_CONFIG = 0x1, +// PM_RESET = 0x2, +// PM_INIT = 0x3, +// PM_SETUP = 0x4, +// PM_SETUP_PIB = 0x5, +// PM_SETUP_ALL = 0x6 +// }; + + +// Base function +/// \param[in] i_target chip Target +/// \param[in] mode PM_CONFIG, PM_INIT + + +fapi::ReturnCode p8_pm_init(const fapi::Target &i_target, uint32_t mode); + + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C new file mode 100755 index 000000000..5d6c1bbe2 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C @@ -0,0 +1,240 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_occ_firinit.C,v 1.6 2012/10/04 03:41:45 jimyac Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Jim Yacynych Email: jimyac@us.ibm.com +// *! +/// \file p8_pm_occ_firinit.C +/// \brief Configures the OCC LFIR Mask and Action + +/// \todo +/// +/// Procedure Prereq: +/// o System clocks are running +/// \endverbatim +//------------------------------------------------------------------------------ + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_firinit.H" +#include "p8_pm_occ_firinit.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Macro definitions +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +/// \param[in] i_target => Chip Target + +/// \retval FAPI_RC_SUCCESS +/// \retval ERROR +fapi::ReturnCode +p8_pm_occ_firinit(const fapi::Target& i_target) +{ + ReturnCode rc; + ecmdDataBufferBase action_0(64); + ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + FAPI_INF("Executing p8_pm_occ_firinit ....\n"); + + // make action default be RECOV_ATTN - "01" + e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = action_1.flushTo1(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // make mask default be unmasked - "0" + e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // ------------------------------------------------------------------------ + // set the action and mask for the OCC LFIR bits using the following macros + // ------------------------------------------------------------------------ + // Action0/1 Setting Macros - 4 possible settings + // SET_CHECK_STOP(b) - sets action0/1 to "00" for LFIR bit b + // SET_RECOV_ATTN(b) - sets action0/1 to "01" for LFIR bit b + // SET_RECOV_INTR(b) - sets action0/1 to "10" for LFIR bit b + // SET_MALF_ALERT(b) - sets action0/1 to "11" for LFIR bit b + // + // Mask Setting Macro + // SET_FIR_MASKED(b) - sets mask to '1' for LFIR bit b + // ------------------------------------------------------------------------ + + SET_MALF_ALERT(0); // 0 = occ_fw0 + SET_MALF_ALERT(1); // 1 = occ_fw1 + SET_MALF_ALERT(2); // 2 = occ_fw2 + SET_MALF_ALERT(3); // 3 = occ_fw3 + SET_MALF_ALERT(4); // 4 = pmc_pore_sw_malf + SET_MALF_ALERT(5); // 5 = pmc_occ_hb_malf + + SET_FIR_MASKED(6); // 6 = pore_gpe0_fatal_err + SET_FIR_MASKED(7); // 7 = pore_gpe1_fatal_err + SET_FIR_MASKED(8); // 8 = ocb_error + + SET_RECOV_ATTN(9); // 9 = srt_ue + SET_RECOV_ATTN(10); // 10 = srt_ce + SET_RECOV_ATTN(11); // 11 = srt_read_error + SET_RECOV_ATTN(12); // 12 = srt_write_error + SET_RECOV_ATTN(13); // 13 = srt_dataout_perr + SET_RECOV_ATTN(14); // 14 = srt_oci_write_data_parity + SET_RECOV_ATTN(15); // 15 = srt_oci_be_parity_err + SET_RECOV_ATTN(16); // 16 = srt_oci_addr_parity_err + + SET_FIR_MASKED(17); // 17 = pore_sw_error_err + SET_FIR_MASKED(18); // 18 = pore_gpe0_error_err + SET_FIR_MASKED(19); // 19 = pore_gpe1_error_err + SET_FIR_MASKED(20); // 20 = external_trap + SET_FIR_MASKED(21); // 21 = ppc405_core_reset + SET_FIR_MASKED(22); // 22 = ppc405_chip_reset + SET_FIR_MASKED(23); // 23 = ppc405_system_reset + SET_FIR_MASKED(24); // 24 = ppc405_dbgmsrwe + SET_FIR_MASKED(25); // 25 = ppc405_dbgstopack + + SET_RECOV_ATTN(26); // 26 = ocb_db_oci_timeout + SET_RECOV_ATTN(27); // 27 = ocb_db_oci_read_data_parity + SET_RECOV_ATTN(28); // 28 = ocb_db_oci_slave_error + SET_RECOV_ATTN(29); // 29 = ocb_pib_addr_parity_err + SET_RECOV_ATTN(30); // 30 = ocb_db_pib_data_parity_err + SET_RECOV_ATTN(31); // 31 = ocb_idc0_error + SET_RECOV_ATTN(32); // 32 = ocb_idc1_error + SET_RECOV_ATTN(33); // 33 = ocb_idc2_error + SET_RECOV_ATTN(34); // 34 = ocb_idc3_error + SET_RECOV_ATTN(35); // 35 = srt_fsm_err + SET_RECOV_ATTN(36); // 36 = jtagacc_err + + SET_FIR_MASKED(37); // 37 = spare_err_37 + + SET_RECOV_ATTN(38); // 38 = c405_ecc_ue + SET_RECOV_ATTN(39); // 39 = c405_ecc_ce + + SET_FIR_MASKED(40); // 40 = c405_oci_machinecheck + + SET_RECOV_ATTN(41); // 41 = sram_spare_direct_error0 + SET_RECOV_ATTN(42); // 42 = sram_spare_direct_error1 + SET_RECOV_ATTN(43); // 43 = sram_spare_direct_error2 + SET_RECOV_ATTN(44); // 44 = sram_spare_direct_error3 + SET_RECOV_ATTN(45); // 45 = slw_ocislv_err + SET_RECOV_ATTN(46); // 46 = gpe_ocislv_err + SET_RECOV_ATTN(47); // 47 = ocb_ocislv_err + SET_RECOV_ATTN(48); // 48 = c405icu_m_timeout + SET_RECOV_ATTN(49); // 49 = c405dcu_m_timeout + + SET_FIR_MASKED(50); // 50 = spare_fir + SET_FIR_MASKED(51); // 51 = spare_fir + SET_FIR_MASKED(52); // 52 = spare_fir + SET_FIR_MASKED(53); // 53 = spare_fir + SET_FIR_MASKED(54); // 54 = spare_fir + SET_FIR_MASKED(55); // 55 = spare_fir + SET_FIR_MASKED(56); // 56 = spare_fir + SET_FIR_MASKED(57); // 57 = spare_fir + SET_FIR_MASKED(58); // 58 = spare_fir + SET_FIR_MASKED(59); // 59 = spare_fir + SET_FIR_MASKED(60); // 60 = spare_fir + SET_FIR_MASKED(61); // 61 = spare_fir + + SET_RECOV_ATTN(62); // 62 = fir_parity_err_dup + SET_RECOV_ATTN(63); // 63 = fir_parity_err + + if (e_rc){ + rc.setEcmdError(e_rc); + return rc; + } + + FAPI_INF(" action_0 => %016llX ", action_0.getDoubleWord(0)); + FAPI_INF(" action_1 => %016llX ", action_1.getDoubleWord(0)); + FAPI_INF(" mask => %016llX ", mask.getDoubleWord(0)); + + // --------------- + // OCC_FIR_ACTION0 + // --------------- + rc = fapiPutScom(i_target, OCC_LFIR_ACT0_0x01010806, action_0 ); + if (!rc.ok()) { + FAPI_ERR("fapiPutScom(OCC_LFIR_ACT0_0x01010806) failed."); + return rc; + } + + // ---------------- + // OCC_FIR_ACTION1 + // ---------------- + rc = fapiPutScom(i_target, OCC_LFIR_ACT1_0x01010807, action_1 ); + if (!rc.ok()) { + FAPI_ERR("fapiPutScom(OCC_LFIR_ACT1_0x01010807) failed."); + return rc; + } + + // ------------ + // OCC_FIR_MASK + // ------------ + rc = fapiPutScom(i_target, OCC_LFIR_MASK_0x01010803, mask ); + if (!rc.ok()) { + FAPI_ERR("fapiPutScom(OCC_LFIR_MASK_0x01010803) failed."); + return rc; + } + + return rc ; +} // end p8_pm_occ_firinit + +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H new file mode 100755 index 000000000..46ff64379 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H @@ -0,0 +1,74 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_occ_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_occ_firinit.H,v 1.3 2012/09/14 19:35:06 jimyac Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_occ_firinit.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : proc_pm_oha_firinit.H +// *! DESCRIPTION : Configures the OCC LFIR Mask and Action +// *! +// *! OWNER NAME: Jim Yacynych Email: jimyac@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _P8_PM_OCC_FIRINIT_H_ +#define _P8_PM_OCC_FIRINIT_H_ + +#include <fapi.H> + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_occ_firinit_FP_t) (const fapi::Target&); + +extern "C" { +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \brief Configures the OCC LFIR Mask and Action +/// \param[in] i_target => Chip Target + +fapi::ReturnCode +p8_pm_occ_firinit(const fapi::Target& i_target); + +} // extern "C" + +#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C new file mode 100755 index 000000000..7c98c1472 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C @@ -0,0 +1,188 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_oha_firinit.C,v 1.4 2012/09/16 05:10:14 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Joe Procwriter Email: asmartpersion@xx.ibm.com +// *! +// *! General Description: Configures the FIR errors +// *! +// *! The purpose of this procedure is to ...... +// *! +// *! High-level procedure flow: +// *! o Do thing 1 +// *! o Do thing 2 +// *! o Do thing 3 +// *! o Check if all went well +// *! o If so celebrate +// *! o Else write logs, set bad return code +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_oha_firinit.H" +#include "p8_pm_firinit.H" + + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- +// #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +// #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +// #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +// #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +// #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + + + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + + +// function: xxx +// parameters: none +// returns: ECMD_SUCCESS if something good happens, +// BAD_RETURN_CODE otherwise +ReturnCode +p8_pm_oha_firinit(const fapi::Target &i_target ) +{ + ReturnCode rc; + // ecmdDataBufferBase action_0(64); +// ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + std::vector<fapi::Target> l_chiplets; + std::vector<Target>::iterator itr; + + + // FAPI_INF(""); + FAPI_INF("Executing proc_pm_oha_firinit ....\n"); + + + +//#--OHA_ERROR_AND_ERROR_MASK_REG:0..1 WREG=0x0E OHA error and error mask register +//#-- tpc_oha1_mac_inst.error_mask 0..5 SCOM +//#-- 0..5 RW oha_error_mask Error mask for OHA/DPLL error reporting registers + + + + + + + e_rc |= mask.flushTo0(); + + + SET_FIR_MASKED(0); // oha21_ppt_timeout_err + SET_FIR_MASKED(1); // NOT CPM_bit_synced + SET_FIR_MASKED(2); // aiss_hang_condition + SET_FIR_MASKED(3); // tc_tc_therm_trip0 + SET_FIR_MASKED(4); // tc_tc_therm_trip1 + SET_FIR_MASKED(5); // pcb_err_to_fir + + if (e_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)e_rc); rc.setEcmdError(e_rc); return rc; } + + + +// #--****************************************************************************** +// #-- Mask EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E +// #--****************************************************************************** + + rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets, TARGET_STATE_FUNCTIONAL); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); + + for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ + + + + rc = fapiPutScom((*itr), EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E, mask ); + if (rc) { + FAPI_ERR("fapiPutScom(EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E) failed."); return rc; + } + + FAPI_INF("Done in current chiplet ....\n"); + + } + + + + + + return rc ; + + +} // Procedure + + +} //end extern C + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H new file mode 100755 index 000000000..40d24b4f1 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_oha_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_oha_firinit.H,v 1.2 2012/09/16 05:10:21 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_oha_firinit.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_pm_oha_firinit.H +// *! DESCRIPTION : SETS OHA firs to proper error settings +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_oha_firinit_FP_t) (const fapi::Target& ); + +extern "C" { + + +fapi::ReturnCode +p8_pm_oha_firinit(const fapi::Target& i_target ); + /// input CHIPTARGET + + +} // extern "C" + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C new file mode 100755 index 000000000..7a8578fef --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C @@ -0,0 +1,321 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pba_firinit.C,v 1.10 2012/10/05 08:44:02 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com +// *! +// *! General Description: +// *! +// *! The purpose of this procedure is to ...... +// *! +// *! High-level procedure flow: +// *! o Set the particluar bits of databuffers action0 , action 1 and mask for the correspoding actions via MACROS +// *! o Write the action1 , actionn0 and mask registers of FIRs +// *! o +// *! o +// *! o +// *! o +// *! o Check if all went well +// *! o If so celebrate +// *! o Else write logs, set bad return code +// *! +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_firinit.H" +#include "p8_pm_pba_firinit.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + + // \todo move these to p8_scom_addresses after testing + // CONST_UINT64_T( PBA_FIR_ACTION1_0x02010847 , ULL(0x02010847)) ; + // CONST_UINT64_T( PBA_FIR_ACTION0_0x02010846 , ULL(0x02010846)) ; + CONST_UINT64_T( PBA_FIR_MASK_WR_0x02010843 , ULL(0x02010843)) ; + CONST_UINT64_T( PBA_FIR_MASK_WR_AND_0x02010844 , ULL(0x02010844)) ; + CONST_UINT64_T( PBA_FIR_MASK_WR_OR_0x02010845 , ULL(0x02010845)) ; + + +// ---------------------------------------------------------------------- +// Macro definitions +// ---------------------------------------------------------------------- + + + +// #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +// #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +// #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +// #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +// #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + + + + +fapi::ReturnCode +p8_pm_pba_firinit(const fapi::Target& i_target ) +{ + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_pba_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of PBA macro +// parameters: i_target => chip target + +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ + + + + enum PBA_FIRS + { + + PBAFIR_OCI_APAR_ERR = 0 , + PBAFIR_PB_RDADRERR_FW =1 , + PBAFIR_PB_RDDATATO_FW =2 , + PBAFIR_PB_SUE_FW =3 , + PBAFIR_PB_UE_FW =4 , + PBAFIR_PB_CE_FW =5 , + PBAFIR_OCI_SLAVE_INIT =6 , + PBAFIR_OCI_WRPAR_ERR =7 , + PBAFIR_OCI_REREQTO =8 , + PBAFIR_PB_UNEXPCRESP =9 , + PBAFIR_PB_UNEXPDATA =10 , + PBAFIR_PB_PARITY_ERR =11 , + PBAFIR_PB_WRADRERR_FW =12 , + PBAFIR_PB_BADCRESP =13 , + PBAFIR_PB_ACKDEAD_FW_RD =14 , + PBAFIR_PB_CRESPTO =15 , + PBAFIR_BCUE_SETUP_ERR =16 , + PBAFIR_BCUE_PB_ACK_DEAD =17 , + PBAFIR_BCUE_PB_ADRERR =18 , + PBAFIR_BCUE_OCI_DATERR =19 , + PBAFIR_BCDE_SETUP_ERR =20 , + PBAFIR_BCDE_PB_ACK_DEAD =21 , + PBAFIR_BCDE_PB_ADRERR =22 , + PBAFIR_BCDE_RDDATATO_ERR =23 , + PBAFIR_BCDE_SUE_ERR =24 , + PBAFIR_BCDE_UE_ERR =25 , + PBAFIR_BCDE_CE =26 , + PBAFIR_BCDE_OCI_DATERR =27 , + PBAFIR_INTERNAL_ERR =28 , + PBAFIR_ILLEGAL_CACHE_OP =29 , + PBAFIR_OCI_BAD_REG_ADDR =30 , + PBAFIR_AXPUSH_WRERR =31 , + PBAFIR_AXRCV_DLO_ERR =32 , + PBAFIR_AXRCV_DLO_TO =33 , + PBAFIR_AXRCV_RSVDATA_TO =34 , + PBAFIR_AXFLOW_ERR =35 , + PBAFIR_AXSND_DHI_RTYTO =36 , + PBAFIR_AXSND_DLO_RTYTO =37 , + PBAFIR_AXSND_RSVTO =38 , + PBAFIR_AXSND_RSVERR =39 , + PBAFIR_PB_ACKDEAD_FW_WR =40 , + PBAFIR_RESERVED_41 =41 , + PBAFIR_RESERVED_42 =42 , + PBAFIR_RESERVED_43 =43 , + PBAFIR_FIR_PARITY_ERR2 =44 , + PBAFIR_FIR_PARITY_ERR =45 + + }; + + + + fapi::ReturnCode rc; + ecmdDataBufferBase action_0(64); + ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + + + FAPI_INF(""); + FAPI_INF("Executing p8_pm_pba_firinit ....\n"); + + e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = action_1.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + SET_RECOV_ATTN (PBAFIR_OCI_APAR_ERR ) ; // 0 PBAFIR_OCI_APAR_ERR + SET_RECOV_ATTN (PBAFIR_PB_RDADRERR_FW ) ; // 1 PBAFIR_PB_RDADRERR_FW + SET_RECOV_ATTN (PBAFIR_PB_RDDATATO_FW ) ; // 2 PBAFIR_PB_RDDATATO_FW + SET_RECOV_ATTN (PBAFIR_PB_SUE_FW ) ; // 3 PBAFIR_PB_SUE_FW + SET_RECOV_ATTN (PBAFIR_PB_UE_FW ) ; // 4 PBAFIR_PB_UE_FW + SET_RECOV_ATTN (PBAFIR_PB_CE_FW ) ; // 5 PBAFIR_PB_CE_FW + SET_RECOV_ATTN (PBAFIR_OCI_SLAVE_INIT ) ; // 6 PBAFIR_OCI_SLAVE_INIT + SET_RECOV_ATTN (PBAFIR_OCI_WRPAR_ERR ) ; // 7 PBAFIR_OCI_WRPAR_ERR + SET_RECOV_ATTN (PBAFIR_OCI_REREQTO ) ; // 8 PBAFIR_OCI_REREQTO + SET_RECOV_ATTN (PBAFIR_PB_UNEXPCRESP ) ; // 9 PBAFIR_PB_UNEXPCRESP + SET_RECOV_ATTN (PBAFIR_PB_UNEXPDATA ) ; // 10 PBAFIR_PB_UNEXPDATA + SET_RECOV_ATTN (PBAFIR_PB_PARITY_ERR ) ; // 11 PBAFIR_PB_PARITY_ERR + SET_RECOV_ATTN (PBAFIR_PB_WRADRERR_FW ) ; // 12 PBAFIR_PB_WRADRERR_FW + SET_RECOV_ATTN (PBAFIR_PB_BADCRESP ) ; // 13 PBAFIR_PB_BADCRESP + SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_RD ) ; // 14 PBAFIR_PB_ACKDEAD_FW_RD + SET_RECOV_ATTN (PBAFIR_PB_CRESPTO ) ; // 15 PBAFIR_PB_CRESPTO + SET_FIR_MASKED (PBAFIR_BCUE_SETUP_ERR ) ; // 16 PBAFIR_BCUE_SETUP_ERR + SET_FIR_MASKED (PBAFIR_BCUE_PB_ACK_DEAD ) ; // 17 PBAFIR_BCUE_PB_ACK_DEAD + SET_FIR_MASKED (PBAFIR_BCUE_PB_ADRERR ) ; // 18 PBAFIR_BCUE_PB_ADRERR + SET_FIR_MASKED (PBAFIR_BCUE_OCI_DATERR ) ; // 19 PBAFIR_BCUE_OCI_DATERR + SET_FIR_MASKED (PBAFIR_BCDE_SETUP_ERR ) ; // 20 PBAFIR_BCDE_SETUP_ERR + SET_FIR_MASKED (PBAFIR_BCDE_PB_ACK_DEAD ) ; // 21 PBAFIR_BCDE_PB_ACK_DEAD + SET_FIR_MASKED (PBAFIR_BCDE_PB_ADRERR ) ; // 22 PBAFIR_BCDE_PB_ADRERR + SET_FIR_MASKED (PBAFIR_BCDE_RDDATATO_ERR ) ; // 23 PBAFIR_BCDE_RDDATATO_ERR + SET_FIR_MASKED (PBAFIR_BCDE_SUE_ERR ) ; // 24 PBAFIR_BCDE_SUE_ERR + SET_FIR_MASKED (PBAFIR_BCDE_UE_ERR ) ; // 25 PBAFIR_BCDE_UE_ERR + SET_FIR_MASKED (PBAFIR_BCDE_CE ) ; // 26 PBAFIR_BCDE_CE + SET_FIR_MASKED (PBAFIR_BCDE_OCI_DATERR ) ; // 27 PBAFIR_BCDE_OCI_DATERR + SET_RECOV_ATTN (PBAFIR_INTERNAL_ERR ) ; // 28 PBAFIR_INTERNAL_ERR + SET_RECOV_ATTN (PBAFIR_ILLEGAL_CACHE_OP ) ; // 29 PBAFIR_ILLEGAL_CACHE_OP + SET_RECOV_ATTN (PBAFIR_OCI_BAD_REG_ADDR ) ; // 30 PBAFIR_OCI_BAD_REG_ADDR + SET_FIR_MASKED (PBAFIR_AXPUSH_WRERR ) ; // 31 PBAFIR_AXPUSH_WRERR + SET_FIR_MASKED (PBAFIR_AXRCV_DLO_ERR ) ; // 32 PBAFIR_AXRCV_DLO_ERR + SET_FIR_MASKED (PBAFIR_AXRCV_DLO_TO ) ; // 33 PBAFIR_AXRCV_DLO_TO + SET_FIR_MASKED (PBAFIR_AXRCV_RSVDATA_TO ) ; // 34 PBAFIR_AXRCV_RSVDATA_TO + SET_FIR_MASKED (PBAFIR_AXFLOW_ERR ) ; // 35 PBAFIR_AXFLOW_ERR + SET_FIR_MASKED (PBAFIR_AXSND_DHI_RTYTO ) ; // 36 PBAFIR_AXSND_DHI_RTYTO + SET_FIR_MASKED (PBAFIR_AXSND_DLO_RTYTO ) ; // 37 PBAFIR_AXSND_DLO_RTYTO + SET_FIR_MASKED (PBAFIR_AXSND_RSVTO ) ; // 38 PBAFIR_AXSND_RSVTO + SET_FIR_MASKED (PBAFIR_AXSND_RSVERR ) ; // 39 PBAFIR_AXSND_RSVERR + SET_RECOV_ATTN (PBAFIR_PB_ACKDEAD_FW_WR ) ; // 40 PBAFIR_PB_ACKDEAD_FW_WR + SET_FIR_MASKED (PBAFIR_RESERVED_41 ) ; // 41 PBAFIR_RESERVED_41 + SET_FIR_MASKED (PBAFIR_RESERVED_42 ) ; // 42 PBAFIR_RESERVED_42 + SET_FIR_MASKED (PBAFIR_RESERVED_43 ) ; // 43 PBAFIR_RESERVED_43 + SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR2 ) ; // 44 PBAFIR_FIR_PARITY_ERR2 + SET_RECOV_ATTN (PBAFIR_FIR_PARITY_ERR ) ; // 45 PBAFIR_FIR_PARITY_ERR + + + if (e_rc) { rc.setEcmdError(e_rc); return rc; } + +// FAPI_INF(" action_0 => %s ", action_0.genHexRightStr(0,64).c_str()); +// FAPI_INF(" action_1 => %s ", action_1.genHexRightStr(0,64).c_str()); +// FAPI_INF(" mask => %s ", mask.genHexRightStr(0,64).c_str()); + + + //#--****************************************************************************** + //#-- PBA_FIR_ACTION0 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PBA_FIR_ACTION0_0x02010846, action_0 ); + if (rc) { + FAPI_ERR("fapiPutScom(PBA_FIR_ACTION0_0x02010846) failed."); return rc; + } + + //#--****************************************************************************** + //#-- PBA_FIR_ACTION1 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PBA_FIR_ACTION1_0x02010847, action_1 ); + if (rc) { + FAPI_ERR("fapiPutScom(PBA_FIR_ACTION1_0x02010847) failed."); return rc; + } + + + //--****************************************************************************** + //-- PBA_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PBA_FIR_MASK_WR_0x02010843, mask ); + if (rc) { + FAPI_ERR("fapiPutScom(PBA_FIR_MASK_WR_0x02010843) failed."); return rc; + } + + + + + + + + + + + + return rc ; + + +} // Procedure + + +} //end extern C + + + + +// ---------------------------------------------------------------------- +// BACKUPS +// ---------------------------------------------------------------------- + +// #define RECOV_INTR 1, 0 +// #define RECOV_ATTN 0, 1 +// #define MALF_ALERT 1, 1 + + +// SET_FIR_ACTION( 1 ,1 ,0) ; +// SET_FIR_ACTION( 2, 0, 1) ; +// SET_FIR_ACTION( 3, 1, 1) ; SET_FIR_MASK(3, 1) ; + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H new file mode 100755 index 000000000..26af3d887 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H @@ -0,0 +1,81 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pba_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pba_firinit.H,v 1.3 2012/09/24 08:44:38 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pba_firinit.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_pm_pba_firinit.H +// *! DESCRIPTION : SET PBA FIRINITS +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_pba_firinit_FP_t) (const fapi::Target& ); + +extern "C" { + + +fapi::ReturnCode +p8_pm_pba_firinit(const fapi::Target& i_target ); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_pba_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of OHA macro +// parameters: i_target => chip target + +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ + +} // extern "C" + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C new file mode 100755 index 000000000..c141f7ee4 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C @@ -0,0 +1,268 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pcbs_firinit.C,v 1.7 2012/10/16 13:43:50 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +/// \file p8_pm_pcbs_firinit.C +/// \brief Configures the PCBS FIR errors + +/// \todo +/// +/// \verbatim +/// +/// Procedure Prereq: +/// - completed istep procedure +/// +/// High-level procedure flow: +/// +/// get all functional child chiplets +/// +/// loop over all functional chiplets { +/// calculate address +/// set the error mask in order to mask all errors +/// +/// } +/// +/// \endverbatim +//------------------------------------------------------------------------------ + + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_pcbs_firinit.H" +#include "p8_pm_firinit.H" + + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + + + +// ---------------------------------------------------------------------- +// Macro definitions +// ---------------------------------------------------------------------- +// ALL the below Macros are calling other macros SET_FIR_ACTION / SET_FIR_MASK . +// Whcih are present in p8_pm_firinit.H +// #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +// #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +// #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +// #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +// #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + + + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + + +fapi::ReturnCode +p8_pm_pcbs_firinit(const fapi::Target &i_target ) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase action_0(64); + ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + std::vector<fapi::Target> l_exChiplets; + fapi::TargetState l_state = TARGET_STATE_FUNCTIONAL; // TARGET_STATE_PRESENT or TARGET_STATE_FUNCTIONAL. It just depends on what you want to do. + + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + uint32_t e_rc = 0; + + + + FAPI_INF(""); + FAPI_INF("Executing proc_pm_pcbs_firinit ....\n"); + + + + + + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_HANG_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ASSIST_HANG_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_ENTRY_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_SLEEP_EXIT_INVOKE_PORE_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_ENTRY_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_ENTRY_SEND_INT_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_NOTIFY_PMC_ERR_MASK); + SET_FIR_MASKED(PCBS_WAIT_DPLL_LOCK_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE8_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WINKLE_EXIT_SEND_INT_POWUP_ASSIST_ERR_MASK); + SET_FIR_MASKED(PCBS_WRITE_FSM_GOTO_REG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_WRITE_PMGP0_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_FREQ_OVERFLOW_IN_PSTATE_MODE_ERR_MASK); + SET_FIR_MASKED(PCBS_ECO_RS_BYPASS_CONFUSION_ERR_MASK); + SET_FIR_MASKED(PCBS_CORE_RS_BYPASS_CONFUSION_ERR_MASK); + SET_FIR_MASKED(PCBS_READ_LPST_IN_PSTATE_MODE_ERR_MASK); + SET_FIR_MASKED(PCBS_LPST_READ_CORR_ERR_MASK); + SET_FIR_MASKED(PCBS_LPST_READ_UNCORR_ERR_MASK); + SET_FIR_MASKED(PCBS_PFET_STRENGTH_OVERFLOW_ERR_MASK); + SET_FIR_MASKED(PCBS_VDS_LOOKUP_ERR_MASK); + SET_FIR_MASKED(PCBS_IDLE_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_PSTATE_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_PMAX_SYNC_INTERRUPT_TIMEOUT_ERR_MASK); + SET_FIR_MASKED(PCBS_GLOBAL_ACTUAL_PSTATE_PROTOCOL_ERR_MASK); + SET_FIR_MASKED(PCBS_PMAX_PROTOCOL_ERR_MASK); + SET_FIR_MASKED(PCBS_IVRM_GROSS_OR_FINE_ERR_MASK); + SET_FIR_MASKED(PCBS_IVRM_RANGE_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_CPM_FMIN_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_DCO_FULL_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_DCO_EMPTY_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_INT_ERR_MASK); + SET_FIR_MASKED(PCBS_FMIN_AND_NOT_CPMBIT_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_FASTER_THAN_FMAX_PLUS_DELTA1_ERR_MASK); + SET_FIR_MASKED(PCBS_DPLL_SLOWER_THAN_FMIN_MINUS_DELTA2_ERR_MASK); + SET_FIR_MASKED(PCBS_RESCLK_CSB_INSTR_VECTOR_CHG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_RESLKC_BAND_BOUNDARY_CHG_IN_INVALID_STATE_ERR_MASK); + SET_FIR_MASKED(PCBS_OCC_HEARTBEAT_LOSS_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE39_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE40_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE41_ERR_MASK); + SET_FIR_MASKED(PCBS_SPARE42_ERR_MASK); + + + if(e_rc){rc.setEcmdError(e_rc); return rc;} + +// e_rc = mask.flushTo1(); +// if (e_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", e_rc); rc.setEcmdError(e_rc); return rc; } + + + + // #--****************************************************************************** + // #-- Mask EX_PMErrMask_REG_0x100F010A + // #--****************************************************************************** + + + + rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_EX_CHIPLET, l_exChiplets, l_state); if (rc) return rc; + FAPI_DBG(" chiplet vector size => %u", l_exChiplets.size()); + + + + for (uint8_t c=0; c< l_exChiplets.size(); c++) { + FAPI_DBG("********* ******************* *********"); + FAPI_DBG("\t Loop Variable %d ",c); + FAPI_DBG("********* ******************* *********"); + + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL with rc = 0x%x", (uint32_t)rc); + return rc; + } + else + { + if (l_functional) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); + return rc; + } + + else + { + + FAPI_DBG("Core number = %d", l_ex_number); + // Use the l_ex_number to build the SCOM address; + rc = fapiPutScom(i_target, EX_PMErrMask_REG_0x100F010A + (l_ex_number * 0x01000000), mask ); + if (rc) { + FAPI_ERR("fapiPutScom(EX_PMErrMask_REG_0x100F010A) failed."); return rc; + } + + FAPI_INF("Done with current core %d ....\n", l_ex_number); + + } + } + else + { + // EX is not functional + FAPI_DBG("Core number = %d is not functional", c); + } + } + + + } + + return rc ; + + +} // Procedure + + +} //end extern C + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H new file mode 100755 index 000000000..51de0646c --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H @@ -0,0 +1,169 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pcbs_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pcbs_firinit.H,v 1.2 2012/09/19 09:55:21 rmaier Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pcbs_firinit.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_pm_pcbs_firinit.H +// *! DESCRIPTION : Configures the PCBS FIR errors +// *! +// *! OWNER NAME : Ralf Maier Email: ralf.maier@de.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_pcbs_firinit_FP_t) (const fapi::Target& ); + + + +// 0x010A PM Error Mask Register +// pm_reg.pm_error_mask_lt 0..42 PCB +// 0 RW pcbs_sleep_entry_notify_pmc_hang_err_mask Mask for this error: 1=masked, 0=not masked +// 1 RW pcbs_sleep_entry_notify_pmc_assist_hang_err_mask Mask for this error: 1=masked, 0=not masked +// 2 RW pcbs_sleep_entry_notify_pmc_err_mask Mask for this error: 1=masked, 0=not masked +// 3 RW pcbs_sleep_exit_invoke_pore_err_mask Mask for this error: 1=masked, 0=not masked +// 4 RW pcbs_winkle_entry_notify_pmc_err_mask Mask for this error: 1=masked, 0=not masked +// 5 RW pcbs_winkle_entry_send_int_assist_err_mask Mask for this error: 1=masked, 0=not masked +// 6 RW pcbs_winkle_exit_notify_pmc_err_mask Mask for this error: 1=masked, 0=not masked +// 7 RW pcbs_wait_dpll_lock_err_mask Mask for this error: 1=masked, 0=not masked +// 8 RW pcbs_spare8_err_mask Mask for this error: 1=masked, 0=not masked +// 9 RW pcbs_winkle_exit_send_int_assist_err_mask Mask for this error: 1=masked, 0=not masked +// 10 RW pcbs_winkle_exit_send_int_powup_assist_err_mask Mask for this error: 1=masked, 0=not masked +// 11 RW pcbs_write_fsm_goto_reg_in_invalid_state_err_mask Mask for this error: 1=masked, 0=not masked +// 12 RW pcbs_write_pmgp0_in_invalid_state_err_mask Mask for this error: 1=masked, 0=not masked +// 13 RW pcbs_freq_overflow_in_pstate_mode_err_mask Mask for this error: 1=masked, 0=not masked +// 14 RW pcbs_eco_rs_bypass_confusion_err_mask Mask for this error: 1=masked, 0=not masked +// 15 RW pcbs_core_rs_bypass_confusion_err_mask Mask for this error: 1=masked, 0=not masked +// 16 RW pcbs_read_lpst_in_pstate_mode_err_mask Mask for this error: 1=masked, 0=not masked +// 17 RW pcbs_lpst_read_corr_err_mask Mask for this error: 1=masked, 0=not masked +// 18 RW pcbs_lpst_read_uncorr_err_mask Mask for this error: 1=masked, 0=not masked +// 19 RW pcbs_pfet_strength_overflow_err_mask Mask for this error: 1=masked, 0=not masked +// 20 RW pcbs_vds_lookup_err_mask Mask for this error: 1=masked, 0=not masked +// 21 RW pcbs_idle_interrupt_timeout_err_mask Mask for this error: 1=masked, 0=not masked +// 22 RW pcbs_pstate_interrupt_timeout_err_mask Mask for this error: 1=masked, 0=not masked +// 23 RW pcbs_global_actual_sync_interrupt_timeout_err_mask Mask for this error: 1=masked, 0=not masked +// 24 RW pcbs_pmax_sync_interrupt_timeout_err_mask Mask for this error: 1=masked, 0=not masked +// 25 RW pcbs_global_actual_pstate_protocol_err_mask Mask for this error: 1=masked, 0=not masked +// 26 RW pcbs_pmax_protocol_err_mask Mask for this error: 1=masked, 0=not masked +// 27 RW pcbs_ivrm_gross_or_fine_err_mask Mask for this error: 1=masked, 0=not masked +// 28 RW pcbs_ivrm_range_err_mask Mask for this error: 1=masked, 0=not masked +// 29 RW pcbs_dpll_cpm_fmin_err_mask Mask for this error: 1=masked, 0=not masked +// 30 RW pcbs_dpll_dco_full_err_mask Mask for this error: 1=masked, 0=not masked +// 31 RW pcbs_dpll_dco_empty_err_mask Mask for this error: 1=masked, 0=not masked +// 32 RW pcbs_dpll_int_err_mask Mask for this error: 1=masked, 0=not masked +// 33 RW pcbs_fmin_and_not_cpmbit_err_mask Mask for this error: 1=masked, 0=not masked +// 34 RW pcbs_dpll_faster_than_fmax_plus_delta1_err_mask Mask for this error: 1=masked, 0=not masked +// 35 RW pcbs_dpll_slower_than_fmin_minus_delta2_err_mask Mask for this error: 1=masked, 0=not masked +// 36 RW pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask Mask for this error: 1=masked, 0=not masked +// 37 RW pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask Mask for this error: 1=masked, 0=not masked +// 38 RW pcbs_occ_heartbeat_loss_err_mask Mask for this error: 1=masked, 0=not masked +// 39 RW pcbs_spare39_err_mask Mask for this error: 1=masked, 0=not masked +// 40 RW pcbs_spare40_err_mask Mask for this error: 1=masked, 0=not masked +// 41 RW pcbs_spare41_err_mask Mask for this error: 1=masked, 0=not masked +// 42 RW pcbs_spare42_err_mask Mask for this error: 1=masked, 0=not masked + + +enum +{ + PCBS_SLEEP_ENTRY_NOTIFY_PMC_HANG_ERR_MASK = 0, + PCBS_SLEEP_ENTRY_NOTIFY_PMC_ASSIST_HANG_ERR_MASK = 1, + PCBS_SLEEP_ENTRY_NOTIFY_PMC_ERR_MASK = 2, + PCBS_SLEEP_EXIT_INVOKE_PORE_ERR_MASK = 3, + PCBS_WINKLE_ENTRY_NOTIFY_PMC_ERR_MASK = 4, + PCBS_WINKLE_ENTRY_SEND_INT_ASSIST_ERR_MASK = 5, + PCBS_WINKLE_EXIT_NOTIFY_PMC_ERR_MASK = 6, + PCBS_WAIT_DPLL_LOCK_ERR_MASK = 7, + PCBS_SPARE8_ERR_MASK = 8, + PCBS_WINKLE_EXIT_SEND_INT_ASSIST_ERR_MASK = 9, + PCBS_WINKLE_EXIT_SEND_INT_POWUP_ASSIST_ERR_MASK = 10, + PCBS_WRITE_FSM_GOTO_REG_IN_INVALID_STATE_ERR_MASK = 11, + PCBS_WRITE_PMGP0_IN_INVALID_STATE_ERR_MASK = 12, + PCBS_FREQ_OVERFLOW_IN_PSTATE_MODE_ERR_MASK = 13, + PCBS_ECO_RS_BYPASS_CONFUSION_ERR_MASK = 14, + PCBS_CORE_RS_BYPASS_CONFUSION_ERR_MASK = 15, + PCBS_READ_LPST_IN_PSTATE_MODE_ERR_MASK = 16, + PCBS_LPST_READ_CORR_ERR_MASK = 17, + PCBS_LPST_READ_UNCORR_ERR_MASK = 18, + PCBS_PFET_STRENGTH_OVERFLOW_ERR_MASK = 19, + PCBS_VDS_LOOKUP_ERR_MASK = 20, + PCBS_IDLE_INTERRUPT_TIMEOUT_ERR_MASK = 21, + PCBS_PSTATE_INTERRUPT_TIMEOUT_ERR_MASK = 22, + PCBS_GLOBAL_ACTUAL_SYNC_INTERRUPT_TIMEOUT_ERR_MASK = 23, + PCBS_PMAX_SYNC_INTERRUPT_TIMEOUT_ERR_MASK = 24, + PCBS_GLOBAL_ACTUAL_PSTATE_PROTOCOL_ERR_MASK = 25, + PCBS_PMAX_PROTOCOL_ERR_MASK = 26, + PCBS_IVRM_GROSS_OR_FINE_ERR_MASK = 27, + PCBS_IVRM_RANGE_ERR_MASK = 28, + PCBS_DPLL_CPM_FMIN_ERR_MASK = 29, + PCBS_DPLL_DCO_FULL_ERR_MASK = 30, + PCBS_DPLL_DCO_EMPTY_ERR_MASK = 31, + PCBS_DPLL_INT_ERR_MASK = 32, + PCBS_FMIN_AND_NOT_CPMBIT_ERR_MASK = 33, + PCBS_DPLL_FASTER_THAN_FMAX_PLUS_DELTA1_ERR_MASK = 34, + PCBS_DPLL_SLOWER_THAN_FMIN_MINUS_DELTA2_ERR_MASK = 35, + PCBS_RESCLK_CSB_INSTR_VECTOR_CHG_IN_INVALID_STATE_ERR_MASK = 36, + PCBS_RESLKC_BAND_BOUNDARY_CHG_IN_INVALID_STATE_ERR_MASK = 37, + PCBS_OCC_HEARTBEAT_LOSS_ERR_MASK = 38, + PCBS_SPARE39_ERR_MASK = 39, + PCBS_SPARE40_ERR_MASK = 40, + PCBS_SPARE41_ERR_MASK = 41, + PCBS_SPARE42_ERR_MASK = 42 +} ; + + + + +extern "C" { + +/// \param[in] &i_target Chip target + +fapi::ReturnCode p8_pm_pcbs_firinit(const fapi::Target& i_target ); + + +} // extern "C" + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C new file mode 100755 index 000000000..bab789d0a --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C @@ -0,0 +1,303 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pmc_firinit.C,v 1.7 2012/10/05 08:44:13 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com +// *! +// *! General Description: Configures the FIR errors +// *! +// *! The purpose of this procedure is to ...... +// *! +// *! High-level procedure flow: +// *! o Set the particluar bits of databuffers action0 , action 1 and mask for the correspoding actions via MACROS +// *! o Write the action1 , actionn0 and mask registers of FIRs +// *! o Check if all went well +// *! o If so celebrate +// *! o Else write logs, set bad return code +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include "p8_scom_addresses.H" +#include "p8_pm_firinit.H" +#include "p8_pm_pmc_firinit.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + + // \todo move these to p8_scom_addresses after testing + CONST_UINT64_T( PMC_FIR_ACTION1_0x01010847 , ULL(0x01010847)) ; + CONST_UINT64_T( PMC_FIR_ACTION0_0x01010846 , ULL(0x01010846)) ; + CONST_UINT64_T( PMC_FIR_MASK_WR_0x01010843 , ULL(0x01010843)) ; + CONST_UINT64_T( PMC_FIR_MASK_WR_AND_0x01010844 , ULL(0x01010844)) ; + CONST_UINT64_T( PMC_FIR_MASK_WR_OR_0x01010845 , ULL(0x01010845)) ; + + +// ---------------------------------------------------------------------- +// Macro definitions +// ---------------------------------------------------------------------- +// ALL the below Macros are calling other macros SET_FIR_ACTION / SET_FIR_MASK . +// Whcih are present in p8_pm_firinit.H +// #define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +// #define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +// #define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +// #define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +// #define SET_FIR_MASKED(b){SET_FIR_MASK(b,1);} + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + + + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_pmc_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of PMC macro +// parameters: i_target => chip target + +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ + +fapi::ReturnCode +p8_pm_pmc_firinit(const fapi::Target& i_target ) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase action_0(64); + ecmdDataBufferBase action_1(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + enum PMC_FIRS + { + + PSTATE_OCI_MASTER_RDERR = 0 , + PSTATE_OCI_MASTER_RDDATA_PARITY_ERR =1 , + PSTATE_GPST_CHECKBYTE_ERR =2 , + PSTATE_GACK_TO_ERR =3 , + PSTATE_PIB_MASTER_NONOFFLINE_ERR =4 , + PSTATE_PIB_MASTER_OFFLINE_ERR =5 , + PSTATE_OCI_MASTER_TO_ERR =6 , + PSTATE_INTERCHIP_UE_ERR =7 , + PSTATE_INTERCHIP_ERRORFRAME_ERR =8 , + PSTATE_MS_FSM_ERR =9 , + MS_COMP_PARITY_ERR =10 , + IDLE_PORESW_FATAL_ERR =11 , + IDLE_PORESW_STATUS_RC_ERR =12 , + IDLE_PORESW_STATUS_VALUE_ERR =13 , + IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR =14 , + IDLE_PORESW_TIMEOUT_ERR =15 , + IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR =16 , + IDLE_INTERNAL_ERR =17 , + INT_COMP_PARITY_ERR =18 , + PMC_OCC_HEARTBEAT_TIMEOUT =19 , + SPIVID_CRC_ERROR0 =20 , + SPIVID_CRC_ERROR1 =21 , + SPIVID_CRC_ERROR2 =22 , + SPIVID_RETRY_TIMEOUT =23 , + SPIVID_FSM_ERR =24 , + SPIVID_MAJORITY_DETECTED_A_MINORITY =25 , + O2S_CRC_ERROR0 =26 , + O2S_CRC_ERROR1 =27 , + O2S_CRC_ERROR2 =28 , + O2S_RETRY_TIMEOUT =29 , + O2S_WRITE_WHILE_BRIDGE_BUSY_ERR =30 , + O2S_FSM_ERR =31 , + O2S_MAJORITY_DETECTED_A_MINORITY =32 , + O2P_WRITE_WHILE_BRIDGE_BUSY_ERR =33 , + O2P_FSM_ERR =34 , + OCI_SLAVE_ERR =35 , + IF_COMP_PARITY_ERR =36 , + FIR_PARITY_ERR_DUP =47 , + FIR_PARITY_ERR =48 + + + }; + + + + + + + FAPI_INF(""); + FAPI_INF("Executing p8_pm_pmc_firinit ....\n"); + + e_rc = action_0.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = action_1.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = mask.flushTo0() ; if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + + + + + SET_RECOV_INTR(PSTATE_OCI_MASTER_RDERR ) ; // pstate_oci_master_rderr + SET_RECOV_INTR(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR ); // pstate_oci_master_rddata_parity_err + SET_RECOV_INTR(PSTATE_GPST_CHECKBYTE_ERR ); // pstate_gpst_checkbyte_err + SET_RECOV_INTR(PSTATE_GACK_TO_ERR ); // pstate_gack_to_err + SET_RECOV_INTR(PSTATE_PIB_MASTER_NONOFFLINE_ERR ); // pstate_pib_master_nonoffline_err + SET_RECOV_INTR(PSTATE_PIB_MASTER_OFFLINE_ERR ); // pstate_pib_master_offline_err + SET_RECOV_INTR(PSTATE_OCI_MASTER_TO_ERR ); // pstate_oci_master_to_err + SET_RECOV_INTR(PSTATE_INTERCHIP_UE_ERR ); // pstate_interchip_ue_err + SET_RECOV_INTR(PSTATE_INTERCHIP_ERRORFRAME_ERR ); // pstate_interchip_errorframe_err + SET_RECOV_INTR(PSTATE_MS_FSM_ERR ); // pstate_ms_fsm_err + SET_MALF_ALERT(MS_COMP_PARITY_ERR ); // ms_comp_parity_err + SET_MALF_ALERT(IDLE_PORESW_FATAL_ERR ); // idle_poresw_fatal_err + SET_MALF_ALERT(IDLE_PORESW_STATUS_RC_ERR ); // idle_poresw_status_rc_err + SET_MALF_ALERT(IDLE_PORESW_STATUS_VALUE_ERR ); // idle_poresw_status_value_err + SET_MALF_ALERT(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR ); // idle_poresw_write_while_inactive_err + SET_MALF_ALERT(IDLE_PORESW_TIMEOUT_ERR ); // idle_poresw_timeout_err + SET_FIR_MASKED(IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR ); // idle_oci_master_write_timeout_err + SET_MALF_ALERT(IDLE_INTERNAL_ERR ); // idle_internal_err + SET_MALF_ALERT(INT_COMP_PARITY_ERR ); // int_comp_parity_err + SET_MALF_ALERT(PMC_OCC_HEARTBEAT_TIMEOUT ); // pmc_occ_heartbeat_timeout + SET_FIR_MASKED(SPIVID_CRC_ERROR0 ); // spivid_crc_error0 + SET_FIR_MASKED(SPIVID_CRC_ERROR1 ); // spivid_crc_error1 + SET_FIR_MASKED(SPIVID_CRC_ERROR2 ); // spivid_crc_error2 + SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT ); // spivid_retry_timeout + SET_FIR_MASKED(SPIVID_FSM_ERR ); // spivid_fsm_err + SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY ); // spivid_majority_detected_a_minority + SET_FIR_MASKED(O2S_CRC_ERROR0 ); // o2s_crc_error0 + SET_FIR_MASKED(O2S_CRC_ERROR1 ); // o2s_crc_error1 + SET_FIR_MASKED(O2S_CRC_ERROR2 ); // o2s_crc_error2 + SET_FIR_MASKED(O2S_RETRY_TIMEOUT ); // o2s_retry_timeout + SET_FIR_MASKED(O2S_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2s_write_while_bridge_busy_err + SET_FIR_MASKED(O2S_FSM_ERR ); // o2s_fsm_err + SET_FIR_MASKED(O2S_MAJORITY_DETECTED_A_MINORITY ); // o2s_majority_detected_a_minority + SET_FIR_MASKED(O2P_WRITE_WHILE_BRIDGE_BUSY_ERR ); // o2p_write_while_bridge_busy_err + SET_FIR_MASKED(O2P_FSM_ERR ); // o2p_fsm_err + SET_FIR_MASKED(OCI_SLAVE_ERR ); // oci_slave_err + SET_MALF_ALERT(IF_COMP_PARITY_ERR ); // if_comp_parity_err // 37:46 spare_fir + SET_RECOV_ATTN(FIR_PARITY_ERR_DUP ); // fir_parity_err_dup + SET_RECOV_ATTN(FIR_PARITY_ERR ); // fir_parity_err + + if(e_rc){rc.setEcmdError(e_rc); return rc;} + + FAPI_INF(" action_0 => 0x%16llx ", action_0.getDoubleWord(0)); + FAPI_INF(" action_1 => 0x%16llx ", action_1.getDoubleWord(0)); + FAPI_INF(" mask => 0x%16llx ", mask.getDoubleWord(0)); + + + //#--****************************************************************************** + //#-- PMC_FIR_ACTION0 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_FIR_ACTION0_0x01010846, action_0 ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_FIR_ACTION0_0x01010846) failed."); return rc; + } + + //#--****************************************************************************** + //#-- PMC_FIR_ACTION1 + //#--****************************************************************************** + + rc = fapiPutScom(i_target, PMC_FIR_ACTION1_0x01010847, action_1 ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_FIR_ACTION1_0x01010847) failed."); return rc; + } + + + //--****************************************************************************** + //-- PMC_FIR_MASK (W0_OR_45) (WR_43) (WO_AND_44) + //--****************************************************************************** + rc = fapiPutScom(i_target, PMC_FIR_MASK_WR_0x01010843, mask ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_FIR_MASK_WR_0x01010843) failed."); return rc; + } + + + + + + + + + + + + return rc ; + + +} // Procedure + + +} //end extern C + + + + +// ---------------------------------------------------------------------- +// BACKUPS +// ---------------------------------------------------------------------- + +// #define RECOV_INTR 1, 0 +// #define RECOV_ATTN 0, 1 +// #define MALF_ALERT 1, 1 + + +// SET_FIR_ACTION( 1 ,1 ,0) ; +// SET_FIR_ACTION( 2, 0, 1) ; +// SET_FIR_ACTION( 3, 1, 1) ; SET_FIR_MASK(3, 1) ; + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H new file mode 100755 index 000000000..15032293b --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pm_pmc_firinit.H,v 1.2 2012/09/24 08:50:36 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_pm_pmc_firinit.H +// *! DESCRIPTION : Set the EX chiplet into Special Wake-up via one of the +// *! entity bits provided +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pm_pmc_firinit_FP_t) (const fapi::Target& ); + +extern "C" { + + +fapi::ReturnCode +p8_pm_pmc_firinit(const fapi::Target& i_target ); +//------------------------------------------------------------------------------ +// function: FAPI p8_pm_pmc_firinit HWP entry point +// operates on chips passed in i_target argument to perform +// desired settings of FIRS of PMC macro +// parameters: i_target => chip target + +// returns: FAPI_RC_SUCCESS if all specified operations complete successfully, +// else return code for failing operation +//------------------------------------------------------------------------------ + + +} // extern "C" + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C new file mode 100755 index 000000000..62432c68a --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -0,0 +1,1323 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pmc_init.C,v 1.6 2012/10/04 10:24:27 pchatnah Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Joe Procwriter Email: asmartpersion@xx.ibm.com +// *! +// *! General Description: +// *! +// *! The purpose of this procedure is to ...... +// *! +// *! High-level procedure flow: +// *! o Do thing 1 +// *! o Do thing 2 +// *! o Do thing 3 +// *! o Check if all went well +// *! o If so celebrate +// *! o Else write logs, set bad return code +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_pmc_init.H" + +//---------------------------------------------------------------------- +// eCMD Includes +//---------------------------------------------------------------------- +// #include <ecmdClientCapi.H> +// #include <ecmdUtils.H> +// #include <ecmdSharedUtils.H> +// #include <iostream> +// #include <fapiUtil.H> +//#include <sim_utils.inc> +//#include "myscoms.H" // Remove eventually + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <fapi.H> +#include <ecmdDataBufferBase.H> + +//#ifdef FAPIECMD +extern "C" { + // #endif + + + +using namespace fapi; + +//TODO RTC: 68461 - Refresh procedures to remove multiple definitions +//RTC 68461 CONST_UINT64_T( OCB_OCI_OIMR1_0x0006a014 , ULL(0x0006a014) ); +//RTC 68461 CONST_UINT64_T( OCB_OCI_OIMR0_0x0006a004 , ULL(0x0006a004) ); + //NST_UINT64_T( PMC_MODE_REG_0x00062000 , ULL(0x00062000) ); +//RTC 68461 CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); +//RTC 68461 CONST_UINT64_T( PMC_INTCHP_STATUS_REG_0x00062013 , ULL(0x00062013) ); + //CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// fapi::ReturnCode +// pmc_create_spivid_settings(const Target& l_pTarget) +// { +// fapi::ReturnCode rc; + + + + + +// return rc ; +// } + +//------------------------------------------------------------------------- + /// Locally computed variables to put into the feature attributes +//------------------------------------------------------------------------- + +fapi::ReturnCode +pmc_config_spivid_settings(const Target& l_pTarget) +{ + fapi::ReturnCode rc; + + uint32_t attr_pm_spivid_clock_divider; + uint32_t attr_pm_spivid_frequency = 10; + uint32_t attr_proc_nest_frequency = 2400; + + FAPI_INF("entering the config function"); + + rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL, attr_proc_nest_frequency); if (rc) return rc; + //TODO RTC: 68461 - refresh procedures - hacked target in the line below. + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency); if (rc) return rc; + + + + + // calculation of clock divider + attr_pm_spivid_clock_divider = (attr_proc_nest_frequency/(attr_pm_spivid_frequency*8)-1 ); + + + rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); if (rc) return rc; + + FAPI_INF("exiting the config function"); + return rc ; +} + + + +fapi::ReturnCode +pmc_reset_function(const Target& i_target) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + // ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + uint32_t count = 0 ; + bool is_stopped ; + bool is_spivid_stopped ; + bool is_not_ongoing ; + bool enable_pstate_voltage_changes ; + bool fw_pstate_mode = false; ////TODO RTC: 68461 - refresh procedures, and to init variable. + bool is_pstate_error_stopped ; + bool is_intchp_error_stopped; + bool is_MasterPMC; + bool enable_fw_pstate_mode; + + +//////////////////////////////////////////////////////////////////////////// +// 1. cRQ_TD_IntMaskRQ: Mask OCC interrupts in OIMR1 +// PMC_PSTATE_REQUEST, PMC_PROTOCOL_ONGOING, PMC_VOLTAGE_CHANGE_ONGOING, +// PMC_INTERCHIP_MSG_SEND_ONGOING, PMC_IDLE_ENTER, PMC_IDLE_EXIT, PMC_SYNC +//////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 1"); + + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + rc = fapiGetScom(i_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR1_0x0006a014) failed."); return rc; + } + + + e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(13); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(14); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(18); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(20); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(22); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + + + rc = fapiPutScom(i_target, OCB_OCI_OIMR1_0x0006a014 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR1_0x0006a014) failed."); return rc; + } + +//////////////////////////////////////////////////////////////////////////// +// 2. cRQ_TD_IntMaskER: Mask OCC interrupts in OIMR0 +// PMC_ERROR, PMC_MALF_ALERT, PMC_INTERCHIP_MSG_RECVD +//////////////////////////////////////////////////////////////////////////// + + + + FAPI_INF("Performing STEP 2"); + rc = fapiGetScom(i_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(OCB_OCI_OIMR0_0x0006a004) failed."); return rc; + } + + + e_rc = data.setBit(9); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(13); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(21); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + + + rc = fapiPutScom(i_target, OCB_OCI_OIMR0_0x0006a004 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(OCB_OCI_OIMR0_0x0006a004) failed."); return rc; + } + + +//////////////////////////////////////////////////////////////////////////// +// 3. cRQ_TD_DisableMPS: Write PMC_MODE_REG to halt things Which register bits should be written with what to make this below halts ? +// halt_pstate_master_fsm<-1 <-1 indicates to write the bit with the value 1 +// halt_idle_state_master_fsm<-1 <-1 indicates to write the bit with the value 1 +// Note: Other bits are left as setup so the configuration remains as things halt, and new +// requests are queued (just now processed now). +//////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 3"); + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); return rc; + } + + + e_rc = data.setBit(05); if(e_rc){rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(14); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + + + rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); return rc; + } + + is_MasterPMC = data.isBitSet(6) & data.isBitSet(7) ; + enable_pstate_voltage_changes = data.isBitSet(6) ; + enable_fw_pstate_mode = data.isBitSet(2) ; + + + + + + +//////////////////////////////////////////////////////////////////////////// +// 4. if enable_interchip_interface==1 +// cRQ_TD_HaltInterchip_On: Write PMC_INTCHP_COMMAND_REG.interchip_halt_msg_fsm<-1 Should we write the command register here ? That's why I specified the command register, PMC_INTCHP_COMMAND_REG. +// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG +// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG +// is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error +// is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? +// is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped +// If !is_stopped Then -->cRQ_TD_HaltInterchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) +// cRQ_TD_HaltInterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if where is this bit ? PMC_MODE_REG bit 15 as documented. + + +//////////////////////////////////////////////////////////////////////////// + + + FAPI_INF("Performing STEP 4"); + if (data.isBitSet(6)) + + { + + rc = fapiGetScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; + } + + e_rc = data.setBit(01); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + + rc = fapiPutScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; + } + + + + + + + for (count = 0 , is_stopped = 0 ; count <= 256 && is_stopped == 0; count++) + { +// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG +// is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error + + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; + } + + + is_pstate_error_stopped = data.isBitSet(0) | data.isBitSet(1) | data.isBitSet(5)| data.isBitSet(6) | data.isBitSet(11) ; + + +// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG +// is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? + + rc = fapiGetScom(i_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_INTCHP_STATUS_REG_0x00062013) failed."); return rc; + } + is_intchp_error_stopped = data.isBitSet(1) | data.isBitSet(7) | (~( data.isBitClear(16,4) && is_MasterPMC)) ; + +// is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped ; + is_stopped = data.isBitClear(0) || is_pstate_error_stopped || is_intchp_error_stopped; + + +// If !is_stopped Then -->cRQ_TD_HaltInterchip_Wait1 (Wait limit is parm TD_Interchip_HaltWait_max=260) + + + } // end_for + if (count > 256) + { + FAPI_ERR("Timed out in polling interchip ongoing ... "); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + return rc; + + } + + +// cRQ_TD_HaltInterchipIf: PMC_MODE_REG.interchip_halt_if<-1 interchip_halt_if where is this bit ? PMC_MODE_REG bit 15 as documented. + + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); return rc; + } + + e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_MODE_REG_0x00062000) failed."); return rc; + } + + + + + } // end if + + + + +//////////////////////////////////////////////////////////////////////////// +// 5. if enable_pstate_voltage_changes==1 +// cRQ_TD_HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 +// cRQ_TD_Spivid_HaltWait: Read PMC_SPIV_STATUS_REG +// is_spivid_error = spivid_retry_timeout || spivid_fsm_err +// if spivid_ongoing && !is_spivid_error Then -->cRQ_TD_Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) +// else -->cRQ_TD_MPS_HaltWait +//////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP 5"); + + if (enable_pstate_voltage_changes==1) + { +// cRQ_TD_HaltSpivid: PMC_SPIV_COMMAND_REG.spivid_halt_fsm<-1 + rc = fapiGetScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; + } + + e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } + + rc = fapiPutScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; + } + + + +// cRQ_TD_Spivid_HaltWait: Read PMC_SPIV_STATUS_REG + +// if spivid_ongoing && !is_spivid_error Then -->cRQ_TD_Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) + + for (count = 0 , is_spivid_stopped=0; count <= 100 && is_spivid_stopped==0 ; count++) + { + + rc = fapiGetScom(i_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); return rc; + } + is_spivid_stopped = data.isBitClear(0) | data.isBitSet(1) | data.isBitSet(2) | data.isBitSet(3) | data.isBitSet(4) ; + + } // end for + + + + if (count > 100) + { + FAPI_ERR("Timed out in polling spiv ongoing ... "); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + return rc; + + } + + } // end if + + +//////////////////////////////////////////////////////////////////////////// +// 6. cRQ_TD_MPS_HaltWait: Read PMC_STATUS_REG +// +// if (fw_pstate_mode) +// is_not_ongoing = (enable_pstate_voltage_changes==0 || volt_chg_ongoing==0) && (brd_cst_ongoing == 0) +// else +// is_not_ongoing = (enable_pstate_voltage_changes==0 || gpsa_chg_ongoing==0) + +// is_pstate_error = (pstate_interchip_error || pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error) +// is_stopped = is_not_ongoing || is_pstate_error + +// if (!is_stopped) then -->cRQ_TD_MPS_HaltWait (Wait limit) + +//////////////////////////////////////////////////////////////////////////// + + FAPI_INF("Performing STEP "); + + + for (count = 0 , is_stopped = 0 ; count <= 256 && is_stopped == 0 ; count++) + { + + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; + } + + + if (fw_pstate_mode) + { + + is_not_ongoing = (enable_pstate_voltage_changes==0 || data.isBitClear(8)) && data.isBitClear(9); + + } + else + { + is_not_ongoing = (enable_pstate_voltage_changes==0 || data.isBitClear(7)); + } + + is_stopped = (data.isBitSet(11) | data.isBitSet(12) | data.isBitSet(1) | data.isBitSet(5) | data.isBitSet(6)) | is_not_ongoing ; + + } // end for + + if (count > 100) + { + FAPI_ERR("Timed out in polling voltage change ongoing ... "); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); + return rc; + + } + return rc; +} +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + + +// function: p8_pmc_init +// parameters: target , mode = (PM_INIT , PM_CONFIG, PM_RESET) +// returns: ECMD_SUCCESS if something good happens, +// BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_pmc_init(const Target& i_target, uint32_t mode) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + uint32_t e_rc = 0; + + FAPI_INF(""); + FAPI_INF("Executing p8_pmc_init ...."); + + + // ------------------------------------------------ + // CONFIG mode + // ------------------------------------------------ + if (mode == PM_CONFIG) + { + + FAPI_INF("PMC configuration..."); rc=pmc_config_spivid_settings(i_target); + + } + + // ------------------------------------------------ + // INIT mode + // ------------------------------------------------ + + else if (mode == PM_INIT) { + + uint8_t attr_pm_spivid_frame_size; + uint8_t attr_pm_spivid_in_delay_frame1; + uint8_t attr_pm_spivid_in_delay_frame2; + uint8_t attr_pm_spivid_clock_polarity; + uint8_t attr_pm_spivid_clock_phase; + uint32_t attr_pm_spivid_clock_divider; + uint8_t attr_pm_spivid_port_enable = 7; + // uint32_t attr_pm_spivid_interframe_delay_write_status; + uint32_t attr_pm_spivid_interframe_delay_write_status_value; +// uint32_t attr_pm_spivid_inter_retry_delay_value; +// uint32_t attr_pm_spivid_inter_retry_delay; + uint8_t attr_pm_spivid_crc_gen_enable; + uint8_t attr_pm_spivid_crc_check_enable; + uint8_t attr_pm_spivid_majority_vote_enable; + uint8_t attr_pm_spivid_max_retries; + uint8_t attr_pm_spivid_crc_polynomial_enables; + + + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &i_target, attr_pm_spivid_frame_size); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &i_target, attr_pm_spivid_in_delay_frame1); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &i_target, attr_pm_spivid_in_delay_frame2); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &i_target, attr_pm_spivid_clock_polarity); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &i_target, attr_pm_spivid_clock_phase); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} + + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &i_target, attr_pm_spivid_interframe_delay_write_status); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &i_target, attr_pm_spivid_interframe_delay_write_status_value); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} + + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &i_target, attr_pm_spivid_inter_retry_delay_value); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &i_target, attr_pm_spivid_inter_retry_delay); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &i_target, attr_pm_spivid_crc_gen_enable); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &i_target, attr_pm_spivid_crc_check_enable); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &i_target, attr_pm_spivid_majority_vote_enable); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &i_target, attr_pm_spivid_max_retries); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &i_target, attr_pm_spivid_crc_polynomial_enables); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} + + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &i_target, attr_pm_spivid_clock_divider); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} + + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &i_target, attr_pm_spivid_port_enable); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} + + + //---------------------------------------------------------- + + + + + + + + + + + + // rc=pmc_create_spivid_settings(i_target); above lines replaced this functions + + FAPI_INF("PMC initialization..."); + + uint8_t o2s_frame_size = attr_pm_spivid_frame_size; + uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; + uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; + uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; + uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; + uint8_t o2s_port_enable = attr_pm_spivid_port_enable; + uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; + uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; + uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; + uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; + uint8_t o2s_max_retries = attr_pm_spivid_max_retries; + uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; + uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; + //spivid_freq = attr_pm_spivid_frequency; + uint8_t o2s_in_count2 = 0 ; + uint8_t o2s_out_count2 = 0 ; + uint8_t o2s_bridge_enable = 0x1 ; + uint8_t o2s_nr_of_frames = 1 ; //(uint8_t) args.front(); args.pop_front(); // for pmc o2s operations it is usually 1 + uint8_t o2s_in_count1 = 0 ; + uint8_t o2s_out_count1 = 32 ; + uint32_t dummy = 0 ; + + + uint8_t one=1; + + + + + + // Here to bypass feature attribute passing until these as moved into proc.pm.pmc.scom.initfile + +// o2s_frame_size = 0x10 ; +// o2s_clk_pol = 0; +// o2s_clk_pha = 0; +// o2s_clk_divider= 0x1D; +// o2s_inter_frame_delay = 0x0; +// nest_freq = 600; +// spivid_freq = 10; +// o2s_in_count1=0; +// o2s_out_count1=0; +// o2s_in_delay1=0; +// o2s_in_count2=0; +// o2s_out_count2=0; +// o2s_in_delay2=0; +// o2s_wdata = 0x11223344; + + + + // ****************************************************************** + // - set PMC_o2s_CTRL_REG0A (24b) + // ****************************************************************** + + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0A) failed."); return rc; + } + + e_rc = data.insertFromRight( o2s_frame_size ,0,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_in_count1 ,6,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_out_count1 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_in_delay1 ,18,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_0A Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + e_rc = data.extractToRight(&dummy,0,6); + FAPI_INF(" frame size => %x ", dummy); + e_rc |= data.extractToRight(&dummy,6,6); + FAPI_INF(" o2s_out_count1 => %x ", dummy); + e_rc |= data.extractToRight(&dummy,12,6); + FAPI_INF(" o2s_in_delay1 => %x ", dummy); + e_rc |= data.extractToRight(&dummy,18,6); + FAPI_INF(" o2s_in_count1 => %x ", dummy); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + if(e_rc){rc.setEcmdError(e_rc); return rc;} + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0A_0x00062050) failed."); return rc; + } + + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG0B (24b) + // ****************************************************************** + + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed."); return rc; + } + + e_rc = data.insertFromRight(o2s_out_count2,00,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight(o2s_in_delay2 ,06,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight(o2s_in_count2 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_0B Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" o2s_out_count2 => %d ", o2s_out_count2); + FAPI_INF(" o2s_in_delay2 => %d ", o2s_in_delay2 ); + FAPI_INF(" o2s_in_count2 => %d ", o2s_in_count2 ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0B_0x00062051) failed."); return rc; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG1 + // ****************************************************************** + + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); return rc; + } + + o2s_nr_of_frames--; + e_rc = data.insertFromRight( o2s_bridge_enable ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_clk_pol ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_clk_pha ,3,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_clk_divider,4,10); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_nr_of_frames ,17,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_port_enable ,18,3); if(e_rc){rc.setEcmdError(e_rc); return rc;} + o2s_nr_of_frames++; + + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_1 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" o2s_bridge_enable => %d ", o2s_bridge_enable ); + FAPI_INF(" o2s_clk_pol => %d ", o2s_clk_pol ); + FAPI_INF(" o2s_clk_pha => %d ", o2s_clk_pha ); + FAPI_INF(" o2s_clk_divider => %d ", o2s_clk_divider); + FAPI_INF(" o2s_nr_of_frames => %d ", o2s_nr_of_frames); + FAPI_INF(" o2s_port_enable => %d ", o2s_port_enable); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG1_0x00062052, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); return rc; + } + + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG2 + // ****************************************************************** + + + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG2) failed."); return rc; + } + + e_rc = data.insertFromRight( o2s_inter_frame_delay ,0,17); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_2 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" o2s_inter_frame_delay => %d ", o2s_inter_frame_delay ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG2_0x00062053, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG2_0x00062053) failed."); return rc; + } + + // ****************************************************************** + // - set PMC_O2S_CTRL_REG4 + // ****************************************************************** + + rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG4) failed."); return rc; + } + + e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_crc_check_en ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_majority_vote_en ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_max_retries ,3,5); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_crc_polynomial_enables,8,8); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_4 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" o2s_crc_gen_en => %d ", o2s_crc_gen_en ); + FAPI_INF(" o2s_crc_check_en => %d ", o2s_crc_check_en ); + FAPI_INF(" o2s_majority_vote_en => %d ", o2s_majority_vote_en ); + FAPI_INF(" o2s_max_retries => %d ", o2s_max_retries ); + FAPI_INF(" o2s_crc_polynomial_enab => %d ", o2s_crc_polynomial_enables ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + rc = fapiPutScom(i_target, PMC_O2S_CTRL_REG4_0x00062055, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG4_0x00062055) failed."); return rc; + } + +// ****************************************************************** +// Program crc polynomials +// ****************************************************************** + + rc = fapiGetScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); + if (rc) { + FAPI_ERR("fapiGetScom(PMC_SPIV_CTRL_REG4) failed."); return rc; + } + + + e_rc = data.insertFromRight( o2s_crc_gen_en ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_crc_check_en ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_majority_vote_en ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_max_retries ,3,5); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight( o2s_crc_polynomial_enables,8,8); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" PMC O2S CTRL_REG_3Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" spiv_crc_gen_en => %d ", o2s_crc_gen_en ); + FAPI_INF(" spiv_crc_check_en => %d ", o2s_crc_check_en ); + FAPI_INF(" spiv_majority_vote_en => %d ", o2s_majority_vote_en ); + FAPI_INF(" spiv_max_retries => %d ", o2s_max_retries ); + FAPI_INF(" spiv_crc_polynomial_enab => %d ", o2s_crc_polynomial_enables ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + rc = fapiPutScom(i_target, PMC_SPIV_CTRL_REG4_0x00062045, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG4_0x00062045) failed."); return rc; + } + + + // ****************************************************************** + // - write PMC_O2S_command_reg to clear any latent errors + // ****************************************************************** + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.insertFromRight(one ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // halt retries + e_rc = data.insertFromRight(one ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // reset sticky errors + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" clearing errors "); + // FAPI_INF(" -----------------------------------------------------"); + + rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; + } + + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + + rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); + if (rc) { + FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; + } + FAPI_INF ("I m done with the init " ); + + } + + /// ------------------------------- + /// Reset: perform reset of PMC + else if (mode == PM_RESET) + { + + FAPI_INF("PMC reset..."); + + // Reset PMC. However, the bit used means the entire PMC must be reconfigured! + + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} + e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } // RESET_ALL_PMC_REGISTERS + + rc=fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data); if(rc) return rc; + // This function is not yet verified + rc=pmc_reset_function(i_target); + + + } + + + /// ------------------------------- + /// Unsupported Mode + + else { + FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); + uint32_t & MODE = mode; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); + } + + return rc; + +} + + + + //#ifdef FAPIECMD +} //end extern C +// #endif + + + + + + + + + + + +// BackUPS + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + + +// PIB Space Addresses + + +/* + CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00072041 , ULL(0x00072041) ); + CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00072042 , ULL(0x00072042) ); + CONST_UINT64_T( PMC_SPIV_CTRL_REG2_0x00072043 , ULL(0x00072043) ); + CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00072044 , ULL(0x00072044) ); + CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00072045 , ULL(0x00072045) ); + CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00072046 , ULL(0x00072046) ); + CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00072047 , ULL(0x00072047) ); + + + CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 ,ULL(0x00062051) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 ,ULL(0x00062052) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 ,ULL(0x00062053) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 ,ULL(0x00062055) ); + CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 ,ULL(0x00062056) ); + CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 ,ULL(0x00062057) ); + CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 ,ULL(0x00062058) ); + CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 ,ULL(0x00062059) ); + +// OCI Space Addresses +CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); +*/ + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +// std::string PROCEDURE = "p8_pmc_init"; // procedure name + //std::string REVISION = "$Revision: 1.6 $"; // procedure CVS revision + +//ReturnCode BAD_RETURN_CODE = 0x12000001; // procedure return code on fail, not used by ECMD +//uint32_t SIM_CYCLE_POLL_DELAY = 200000; // simulation cycle delay between status register polls +//bool VERBOSE = true; // enable verbose mode debug comments +//uint32_t MAX_POLL_ATTEMPTS = 5; // maximum number of status poll attempts to make before giving up + + + + // Global Variables + /// From generated pm_attributes_plat.H + +/* + uint8_t attr_pm_pstate_stepsize; + uint8_t attr_pm_external_vrm_stepdelay_range; + uint8_t attr_pm_external_vrm_stepdelay_value; + uint8_t attr_pm_pmc_hangpulse_divider; + uint8_t attr_pm_pvsafe_pstate; + uint8_t attr_pm_pstate_undervolting_minimum; + uint8_t attr_pm_pstate_undervolting_maximum; +*/ + + + /// From generated pm_attributes_plat.H + + + + + + + + + +/* + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, l_pTarget, attr_pm_spivid_frame_size); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, l_pTarget, attr_pm_spivid_in_delay_frame1); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, l_pTarget, attr_pm_spivid_in_delay_frame2); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_FRAME_DELAY, l_pTarget, attr_pm_spivid_inter_frame_delay); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_FRAME_DELAY_WRITE_STATUS, l_pTarget, attr_pm_spivid_inter_frame_delay_write_status); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, l_pTarget, attr_pm_spivid_inter_retry_delay); if (rc) return rc; +*/ + + + // Here to test feature attribute passing util these as moved into proc.pm.pmc.scom.initfile + /* + rc = FAPI_ATTR_GET(ATTR_SPIVID_CLOCK_POLARITY, NULL, o2s_clk_pol); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_CLOCK_PHASE, NULL, o2s_clk_pha); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_PORT_ENABLE, NULL, o2s_port_enable); if (rc) return rc; + rc = FAPI_ATTR_GET(SPIVID_INTER_FRAME_DELAY_WRITE_STATUS, NULL, o2s_inter_frame_delay); if (rc) return rc; + + + // rc = FAPI_ATTR_GET(SPIVID_INTER_RETRY_DELAY, NULL, l_uint64_1); if (rc) return rc; + + rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_GEN_ENABLE, NULL, o2s_crc_gen_en); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_CHECK_ENABLE, NULL, o2s_crc_check_en); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_MAJORITY_VOTE_ENABLE, NULL, o2s_majority_vote_en); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_MAX_RETRIES, NULL, o2s_max_retries); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_CRC_POLYNOMIAL_ENABLES, NULL, o2s_crc_polynomial_enables); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_IN_DELAY_FRAME1, NULL, o2s_in_delay1); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPIVID_IN_DELAY_FRAME2, NULL, o2s_in_delay2); if (rc) return rc; + */ + + + + +// uint8_t attr_pm_spivid_frame_size_set = 32; +// uint8_t attr_pm_spivid_in_delay_frame1_set = 0; +// uint8_t attr_pm_spivid_in_delay_frame2_set = 0 ; +// uint8_t attr_pm_spivid_clock_polarity_set = 0; +// uint8_t attr_pm_spivid_clock_phase_set = 0 ; +// // uint32_t attr_pm_spivid_clock_divider_set = 0x1D ; +// // uint8_t attr_pm_spivid_port_enable_set = 3 ; +// uint32_t attr_pm_spivid_interframe_delay_write_status_set = 0 ; +// uint32_t attr_pm_spivid_interframe_delay_write_status_value_set = 12; +// uint32_t attr_pm_spivid_inter_retry_delay_value_set = 20 ; +// uint32_t attr_pm_spivid_inter_retry_delay_set = 1; +// uint8_t attr_pm_spivid_crc_gen_enable_set = 1 ; +// uint8_t attr_pm_spivid_crc_check_enable_set = 1 ; +// uint8_t attr_pm_spivid_majority_vote_enable_set = 1; +// uint8_t attr_pm_spivid_max_retries_set = 5 ; +// uint8_t attr_pm_spivid_crc_polynomial_enables_set = 0xD5; +// // uint32_t attr_pm_spivid_frequency_set = 20; +// // uint32_t attr_p8_nest_frequency_set = 3000; + + + + + +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size_set); +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } + + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } + + +// // rc = FAPI_ATTR_SET(ATTR_FREQ_PB, &l_pTarget, attr_p8_nest_frequency_set); if (rc) return rc; +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency_set); if (rc) return rc; + + +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider_set); +// // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } + + +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable_set); +// // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } + + + + + + + + + + + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_STEPSIZE, &l_pTarget, attr_pm_pstate_stepsize_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_STEPSIZE with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE, &l_pTarget, attr_pm_external_vrm_stepdelay_range_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE, &l_pTarget, attr_pm_external_vrm_stepdelay_value_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PMC_HANGPULSE_DIVIDER, &l_pTarget, attr_pm_pmc_hangpulse_divider_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PMC_HANGPULSE_DIVIDER with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PVSAFE_PSTATE, &l_pTarget, attr_pm_pvsafe_pstate_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PVSAFE_PSTATE with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &l_pTarget, attr_pm_pstate_undervolting_minimum_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)rc); break; } + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &l_pTarget, attr_pm_pstate_undervolting_maximum_set); + /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)rc); break; } + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_OCC_HEARTBEAT_TIME, &l_pTarget, attr_pm_occ_heartbeat_time_set); +// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_OCC_HEARTBEAT_TIME with rc = 0x%x", (uint32_t)rc); break; } + +// ------------------------------------------------------------------------------------------------------------------------------------------------ + +// Enable the get functions + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size); +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} + + +// //---------------------------------------------------------- + + + + + + + //-------------------------------------------------------------------- + //- >>> SCOM.INITFILE elements + //-------------------------------------------------------------------- diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H new file mode 100755 index 000000000..20a1b14dc --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H @@ -0,0 +1,76 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Greg Stilll Email: stillgs@us.ibm.com +// *! +// *! General Description: +// *! This procedure is intializes / resets / configures the O2S access bridge +// *! Target : Processor chip +//------------------------------------------------------------------------------ +// + +/// \param[in] i_target Chip target +/// \param[in] mode + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pmc_init_FP_t) (const fapi::Target&, uint32_t mode); + +extern "C" { + +// enum p8_PM_FLOW_MODE { +// PM_CONFIG = 0x1, +// PM_RESET = 0x2, +// PM_INIT = 0x3, +// PM_SETUP = 0x4, +// PM_SETUP_PIB = 0x5, +// PM_SETUP_ALL = 0x6 +// }; + + +fapi::ReturnCode p8_pmc_init(const fapi::Target& i_target, uint32_t mode); + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C new file mode 100755 index 000000000..c072347ee --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C @@ -0,0 +1,316 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_poregpe_init.C,v 1.2 2012/10/10 20:23:05 stillgs Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poregpe_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com +// *! +/// \file p8_poregpe_init.C +/// \brief Configure or reset the targeted GPE0 and/or GPE1 +/// +/// +/// \todo add to required proc ENUM requests +/// +/// High-level procedure flow: +/// \verbatim +/// +/// Check for valid parameters +/// if PM_CONFIG { +/// Do nothing (done by OCC programs) +/// } else if PM_RESET { +/// for each GPE, +/// set and then reset bit 0 in the GPEx_RESET_REGISTER +/// +/// } +/// +/// Procedure Prereq: +/// - System clocks are running +/// \endverbatim +/// +//------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_poregpe_init.H" + +#ifdef FAPIECMD +extern "C" { +#endif + + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + +fapi::ReturnCode poregpe_reset(const Target& i_target, const uint32_t engine); + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + + +/// \param[in] i_target Chip target +/// \param[in] mode Control mode for the procedure +/// (PM_CONFIG, PM_INIT, PM_RESET) +/// \param[in] engine Targeted engine: GPE0, GPE1, GPEALL + +/// \retval FAPI_RC_SUCCESS +/// \retval ERROR defined in xml +fapi::ReturnCode +p8_poregpe_init(const Target& i_target, uint32_t mode, uint32_t engine) +{ + fapi::ReturnCode l_rc; + + do + { + FAPI_INF("Executing p8_poregpe_init in mode %x for engine %x....\n", + mode, engine); + + if (!(engine == GPE0 || engine == GPE1 || engine == GPEALL) ) + { + + FAPI_ERR("Unknown engine passed to p8_poregpe_init. Engine %x ....\n", + engine); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE_BAD_ENGINE); + break; + } + + /// ------------------------------- + /// Configuration: perform translation of any Platform Attributes into + /// Feature Attributes that are applied during Initalization + if (mode == PM_CONFIG) + { + FAPI_INF("PORE-GPE configuration...\n"); + FAPI_INF("---> None is defined...done by OCC firmware\n"); + } + + /// ------------------------------- + /// Initialization: perform order or dynamic operations to initialize + /// the GPEs using necessary Platform or Feature attributes. + else if (mode == PM_INIT) + { + FAPI_INF("PORE-GPE initialization...\n"); + FAPI_INF("---> None is defined...done by OCC firmware\n"); + } + + /// ------------------------------- + /// Reset: perform reset of GPE engines so that they can reconfigured + /// and reinitialized + else if (mode == PM_RESET) + { + // GPE0 + if (engine == GPE0 || engine == GPEALL) + { + l_rc = poregpe_reset(i_target, GPE0); + } + + if (engine == GPE1 || engine == GPEALL) + { + l_rc = poregpe_reset(i_target, GPE1); + } + + } + + /// ------------------------------- + /// Unsupported Mode + + else + { + FAPI_ERR("Unknown mode passed to p8_poregpe_init. Mode %x ....\n", mode); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE_CODE_BAD_MODE); + } + } while(0); + + return l_rc; +} + +//------------------------------------------------------------------------------ +// PORE GPE Reset Function +//------------------------------------------------------------------------------ +fapi::ReturnCode +poregpe_reset(const Target& i_target, const uint32_t engine) +{ + fapi::ReturnCode l_rc; + uint32_t e_rc = 0; + ecmdDataBufferBase data(64); + ecmdDataBufferBase polldata(64); + const uint32_t max_polls = 8; + uint32_t poll_count; + bool wait_state_detected; + bool poll_loop_error = false; + uint64_t control_reg; + uint64_t reset_reg; + uint64_t status_reg; + + + + FAPI_INF("PORE-GPE reset...Engine: %x\n", engine); + + do + { + // Set the address offset values based on which engine is being operated + // on + if (engine == GPE0) + { + control_reg = PORE_GPE0_CONTROL_0x00060001; + reset_reg = PORE_GPE0_RESET_0x00060002; + status_reg = PORE_GPE0_STATUS_0x00060000; + } + else if (engine == GPE1) + { + control_reg = PORE_GPE1_CONTROL_0x00060021; + reset_reg = PORE_GPE1_RESET_0x00060022; + status_reg = PORE_GPE1_STATUS_0x00060020; + } + else + { + FAPI_ERR("Invalid engine parm passed to poregpe_reset"); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE_BAD_ENGINE); + break; + } + + // Reset the GPEsusing the Reset Register bits 0 and 1. + // Note: This resets ALL registers (including debug registers) with + // the exception of Error Mask + + // set PORE run bit to stop + l_rc=fapiGetScom(i_target, control_reg, data); + if(!l_rc.ok()) + { + FAPI_ERR("Scom error reading PORE_GPE%x_CONTROL_%08llx", engine, control_reg); + break; + } + + e_rc=data.setBit(0); + if (e_rc) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); + l_rc.setEcmdError(e_rc); + break; + } + + l_rc=fapiPutScom(i_target, control_reg, data); + if(!l_rc.ok()) + { + FAPI_ERR("Scom error writing PORE_GPE%x_CONTROL_%08llx", engine, control_reg); + break; + } + + // Reset PORE (state machines and PIBMS_DBG registers) and PIB2OCI + // interface write Reset_Register(0:1) with 0b11 to trigger the reset. + // Check that these are cleared to 0 to validate the reset occured. + e_rc |= data.flushTo0(); + e_rc |= data.setBit(0, 2); + if (e_rc) + { + FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); + l_rc.setEcmdError(e_rc); + break; + } + + FAPI_DBG("PORE-GPE%x Reset value: 0x%16llX", engine, data.getDoubleWord(0)); + + l_rc=fapiPutScom(i_target, reset_reg, data); + if(!l_rc.ok()) + { + FAPI_ERR("Scom error writing PORE_GPE%x_CONTROL", engine); + break; + } + + // poll until PORE has returned to WAIT state 3:6=0b0001 + wait_state_detected = false; + for (poll_count=0; poll_count<max_polls; poll_count++) + { + l_rc=fapiGetScom(i_target, status_reg, polldata); + if(l_rc) + { + FAPI_ERR("Scom error reading PORE_GPE%x_STATUS", engine); + poll_loop_error = true; + break; + } + + if(polldata.isBitClear(3, 3) && polldata.isBitSet(6)) + { + wait_state_detected = true; + break; + } + else + { + fapiDelay(1000, 10); + } + } + // Break if a FAPI error occured in the polling loop + if (poll_loop_error) + { + break; + } + + if(!wait_state_detected) + { + FAPI_ERR("GPE%x reset failed \n", engine); + FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_GPE0_RESET_TIMEOUT); + } + + } while(0); + + return l_rc; +} + +#ifdef FAPIECMD +} //end extern C +#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.H new file mode 100755 index 000000000..374c9f9e6 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.H @@ -0,0 +1,105 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_poregpe_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_poregpe_init.H,v 1.1 2012/08/23 04:58:56 stillgs Exp $ +// $Source: /afs/awd.austin.ibm.com/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poregpe_init.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_poregpe_init.H +// *! DESCRIPTION : Initialize the PORE GPE Engines in the OCC +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Jim Yacynych Email: jimyac@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _P8_POREGPE_H_ +#define _P8_POREGPE_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_poregpe_init_FP_t) (const fapi::Target&, uint32_t, uint32_t); + +extern "C" { + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +#ifndef _P8_POREGPE_ENGINES +#define _P8_POREGPE_ENGINES +enum P8_POREGPE_ENGINES { + GPE0 = 0x0, + GPE1 = 0x1, + GPEALL = 0XF + }; +#endif // _P8_POREGPE_ENGINES + + +//------------------------------------------------------------------------------ +// Parameter structure definitions +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \param[in] i_target Chip target +/// \param[in] mode Control mode for the procedure (PM_CONFIG, PM_RESET) +/// \param[in] engine Targeted engine: GPE0, GPE1, GPEALL + +/// \retval ECMD_SUCCESS if something good happens, +/// \retval BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_poregpe_init(const fapi::Target& i_target, uint32_t mode, uint32_t engine); + + +} // extern "C" + +#endif // _P8_POREGPE_H_ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C new file mode 100755 index 000000000..877d1bd2d --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C @@ -0,0 +1,984 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// $Id: p8_pss_init.C,v 1.2 2012/08/24 10:18:50 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pss_init.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : p8_pss_init.C +// *! DESCRIPTION : Initializes P2S and HWC logic +// *! OWNER NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! BACKUP NAME : Email: +// #! ADDITIONAL COMMENTS : +// +// +///Procedure Summary: +//-------------------- +/// One procedure to initialize both P2S and HWC SPIPSS registers to + +/// second Procedure is to access APSS or DPSS through P2S Bridge +/// Third procedure is to access APSS or DPSS through HWC (hardware control) +// +// *! High-level procedure flow: +//---------------------------------- +/// *! o INIT PROCEDURE(frame_size,cpol,cpha) +/// *! - set SPIPSS_ADC_CTRL_REG0(24b) +/// *! hwctrl_frame_size = 16 +/// *! - set SPIPSS_ADC_CTRL_REG1 +/// *! hwctrl_fsm_enable = disable +/// *! hwctrl_device = APSS +/// *! hwctrl_cpol = 0 (set idle state = deasserted) +/// *! hwctrl_cpha = 0 (set 1st edge = capture 2nd edge = change) +/// *! hwctrl_clock_divider = set to 10Mhz(0x1D) +/// *! hwctrl_nr_of_frames (4b) = 16 (for auto 2 mode) +/// *! - set SPIPSS_ADC_CTRL_REG2 +/// *! hwctrl_interframe_delay = 0x0 +/// *! - clear SPIPSS_ADC_WDATA_REG + +/// *! - set SPIPSS_P2S_CTRL_REG0 (24b) +/// *! p2s_frame_size = 16 +/// *! - set SPIPSS_P2S_CTRL_REG1 +/// *! p2s_bridge_enable = disable +/// *! p2s_device = DPSS +/// *! p2s_cpol = 0 +/// *! p2s_cpha = 0 +/// *! p2s_clock_divider = set to 10Mhz +/// *! p2s_nr_of_frames (1b) = 0 (means 1 frame operation) +/// *! - set SPIPSS_P2S_CTRL_REG2 +/// *! p2s_interframe_delay = 0x0 +/// *! - clear SPIPSS_P2S_WDATA_REG +/// +/// +/// *! +/// *! Procedure Prereq: +/// *! o System clocks are running +/// *! +///------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include "p8_pm.H" +#include "p8_scom_addresses.H" + +// #ifdef FAPIECMD + extern "C" { +// #endif + + + using namespace fapi; + + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + + + + + + + + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +// // Transform Platform Attribute for SPI PSS to Feature Attributes +// fapi::ReturnCode +// pss_create_spi_settings(const Target& l_pTarget) +// { +// fapi::ReturnCode rc; + + + + + + + + + + + +// return rc ; +// } + + + + + +fapi::ReturnCode +pss_config_spi_settings(const Target& l_pTarget) +{ + fapi::ReturnCode rc; + + uint32_t attr_proc_pss_init_nest_frequency=2400; + uint32_t attr_pm_pss_init_spipss_frequency=10; + uint8_t attr_pm_spipss_clock_divider ; + + + + + + + + + rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL , attr_proc_pss_init_nest_frequency); if (rc) return rc; + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_FREQUENCY, &l_pTarget,attr_pm_pss_init_spipss_frequency); if (rc) return rc ; + + + + // calculation of clock divider + attr_pm_spipss_clock_divider = ((attr_proc_pss_init_nest_frequency/attr_pm_pss_init_spipss_frequency)/8 )-1 ; + // printf ("clk_dive = %d ",attr_pm_spipss_clock_divider); + + rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_CLOCK_DIVIDER, &l_pTarget, attr_pm_spipss_clock_divider); if (rc) return rc; + + + return rc; +} + +// function: xxx +// parameters: none +// returns: ECMD_SUCCESS if something good happens, +// BAD_RETURN_CODE otherwise + +fapi::ReturnCode +p8_pss_init(Target &i_target, uint32_t mode) +{ + fapi::ReturnCode rc; + + uint32_t attr_proc_pss_init_nest_frequency=2400; + // uint32_t attr_pm_pss_init_spipss_frequency=10; + uint8_t attr_pm_spipss_clock_divider ; + + + uint8_t attr_pm_apss_chip_select=1 ; + uint8_t attr_pm_spipss_frame_size ; + // uint8_t attr_pm_spipss_out_count ; + // uint8_t attr_pm_spipss_in_delay ; + // uint8_t attr_pm_spipss_in_count ; + uint8_t attr_pm_spipss_clock_polarity ; + uint8_t attr_pm_spipss_clock_phase ; + + uint32_t attr_pm_spipss_inter_frame_delay ; + // attr_pm_spipss_inter_frame_delay_setting ; + uint32_t e_rc = 0; + uint32_t pollcount=0; + uint32_t max_polls = 255; + + + + + // size_t i; + + //i = args.size(); + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + /// ------------------------------- + /// Configuration: perform translation of any Platform Attributes into Feature Attributes + /// that are applied during Initalization + if (mode == PM_CONFIG) + { + + FAPI_INF("PSS configuration.."); + + rc=pss_config_spi_settings(i_target); + + } + + /// ------------------------------- + /// Initialization: perform order or dynamic operations to initialize + /// the PMC using necessary Platform or Feature attributes. + else if (mode == PM_INIT) + { + + + FAPI_INF("PSS initialisation..."); + // rc=pss_create_spi_settings(i_target); + + +// rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_OUT_COUNT, &i_target, attr_pm_spipss_out_count); if (rc) return rc; +// rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_IN_COUNT, &i_target, attr_pm_spipss_in_count); if (rc) return rc; + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_FRAME_SIZE, &i_target, attr_pm_spipss_frame_size); + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_frame_size = 0x%x", attr_pm_spipss_frame_size );} + + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_IN_DELAY, &i_target, attr_pm_spipss_in_delay); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_IN_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spipss_in_delay_frame1 = 0x%x", attr_pm_spipss_in_delay);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_CLOCK_POLARITY, &i_target, attr_pm_spipss_clock_polarity); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_clock_polarity = 0x%x", attr_pm_spipss_clock_polarity);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_CLOCK_PHASE, &i_target, attr_pm_spipss_clock_phase); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_clock_phase = 0x%x", attr_pm_spipss_clock_phase);} + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_INTER_FRAME_DELAY, &i_target, attr_pm_spipss_inter_frame_delay); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_INTER_FRAME_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_interframe_delay = 0x%x", attr_pm_spipss_inter_frame_delay);} + + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_APSS_CHIP_SELECT, &i_target, attr_pm_apss_chip_select); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_APSS_CHIP_SELECT with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_apss_chip_select = 0x%x", attr_pm_apss_chip_select);} + + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &i_target, attr_pm_spipss_interframe_delay_write_status_value); + +// if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } +// else { FAPI_INF (" value read from the attribute attr_pm_spipss_interframe_delay_write_status_value = 0x%x", attr_pm_spipss_interframe_delay_write_status_value);} + + + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIPSS_CLOCK_DIVIDER, &i_target, attr_pm_spipss_clock_divider); + + if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIPSS_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } + else { FAPI_INF (" value read from the attribute attr_pm_spipss_clock_divider = 0x%x", attr_pm_spipss_clock_divider);} + + + + + + + + + + + + + + + + + + + // ------------------------------------------ + // -- Init procedure + // ------------------------------------------ + + + + // modify_data here +// uint8_t hwctrl_frame_size ; +// uint8_t hwctrl_device =0 ; +// uint8_t hwctrl_clk_pol ; +// uint8_t hwctrl_clk_pha ; +// uint32_t hwctrl_clk_divider; +// uint32_t hwctrl_inter_frame_delay; +// uint16_t nest_freq ; +// // uint16_t spipss_freq ; +// uint8_t hwctrl_in_count; +// uint8_t hwctrl_out_count; +// uint8_t hwctrl_in_delay; + + + uint8_t hwctrl_target = 0xA; + + + + + + uint8_t hwctrl_frame_size = attr_pm_spipss_frame_size ; +// uint8_t hwctrl_out_count = attr_pm_spipss_out_count ; +// uint8_t hwctrl_in_delay = attr_pm_spipss_in_delay ; +// uint8_t hwctrl_in_count = attr_pm_spipss_in_count ; + uint8_t hwctrl_clk_pol = attr_pm_spipss_clock_polarity ; + uint8_t hwctrl_clk_pha = attr_pm_spipss_clock_phase ; + uint32_t hwctrl_clk_divider = attr_pm_spipss_clock_divider ; + uint32_t hwctrl_inter_frame_delay = attr_pm_spipss_inter_frame_delay ; + uint8_t hwctrl_device = attr_pm_apss_chip_select; + uint8_t nest_freq = attr_proc_pss_init_nest_frequency ; + uint32_t spipss_100ns_div_value ; + spipss_100ns_div_value = 4 / ( attr_proc_pss_init_nest_frequency*1000000) * (100 /1000000000); + + + + + + + + // ****************************************************************** + + // - set SPIPSS_ADC_CTRL_REG0 (24b) + // adc_frame_size = 16 + + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_ADC_CTRL_REG0_0x00070000, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_ADC_CTRL_REG0) failed."); return rc; + } + + + + // data.flushTo0(); + // data.setWord(1, 0x41000100); + e_rc=data.insertFromRight(hwctrl_frame_size,0,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS ADC CTRL_REG_0 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" frame size => %d ", hwctrl_frame_size); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_ADC_CTRL_REG0_0x00070000, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_ADC_CTRL_REG0_0x00070000) failed."); return rc; + } + + + + // ****************************************************************** + // - set SPIPSS_ADC_CTRL_REG1 + // adc_fsm_enable = disable + // adc_device = APSS + // adc_cpol = 0 + // adc_cpha = 0 + // adc_clock_divider = set to 10Mhz + // adc_nr_of_frames (4b) = 16 (for auto 2 mode) + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_ADC_CTRL_REG1_0x00070001, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_ADC_CTRL_REG1) failed."); return rc; + } + + // modify_data here + + uint8_t hwctrl_fsm_enable = 0x0 ; + uint8_t hwctrl_nr_of_frames = 0x10 ; + + + // data.flushTo0(); + // rc=data.setWord(1, 0x41000100); if (rc) return rc; + e_rc=data.insertFromRight(hwctrl_fsm_enable ,0,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_device ,1,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_clk_pol ,2,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_clk_pha ,3,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_clk_divider ,4,10); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_nr_of_frames ,14,4); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS ADC CTRL_REG_1 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" hwctrl_fsm_enable => %d ", hwctrl_fsm_enable ); + FAPI_INF(" nest_freq => %d ", nest_freq ); + FAPI_INF(" hwctrl_target => %d ", hwctrl_target ); + FAPI_INF(" hwctrl_device => %d ", hwctrl_device ); + FAPI_INF(" hwctrl_clk_pol => %d ", hwctrl_clk_pol ); + FAPI_INF(" hwctrl_clk_pha => %d ", hwctrl_clk_pha ); + FAPI_INF(" hwctrl_clk_divider => %d ", hwctrl_clk_divider ); + FAPI_INF(" hwctrl_nr_of_frames => %d ", hwctrl_nr_of_frames); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_ADC_CTRL_REG1_0x00070001, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_ADC_CTRL_REG1_0x00070001) failed."); return rc; + } + + + + // ****************************************************************** + // - set SPIPSS_ADC_CTRL_REG2 + // adc_inter_frame_delay = 0x0 + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_ADC_CTRL_REG2_0x00070002, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_ADC_CTRL_REG2) failed."); return rc; + } + // FAPI_INF("sumne data %s " data.genHexLeftStr(0,64) ); + + // modify_data here + + + // rc=data.flushTo0(); if (rc) return rc; + // rc=data.setWord(1, 0x41000100); if (rc) return rc; + e_rc=data.insertFromRight(hwctrl_inter_frame_delay,0,17); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS ADC CTRL_REG_2 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" hwctrl_inter_frm_delay => %d ", hwctrl_inter_frame_delay ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_ADC_CTRL_REG2_0x00070002, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_ADC_CTRL_REG2_0x00070002) failed."); return rc; + } + + + // ****************************************************************** + // - clear SPIPSS_ADC_Wdata_REG + // ****************************************************************** +// rc = fapiGetScom(i_target, SPIPSS_ADC_WDATA_REG_0x00070010, data ); +// if (rc) { +// FAPI_ERR("fapiGetScom(SPIPSS_ADC_WDATA_REG_0x00070010) failed."); return rc; +// } + + // modify_data here + + uint32_t hwctrl_wdata = 0x0; + + e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // e_rc=data.setWord(1, 0x41000100); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(hwctrl_wdata ,0,16); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS_WDATA_REG is cleared "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" hwctrl_wdata => %d ", hwctrl_wdata ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_ADC_WDATA_REG_0x00070010, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_ADC_WDATA_REG_0x00070010) failed."); return rc; + } + + + // ****************************************************************** + // - set SPIPSS_P2S_CTRL_REG0 (24b) + // p2s_frame_size = 16 + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_P2S_CTRL_REG0_0x00070040, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_CTRL_REG0) failed."); return rc; + } + + // modify_data here + uint8_t p2s_frame_size = 0x02 ; + uint8_t p2s_device = 0; + uint8_t p2s_clk_pol = 0; + uint8_t p2s_clk_pha = 0; + uint16_t p2s_clk_divider= 0x1D; + uint8_t p2s_target = 0xA;// DPSS + uint32_t p2s_inter_frame_delay = 0x0; +// uint8_t p2s_in_count1; +// uint8_t p2s_out_count1; +// uint8_t p2s_in_delay1; +// uint8_t p2s_in_count2; +// uint8_t p2s_out_count2; +// uint8_t p2s_in_delay2; + + +// if (p2s_target == 13) +// { +// p2s_device = 1; +// FAPI_INF(" p2s_target_DPSS " ); +// } +// else if (p2s_target == 10) +// { +// p2s_device = 0; +// FAPI_INF(" p2s_target_APSS " ); +// } +// else +// { FAPI_INF(" " ); +// FAPI_ERR("wrong device taget : make sure that you use 0xA=APSS and 0XD=DPSS no other value works"); +// FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PSS_WRONG_DEVICE); +// return rc; +// } + + + + +// p2s_frame_size = 0x10 ; +// p2s_clk_pol = 0; +// p2s_clk_pha = 0; +// p2s_clk_divider= 0x1D; +// p2s_inter_frame_delay = 0x0; + + // calculation of clock divider +// p2s_clk_divider= nest_freq/spipss_freq/8-1 ; + + + p2s_frame_size = attr_pm_spipss_frame_size ; + // p2s_out_count = attr_pm_spipss_out_count ; + // p2s_in_delay = attr_pm_spipss_in_delay ; + // p2s_in_count = attr_pm_spipss_in_count ; + p2s_clk_pol = attr_pm_spipss_clock_polarity ; + p2s_clk_pha = attr_pm_spipss_clock_phase ; + p2s_clk_divider = attr_pm_spipss_clock_divider ; + p2s_inter_frame_delay = attr_pm_spipss_inter_frame_delay ; + // nest_freq = attr_p8_pss_init_nest_frequency ; + // spipss_freq = attr_pm_pss_init_spipss_frequency; + p2s_device = attr_pm_apss_chip_select; + + + + + // ****************************************************************** + // - set SPIPSS_P2S_CTRL_REG0 + // ****************************************************************** + + + rc = fapiGetScom(i_target, SPIPSS_P2S_CTRL_REG0_0x00070040, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_CTRL_REG0) failed."); return rc; + } + + + // e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + // e_rc=data.setWord(1, 0x41000100); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_frame_size,0,6); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS P2S CTRL_REG_0 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" frame size => %d ", p2s_frame_size); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_P2S_CTRL_REG0_0x00070040, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_P2S_CTRL_REG0_0x00070040) failed."); return rc; + } + + + + // ****************************************************************** + // - set SPIPSS_P2S_CTRL_REG1 + // p2s_fsm_enable = disable + // p2s_device = APSS + // p2s_cpol = 0 + // p2s_cpha = 0 + // p2s_clock_divider = set to 10Mhz + // p2s_nr_of_frames (4b) = 16 (for auto 2 mode) + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_P2S_CTRL_REG1_0x00070041, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_CTRL_REG1) failed."); return rc; + } + + // modify_data here + + uint8_t p2s_fsm_enable = 0x0 ; + uint8_t p2s_nr_of_frames = 0x10 ; + + // e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + // e_rc=data.setWord(1, 0x41000100); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_fsm_enable ,0,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_device ,1,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_clk_pol ,2,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_clk_pha ,3,1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_clk_divider ,4,10); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_nr_of_frames ,14,4); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS P2S CTRL_REG_1 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" p2s_fsm_enable => %d ", p2s_fsm_enable ); + FAPI_INF(" p2s_target => %d ", p2s_target ); + FAPI_INF(" p2s_device => %d ", p2s_device ); + FAPI_INF(" p2s_clk_pol => %d ", p2s_clk_pol ); + FAPI_INF(" p2s_clk_pha => %d ", p2s_clk_pha ); + FAPI_INF(" p2s_clk_divider => %d ", p2s_clk_divider ); + FAPI_INF(" p2s_nr_of_frames => %d ", p2s_nr_of_frames); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_P2S_CTRL_REG1_0x00070041, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_P2S_CTRL_REG1_0x00070041) failed."); return rc; + } + + + // ****************************************************************** + // - set SPIPSS_P2S_CTRL_REG2 + // p2s_inter_frame_delay = 0x0 + // ****************************************************************** + + rc = fapiGetScom(i_target, SPIPSS_P2S_CTRL_REG2_0x00070042, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_CTRL_REG2) failed."); return rc; + } + + // modify_data here + + // e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + // e_rc=data.setWord(1, 0x41000100); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_inter_frame_delay,0,17); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS P2S CTRL_REG_2 Configuration "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" p2s_inter_frm_delay => %d ", p2s_inter_frame_delay ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + rc = fapiPutScom(i_target, SPIPSS_P2S_CTRL_REG2_0x00070042, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_P2S_CTRL_REG2_0x00070042) failed."); return rc; + } + + + // ****************************************************************** + // - clear SPIPSS_P2S_Wdata_REG + // ****************************************************************** + rc = fapiGetScom(i_target, SPIPSS_P2S_WDATA_REG_0x00070050, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_WDATA_REG_0x00070050) failed."); return rc; + } + +// modify_data here + + uint32_t p2s_wdata = 0x0; + e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.insertFromRight(p2s_wdata ,0,16); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS_P2S_WDATA_REG is cleared "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" p2s_wdata => %d ", p2s_wdata ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + + + + rc = fapiPutScom(i_target, SPIPSS_P2S_WDATA_REG_0x00070050, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_P2Sb_WDATA_REG_0x00070050) failed."); return rc; + } + + // ****************************************************************** + // - Set 100ns Register for Interframe delay + + // ****************************************************************** + rc = fapiGetScom(i_target, SPIPSS_100NS_REG_0x00070028, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_100NS_REG_0x00070028) failed."); return rc; + } + + // modify_data here + + + e_rc=data.insertFromRight(spipss_100ns_div_value ,0,32); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" SPIPSS_100NS_REG is set the value "); + // FAPI_INF(" -----------------------------------------------------"); + FAPI_INF(" spipss_100ns_div_value => %d ", spipss_100ns_div_value ); + FAPI_INF(" " ); + FAPI_INF(" " ); + // FAPI_INF(" -----------------------------------------------------"); + + rc = fapiPutScom(i_target, SPIPSS_100NS_REG_0x00070028, data ); + if (rc) { + FAPI_ERR("fapiPutScom(SPIPSS_100NS_REG_0x00070028) failed."); return rc; + } + + + + FAPI_INF(""); + FAPI_INF("Executing p8_pss_init ...."); + + } + // ------------------------------- + /// Reset: perform reset of PSS + else if (mode == PM_RESET) + { + + FAPI_INF("PSS reset..."); + // FAPI_INF("PSS reset not yet supported!!!!..."); + + +// ****************************************************************** +// - POLLing status register for ongoing or errors + +// ****************************************************************** + rc = fapiGetScom(i_target, SPIPSS_ADC_STATUS_REG_0x00070003, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_ADC_STATUS_REG_0x00070003) failed."); return rc; + } + FAPI_INF("polling for ongoing to go low ... "); + + while (data.isBitSet(0) && data.isBitClear(5) && pollcount < max_polls) + { + rc = fapiGetScom(i_target, SPIPSS_ADC_STATUS_REG_0x00070003, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_ADC_STATUS_REG_0x00070003) failed."); return rc; + } + FAPI_INF("."); + pollcount++; + + } + + FAPI_INF("Send all the frames from ADC to the device.So now resetting it "); + + pollcount = 0; + +// ****************************************************************** +// - POLLing status register for ongoing or errors + +// ****************************************************************** + rc = fapiGetScom(i_target, SPIPSS_P2S_STATUS_REG_0x00070043, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_STATUS_REG_0x00070043) failed."); return rc; + } + FAPI_INF("polling for ongoing to go low ... "); + + while (data.isBitSet(0) && data.isBitClear(5)&& pollcount < max_polls) + { + rc = fapiGetScom(i_target, SPIPSS_P2S_STATUS_REG_0x00070043, data ); + if (rc) { + FAPI_ERR("fapiGetScom(SPIPSS_P2S_STATUS_REG_0x00070043) failed."); return rc; + } + FAPI_INF("."); + pollcount++; + } + + FAPI_INF("Sent all the frames from P2S bridge to the device."); + + +// ****************************************************************** +// - Resetting both ADC and P2S bridge +// ****************************************************************** + + + FAPI_INF("Resetting P2S and ADC bridge."); + + + e_rc=data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc=data.setBit(1); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + rc=fapiPutScom(i_target, SPIPSS_ADC_RESET_REGISTER_0x00070005 , data); if(rc) return rc; + rc=fapiPutScom(i_target, SPIPSS_P2S_RESET_REGISTER_0x00070045 , data); if(rc) return rc; + + // Reset PMC. However, the bit used means the entire PMC must be reconfigured! + //e_rc=data.clear(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + //e_rc=data.setBit(12); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + // rc=fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data); if(rc) return rc; + + FAPI_INF("Reset procedure is done ."); + + } + + /// ------------------------------- + /// Unsupported Mode + + else { + + FAPI_ERR("Unknown mode passed to p8_pss_init. Mode %x ....", mode); + uint32_t & MODE = mode; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PSS_CODE_BAD_MODE); + + } + + return rc; + +} + + + +//#ifdef FAPIECMD +} //end extern C +//#endif + + + +// Backups + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- +// CONST_UINT64_T( SPIPSS_ADC_CTRL_REG0_0x00070000 , ULL(0x00070000) ); +// CONST_UINT64_T( SPIPSS_ADC_CTRL_REG1_0x00070001 , ULL(0x00070001) ); +// CONST_UINT64_T( SPIPSS_ADC_CTRL_REG2_0x00070002 , ULL(0x00070002) ); +// CONST_UINT64_T( SPIPSS_ADC_STATUS_REG_0x00070003 , ULL(0x00070003) ); +// CONST_UINT64_T( SPIPSS_ADC_CMD_REG_0x00070004 , ULL(0x00070004) ); + +// CONST_UINT64_T( SPIPSS_ADC_WDATA_REG_0x00070010 , ULL(0x00070010) ); +// CONST_UINT64_T( SPIPSS_ADC_RDATA_REG0_0x00070020 , ULL(0x00070020) ); +// CONST_UINT64_T( SPIPSS_ADC_RDATA_REG1_0x00070021 , ULL(0x00070021) ); +// CONST_UINT64_T( SPIPSS_ADC_RDATA_REG2_0x00070022 , ULL(0x00070022) ); +// CONST_UINT64_T( SPIPSS_ADC_RDATA_REG3_0x00070023 , ULL(0x00070023) ); +// CONST_UINT64_T( SPIPSS_100NS_REG_0x00070028 , ULL(0x00070028) ); +// CONST_UINT64_T( SPIPSS_P2S_CTRL_REG0_0x00070040 , ULL(0x00070040) ); +// CONST_UINT64_T( SPIPSS_P2S_CTRL_REG1_0x00070041 , ULL(0x00070041) ); +// CONST_UINT64_T( SPIPSS_P2S_CTRL_REG2_0x00070042 , ULL(0x00070042) ); +// CONST_UINT64_T( SPIPSS_P2S_STATUS_REG_0x00070043 , ULL(0x00070043) ); +// CONST_UINT64_T( SPIPSS_P2S_COMMAND_REG_0x00070044 , ULL(0x00070044) ); + +// CONST_UINT64_T( SPIPSS_P2S_WDATA_REG_0x00070050 , ULL(0x00070050) ); +// CONST_UINT64_T( SPIPSS_P2S_RDATA_REG_0x00070060 , ULL(0x00070060) ); +// CONST_UINT64_T( SPIPSS_ADC_RESET_REGISTER_0x00070005 , ULL(0x00070005) ); +// CONST_UINT64_T( SPIPSS_P2S_RESET_REGISTER_0x00070045 , ULL(0x00070045) ); + + + + + + + +// if (hwctrl_target == 13) +// { +// hwctrl_device = 1; +// FAPI_INF(" hwctrl_target_DPSS " ); +// } +// else if (hwctrl_target == 10) +// { +// hwctrl_device = 0; +// FAPI_INF(" hwctrl_target_APSS " ); +// } +// else +// { +// FAPI_INF(" " ); +// FAPI_ERR("wrong device taget : make sure that you use 0xA=APSS and 0XD=DPSS no other value works"); +// FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PSS_WRONG_DEVICE); +// return rc; +// } + + // ********************************************** + // Add All Attributes related to hwctrl here + // ********************************************** + + +// hwctrl_frame_size = 0x10 ; +// hwctrl_clk_pol = 0; +// hwctrl_clk_pha = 0; +// hwctrl_clk_divider= 0x1D; +// hwctrl_inter_frame_delay = 0x0; +// nest_freq = 600; +// spipss_freq = 10; +// hwctrl_in_count=0; +// hwctrl_out_count=0; +// hwctrl_in_delay=0; + + + + +// uint8_t attr_pm_spipss_frame_size_set = 16 ; +// uint8_t attr_pm_spipss_out_count_set = 16; +// uint8_t attr_pm_spipss_in_delay_set = 0; +// uint8_t attr_pm_spipss_in_count_set = 16; +// uint8_t attr_pm_spipss_clock_polarity_set =0 ; +// uint8_t attr_pm_spipss_clock_phase_set = 0; +// //uint32_t attr_pm_spipss_clock_divider_set = 0; +// uint32_t attr_pm_spipss_inter_frame_delay_set = 1; + + + +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_FRAME_SIZE, &l_pTarget, attr_pm_spipss_frame_size_set); if (rc) return rc; +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_OUT_COUNT, &l_pTarget, attr_pm_spipss_out_count_set); if (rc) return rc; +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_IN_COUNT, &l_pTarget, attr_pm_spipss_in_count_set); if (rc) return rc; +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_IN_DELAY, &l_pTarget, attr_pm_spipss_in_delay_set); if (rc) return rc; + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_CLOCK_POLARITY, &l_pTarget, attr_pm_spipss_clock_polarity_set); if (rc) return rc; + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_CLOCK_PHASE, &l_pTarget, attr_pm_spipss_clock_phase_set); if (rc) return rc; + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_INTER_FRAME_DELAY, &l_pTarget, attr_pm_spipss_inter_frame_delay_set); if (rc) return rc; + +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_INTER_FRAME_DELAY_WRITE_SETTNG, &l_pTarget, attr_pm_spipss_interframe_delay_write_status_value_set); + + + +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIPSS_CLOCK_DIVIDER, &l_pTarget, attr_pm_spipss_clock_divider_set); + + + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H new file mode 100755 index 000000000..9e5394804 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pss_init.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Greg Stilll Email: stillgs@us.ibm.com +// *! +// *! General Description: Calls the function p8_pss_init.C +// *! Initializes the PSS macro , resets it and configures the required +// *! Attributes +//------------------------------------------------------------------------------ +// Calls + +/// \param[in] i_target Chip target +/// \param[in] mode + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pss_init_FP_t) (const fapi::Target&, uint32_t); + + +extern "C" { + +fapi::ReturnCode p8_pss_init(const fapi::Target& i_target, uint32_t mode); + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/pba_firmware_register.H b/src/usr/hwpf/hwp/occ/occ_procedures/pba_firmware_register.H new file mode 100755 index 000000000..51fd5343b --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/pba_firmware_register.H @@ -0,0 +1,1453 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/pba_firmware_register.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* begin_generated_IBM_copyright_prolog */ +/* */ +/* This is an automatically generated copyright prolog. */ +/* After initializing, DO NOT MODIFY OR MOVE */ +/* --------------------------------------------------------------- */ +/* IBM Confidential */ +/* */ +/* Licensed Internal Code Source Materials */ +/* */ +/* (C)Copyright IBM Corp. 2014, 2014 */ +/* */ +/* The Source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* -------------------------------------------------------------- */ +/* */ +/* end_generated_IBM_copyright_prolog */ +// Subversion Repositories OCC +// (root)/ssx/trunk/pgp/registers/pba_firmware_registers.h - Rev 1095 +// Rev + +// Rev 1077 | Blame | Compare with Previous | Last modification | View Log | RSS feed +#ifndef __PBA_FIRMWARE_REGISTERS_H__ +#define __PBA_FIRMWARE_REGISTERS_H__ + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +// $Id: pba_firmware_register.H,v 1.1 2012/01/09 13:46:34 kgungl Exp $ + +/// \file pba_firmware_registers.h +/// \brief C register structs for the PBA unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#include <stdint.h> + + +typedef union pba_barn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cmd_scope : 3; + uint64_t reserved0 : 1; + uint64_t reserved1 : 10; + uint64_t addr : 30; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t addr : 30; + uint64_t reserved1 : 10; + uint64_t reserved0 : 1; + uint64_t cmd_scope : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_barn_t; + + + +typedef union pba_barmskn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 23; + uint64_t mask : 21; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t mask : 21; + uint64_t reserved0 : 23; +#endif // _BIG_ENDIAN + } fields; +} pba_barmskn_t; + + + +typedef union pba_fir { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t reserved : 4; + uint64_t fir_parity_error : 1; + uint64_t _reserved0 : 19; +#else + uint64_t _reserved0 : 19; + uint64_t fir_parity_error : 1; + uint64_t reserved : 4; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_t; + + + +typedef union pba_fir_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t reserved : 4; + uint64_t fir_parity_error : 1; + uint64_t _reserved0 : 19; +#else + uint64_t _reserved0 : 19; + uint64_t fir_parity_error : 1; + uint64_t reserved : 4; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_and_t; + + + +typedef union pba_fir_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t reserved : 4; + uint64_t fir_parity_error : 1; + uint64_t _reserved0 : 19; +#else + uint64_t _reserved0 : 19; + uint64_t fir_parity_error : 1; + uint64_t reserved : 4; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_or_t; + + + +typedef union pba_fir_mask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t mask : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t mask : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_mask_t; + + + +typedef union pba_fir_mask_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t mask : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t mask : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_mask_and_t; + + + +typedef union pba_fir_mask_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t mask : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t mask : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_mask_or_t; + + + +typedef union pba_fir_action0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fir_action0 : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t fir_action0 : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_action0_t; + + + +typedef union pba_fir_action1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fir_action1 : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t fir_action1 : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_action1_t; + + + +typedef union pba_occ_action { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_action_set : 44; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t occ_action_set : 44; +#endif // _BIG_ENDIAN + } fields; +} pba_occ_action_t; + + + +typedef union pba_rbufvaln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t rd_slvnum : 2; + uint64_t cur_rd_addr : 23; + uint64_t spare1 : 3; + uint64_t prefetch : 1; + uint64_t spare2 : 2; + uint64_t abort : 1; + uint64_t spare3 : 1; + uint64_t buffer_status : 7; + uint64_t spare4 : 4; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t spare4 : 4; + uint64_t buffer_status : 7; + uint64_t spare3 : 1; + uint64_t abort : 1; + uint64_t spare2 : 2; + uint64_t prefetch : 1; + uint64_t spare1 : 3; + uint64_t cur_rd_addr : 23; + uint64_t rd_slvnum : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_rbufvaln_t; + + + +typedef union pba_wbufvaln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t wr_slvnum : 2; + uint64_t start_wr_addr : 30; + uint64_t spare1 : 3; + uint64_t wr_buffer_status : 5; + uint64_t spare2 : 1; + uint64_t wr_byte_count : 7; + uint64_t spare3 : 16; +#else + uint64_t spare3 : 16; + uint64_t wr_byte_count : 7; + uint64_t spare2 : 1; + uint64_t wr_buffer_status : 5; + uint64_t spare1 : 3; + uint64_t start_wr_addr : 30; + uint64_t wr_slvnum : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_wbufvaln_t; + + + +typedef union pba_mode { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 4; + uint64_t dis_rearb : 1; + uint64_t reserved1 : 1; + uint64_t dis_slave_rdpipe : 1; + uint64_t dis_slave_wrpipe : 1; + uint64_t en_marker_ack : 1; + uint64_t dis_slvmatch_order : 1; + uint64_t en_second_wrbuf : 1; + uint64_t dis_rerequest_to : 1; + uint64_t inject_type : 2; + uint64_t inject_mode : 2; + uint64_t pba_region : 2; + uint64_t oci_marker_space : 3; + uint64_t bcde_ocitrans : 2; + uint64_t bcue_ocitrans : 2; + uint64_t dis_master_rd_pipe : 1; + uint64_t dis_master_wr_pipe : 1; + uint64_t en_slave_fairness : 1; + uint64_t en_ecvent_count : 1; + uint64_t pb_noci_event_sel : 1; + uint64_t slv_event_mux : 2; + uint64_t enable_debug_bus : 1; + uint64_t debug_pb_not_oci : 1; + uint64_t debug_oci_mode : 5; + uint64_t reserved2 : 1; + uint64_t ocislv_fairness_mask : 5; + uint64_t ocislv_rereq_hang_div : 5; + uint64_t dis_chgrate_count : 1; + uint64_t pbreq_event_mux : 2; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t pbreq_event_mux : 2; + uint64_t dis_chgrate_count : 1; + uint64_t ocislv_rereq_hang_div : 5; + uint64_t ocislv_fairness_mask : 5; + uint64_t reserved2 : 1; + uint64_t debug_oci_mode : 5; + uint64_t debug_pb_not_oci : 1; + uint64_t enable_debug_bus : 1; + uint64_t slv_event_mux : 2; + uint64_t pb_noci_event_sel : 1; + uint64_t en_ecvent_count : 1; + uint64_t en_slave_fairness : 1; + uint64_t dis_master_wr_pipe : 1; + uint64_t dis_master_rd_pipe : 1; + uint64_t bcue_ocitrans : 2; + uint64_t bcde_ocitrans : 2; + uint64_t oci_marker_space : 3; + uint64_t pba_region : 2; + uint64_t inject_mode : 2; + uint64_t inject_type : 2; + uint64_t dis_rerequest_to : 1; + uint64_t en_second_wrbuf : 1; + uint64_t dis_slvmatch_order : 1; + uint64_t en_marker_ack : 1; + uint64_t dis_slave_wrpipe : 1; + uint64_t dis_slave_rdpipe : 1; + uint64_t reserved1 : 1; + uint64_t dis_rearb : 1; + uint64_t reserved0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pba_mode_t; + + + +typedef union pba_slvrst { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t set : 3; + uint64_t notimp1 : 1; + uint64_t in_prog : 4; + uint64_t busy_status : 4; + uint64_t _reserved0 : 52; +#else + uint64_t _reserved0 : 52; + uint64_t busy_status : 4; + uint64_t in_prog : 4; + uint64_t notimp1 : 1; + uint64_t set : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_slvrst_t; + + + +typedef union pba_slvctln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable : 1; + uint64_t mid_match_value : 3; + uint64_t _reserved0 : 1; + uint64_t mid_care_mask : 3; + uint64_t write_ttype : 3; + uint64_t _reserved1 : 4; + uint64_t read_ttype : 1; + uint64_t read_prefetch_ctl : 2; + uint64_t buf_invalidate_ctl : 1; + uint64_t buf_alloc_w : 1; + uint64_t buf_alloc_a : 1; + uint64_t buf_alloc_b : 1; + uint64_t buf_alloc_c : 1; + uint64_t _reserved2 : 1; + uint64_t dis_write_gather : 1; + uint64_t wr_gather_timeout : 3; + uint64_t write_tsize : 7; + uint64_t extaddr : 14; + uint64_t _reserved3 : 15; +#else + uint64_t _reserved3 : 15; + uint64_t extaddr : 14; + uint64_t write_tsize : 7; + uint64_t wr_gather_timeout : 3; + uint64_t dis_write_gather : 1; + uint64_t _reserved2 : 1; + uint64_t buf_alloc_c : 1; + uint64_t buf_alloc_b : 1; + uint64_t buf_alloc_a : 1; + uint64_t buf_alloc_w : 1; + uint64_t buf_invalidate_ctl : 1; + uint64_t read_prefetch_ctl : 2; + uint64_t read_ttype : 1; + uint64_t _reserved1 : 4; + uint64_t write_ttype : 3; + uint64_t mid_care_mask : 3; + uint64_t _reserved0 : 1; + uint64_t mid_match_value : 3; + uint64_t enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_slvctln_t; + + + +typedef union pba_bcde_ctl { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t stop : 1; + uint64_t start : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t start : 1; + uint64_t stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_ctl_t; + +#endif // __ASSEMBLER__ +#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#ifndef __ASSEMBLER__ + + +typedef union pba_bcde_set { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t copy_length : 6; + uint64_t _reserved1 : 56; +#else + uint64_t _reserved1 : 56; + uint64_t copy_length : 6; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_set_t; + + + +typedef union pba_bcde_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t running : 1; + uint64_t waiting : 1; + uint64_t wrcmp : 6; + uint64_t _reserved0 : 6; + uint64_t rdcmp : 6; + uint64_t debug : 9; + uint64_t stopped : 1; + uint64_t error : 1; + uint64_t done : 1; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t done : 1; + uint64_t error : 1; + uint64_t stopped : 1; + uint64_t debug : 9; + uint64_t rdcmp : 6; + uint64_t _reserved0 : 6; + uint64_t wrcmp : 6; + uint64_t waiting : 1; + uint64_t running : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_status_t; + + + +typedef union pba_bcde_pbadr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved1 : 2; + uint64_t extaddr : 14; + uint64_t _reserved2 : 23; +#else + uint64_t _reserved2 : 23; + uint64_t extaddr : 14; + uint64_t _reserved1 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_pbadr_t; + + + +typedef union pba_bcde_ocibar { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t addr : 25; + uint64_t _reserved0 : 39; +#else + uint64_t _reserved0 : 39; + uint64_t addr : 25; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_ocibar_t; + + + +typedef union pba_bcue_ctl { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t stop : 1; + uint64_t start : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t start : 1; + uint64_t stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_ctl_t; + +#endif // __ASSEMBLER__ +#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#ifndef __ASSEMBLER__ + + +typedef union pba_bcue_set { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t copy_length : 6; + uint64_t _reserved1 : 56; +#else + uint64_t _reserved1 : 56; + uint64_t copy_length : 6; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_set_t; + + + +typedef union pba_bcue_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t running : 1; + uint64_t waiting : 1; + uint64_t wrcmp : 6; + uint64_t _reserved0 : 6; + uint64_t rdcmp : 6; + uint64_t debug : 9; + uint64_t stopped : 1; + uint64_t error : 1; + uint64_t done : 1; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t done : 1; + uint64_t error : 1; + uint64_t stopped : 1; + uint64_t debug : 9; + uint64_t rdcmp : 6; + uint64_t _reserved0 : 6; + uint64_t wrcmp : 6; + uint64_t waiting : 1; + uint64_t running : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_status_t; + + + +typedef union pba_bcue_pbadr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved1 : 2; + uint64_t extaddr : 14; + uint64_t _reserved2 : 23; +#else + uint64_t _reserved2 : 23; + uint64_t extaddr : 14; + uint64_t _reserved1 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_pbadr_t; + + + +typedef union pba_bcue_ocibar { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t addr : 25; + uint64_t _reserved0 : 39; +#else + uint64_t _reserved0 : 39; + uint64_t addr : 25; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_ocibar_t; + + + +typedef union pba_pbocrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 16; + uint64_t event : 16; + uint64_t _reserved1 : 12; + uint64_t accum : 20; +#else + uint64_t accum : 20; + uint64_t _reserved1 : 12; + uint64_t event : 16; + uint64_t _reserved0 : 16; +#endif // _BIG_ENDIAN + } fields; +} pba_pbocrn_t; + + + +typedef union pba_xsndtx { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t snd_scope : 3; + uint64_t snd_qid : 1; + uint64_t snd_type : 1; + uint64_t snd_reservation : 1; + uint64_t spare1 : 2; + uint64_t snd_nodeid : 3; + uint64_t snd_chipid : 3; + uint64_t spare2 : 2; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t spare2 : 2; + uint64_t snd_chipid : 3; + uint64_t snd_nodeid : 3; + uint64_t spare1 : 2; + uint64_t snd_reservation : 1; + uint64_t snd_type : 1; + uint64_t snd_qid : 1; + uint64_t snd_scope : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_xsndtx_t; + + + +typedef union pba_xcfg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pbax_en : 1; + uint64_t reservation_en : 1; + uint64_t snd_reset : 1; + uint64_t rcv_reset : 1; + uint64_t rcv_nodeid : 3; + uint64_t rcv_chipid : 3; + uint64_t spare1 : 2; + uint64_t rcv_brdcst_group : 8; + uint64_t rcv_datalo_thresh : 8; + uint64_t snd_retry_thresh : 8; + uint64_t snd_rsv_req_thresh : 2; + uint64_t snd_retry_count_overcom : 1; + uint64_t _reserved0 : 25; +#else + uint64_t _reserved0 : 25; + uint64_t snd_retry_count_overcom : 1; + uint64_t snd_rsv_req_thresh : 2; + uint64_t snd_retry_thresh : 8; + uint64_t rcv_datalo_thresh : 8; + uint64_t rcv_brdcst_group : 8; + uint64_t spare1 : 2; + uint64_t rcv_chipid : 3; + uint64_t rcv_nodeid : 3; + uint64_t rcv_reset : 1; + uint64_t snd_reset : 1; + uint64_t reservation_en : 1; + uint64_t pbax_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xcfg_t; + + + +typedef union pba_xsndstat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t snd_in_progress : 1; + uint64_t snd_error : 1; + uint64_t snd_status : 6; + uint64_t snd_retry_count : 8; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t snd_retry_count : 8; + uint64_t snd_status : 6; + uint64_t snd_error : 1; + uint64_t snd_in_progress : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xsndstat_t; + + + +typedef union pba_xsnddat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pbax_datahi : 32; + uint64_t pbax_datalo : 32; +#else + uint64_t pbax_datalo : 32; + uint64_t pbax_datahi : 32; +#endif // _BIG_ENDIAN + } fields; +} pba_xsnddat_t; + + + +typedef union pba_xrcvstat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t rcv_in_progress : 1; + uint64_t rcv_error : 1; + uint64_t rcv_write_in_progress : 1; + uint64_t rcv_reservation_set : 1; + uint64_t rcv_capture : 14; + uint64_t _reserved0 : 46; +#else + uint64_t _reserved0 : 46; + uint64_t rcv_capture : 14; + uint64_t rcv_reservation_set : 1; + uint64_t rcv_write_in_progress : 1; + uint64_t rcv_error : 1; + uint64_t rcv_in_progress : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xrcvstat_t; + + + +typedef union pba_xshbrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t push_start : 29; + uint64_t _reserved0 : 35; +#else + uint64_t _reserved0 : 35; + uint64_t push_start : 29; +#endif // _BIG_ENDIAN + } fields; +} pba_xshbrn_t; + + + +typedef union pba_xshcsn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t push_full : 1; + uint64_t push_empty : 1; + uint64_t spare1 : 2; + uint64_t push_intr_action : 2; + uint64_t push_length : 5; + uint64_t notimp1 : 2; + uint64_t push_write_ptr : 5; + uint64_t notimp2 : 3; + uint64_t push_read_ptr : 5; + uint64_t notimp3 : 5; + uint64_t push_enable : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t push_enable : 1; + uint64_t notimp3 : 5; + uint64_t push_read_ptr : 5; + uint64_t notimp2 : 3; + uint64_t push_write_ptr : 5; + uint64_t notimp1 : 2; + uint64_t push_length : 5; + uint64_t push_intr_action : 2; + uint64_t spare1 : 2; + uint64_t push_empty : 1; + uint64_t push_full : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xshcsn_t; + + + +typedef union pba_xshincn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 64; +#else + uint64_t reserved : 64; +#endif // _BIG_ENDIAN + } fields; +} pba_xshincn_t; + + +#endif // __ASSEMBLER__ +#endif // __PBA_FIRMWARE_REGISTERS_H__ + + |
