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| author | Shelton Leung <sleung@us.ibm.com> | 2017-08-08 10:23:34 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-21 14:51:49 -0400 |
| commit | f7a823d1fd89870c34205e2067c67d14714c3ef7 (patch) | |
| tree | dbc1903018d27da95ea9d194716f83c46c3926e8 /src | |
| parent | 82b108909e0401fbbb4b55784cc93fcdd7b8d85a (diff) | |
| download | talos-hostboot-f7a823d1fd89870c34205e2067c67d14714c3ef7.tar.gz talos-hostboot-f7a823d1fd89870c34205e2067c67d14714c3ef7.zip | |
DD2 slow mss scrub fix (resurgence of HW397255)
Change-Id: Id24217531bbb5bc00d0f3e143c9938b957ea17e9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44350
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44358
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
3 files changed, 26 insertions, 0 deletions
diff --git a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile index 8b032fa7e..1cac62958 100644 --- a/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile +++ b/src/import/chips/p9/initfiles/p9n.mcs.scom.initfile @@ -168,6 +168,18 @@ espy MC01.PBI01.SCOMFIR.MCPERF1_ENABLE_PREFETCH_PROMOTE [when=S && ATTR_CHIP_EC_ ON; } +# For DD2, HW397255 fix doesn't get configured until mss_thermal_init, so start with this on to protect mss_scrub +espy MC01.PBI01.SCOMFIR.MCMODE0_DISABLE_MC_SYNC [when=S && !ATTR_CHIP_EC_FEATURE_HW397255] { + spyv; + ON; +} + +# For DD2, HW397255 fix doesn't get configured until mss_thermal_init, so start with this on to protect mss_scrub +espy MC01.PBI01.SCOMFIR.MCMODE0_DISABLE_MC_PAIR_SYNC [when=S && !ATTR_CHIP_EC_FEATURE_HW397255] { + spyv; + ON; +} + # Dis Spec Ops for DCBFs (HW414958) dd1 and dd2 ispy MC01.PBI01.SCOMFIR.MCMODE1_DISABLE_SPEC_OP [when=S] { spyv; diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C index 4fa0017d3..7d320eee8 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mcs_scom.C @@ -103,6 +103,10 @@ fapi2::ReturnCode p9n_mcs_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& TGT0 l_scom_buffer.insert<8, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE_ON ); constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF = 0x0; l_scom_buffer.insert<7, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_CENTAURP_ENABLE_ECRESP_OFF ); + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_SYNC_ON = 0x1; + l_scom_buffer.insert<27, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_SYNC_ON ); + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_PAIR_SYNC_ON = 0x1; + l_scom_buffer.insert<28, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_DISABLE_MC_PAIR_SYNC_ON ); FAPI_TRY(fapi2::putScom(TGT0, 0x5010811ull, l_scom_buffer)); } } diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C index af80d2fb8..e86021ea4 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C @@ -181,12 +181,22 @@ fapi2::ReturnCode progMCMODE0( l_scomData.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); } + else + { + l_scomData.clearBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); + l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_SYNC>(); + } if (!l_same_side_functional) { l_scomData.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); } + else + { + l_scomData.clearBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + l_scomMask.setBit<MCS_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + } FAPI_INF("Writing MCS_MCMODE0 reg 0x%.16llX: Mask 0x%.16llX , Data 0x%.16llX", MCS_MCMODE0, l_scomMask, l_scomData); |
