summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorStephen Glancy <sglancy@us.ibm.com>2019-06-05 12:15:04 -0400
committerChristian R. Geddes <crgeddes@us.ibm.com>2019-06-18 10:21:37 -0500
commitea9fb95e6c5a4a069a21c0a17dca1eb0f5ffe2e9 (patch)
tree3bdbe413414117ee8871a2f84dd784dab33454df /src
parent42dbafc33bfa91e9a2f96ed8653958091640ba3b (diff)
downloadtalos-hostboot-ea9fb95e6c5a4a069a21c0a17dca1eb0f5ffe2e9.tar.gz
talos-hostboot-ea9fb95e6c5a4a069a21c0a17dca1eb0f5ffe2e9.zip
Adds axone support for p9_throttle_sync
Change-Id: Ic63667f4798efebda5b1030a495b4a844706831d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78387 Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78413 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C33
1 files changed, 26 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C
index e62ff6ab1..99b98b778 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -79,13 +79,30 @@ template<>
uint8_t findNumDimms(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_miTarget)
{
FAPI_DBG("Entering findNumDimms");
- auto l_dmiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_DMI>();
uint8_t l_num_dimms = 0;
- for (auto l_dmi : l_dmiChiplets)
+ // Cumulus code
+ const auto& l_dmiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_DMI>();
+
+ for (const auto& l_dmi : l_dmiChiplets)
+ {
+ const auto& l_memBufs = l_dmi.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
+
+ if (l_memBufs.size() > 0)
+ {
+ l_num_dimms++;
+ }
+ }
+
+ FAPI_DBG("After number of DIMM's after cumulus targets %u", l_num_dimms);
+
+ // Axone code
+ const auto& l_omiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_OMI>();
+
+ for (const auto& l_omi : l_omiChiplets)
{
- auto l_memBufs = l_dmi.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>();
+ const auto& l_memBufs = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>();
if (l_memBufs.size() > 0)
{
@@ -93,6 +110,8 @@ uint8_t findNumDimms(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_miTarget)
}
}
+ FAPI_DBG("After number of DIMM's after axone targets %u", l_num_dimms);
+
FAPI_DBG("Exiting findNumDimms");
return l_num_dimms;
}
@@ -374,7 +393,7 @@ fapi2::ReturnCode throttleSync(
}
// Program the MCMODE0 if HW397255 is not enabled which means we
- // should have a chip with Nimbus DD2+ or Cumulus.
+ // should have a chip with Nimbus DD2+ or Cumulus/Axone.
if (i_HW397255_enabled == 0)
{
progMCMODE0(l_mc, i_mcTargets);
@@ -442,7 +461,7 @@ extern "C"
// HW397255 requires to also program a master MCS on MC23 if
// it has DIMMs.
// This should only be enabled for Nimbus DD1, disabled for Nimbus DD2
- // and Cumulus.
+ // and Cumulus/Axone.
fapi2::ATTR_CHIP_EC_FEATURE_HW397255_Type l_HW397255_enabled;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW397255,
i_target, l_HW397255_enabled),
@@ -456,7 +475,7 @@ extern "C"
(uint64_t)fapi2::current_err);
}
- // Cumulus
+ // Cumulus/Axone
if (l_miChiplets.size() > 0)
{
FAPI_TRY(throttleSync(l_miChiplets, l_HW397255_enabled),
OpenPOWER on IntegriCloud