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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2017-06-12 04:46:57 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-20 10:47:02 -0400 |
| commit | e4db240642ee48563458cf3ac15d5ad85e41e103 (patch) | |
| tree | 556a18cfa550797eea3dc03c2731014654a21475 /src | |
| parent | 59e501ebede88684938b75cb8dbd00275099979f (diff) | |
| download | talos-hostboot-e4db240642ee48563458cf3ac15d5ad85e41e103.tar.gz talos-hostboot-e4db240642ee48563458cf3ac15d5ad85e41e103.zip | |
P9_start_cbs updates
Adding FIFO reset
Change-Id: Iddcc70f072d308fafcd16d929b02d7acbb0f4a6e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41816
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41820
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C index 54a212f6c..3ddc71375 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C @@ -54,7 +54,8 @@ enum P9_START_CBS_Private_Constants // max : 64k x (1/50MHz) = 128k x 10(-8) = 1280 us] P9_CBS_IDLE_SIM_CYCLE_DELAY = 7500000, // unit is sim cycles,to match the poll count change( 250000 * 30 ) P9_PIBRESET_HW_NS_DELAY = 4000, // 256 pibclocks - P9_PIBRESET_SIM_CYCLE_DELAY = 256000 + P9_PIBRESET_SIM_CYCLE_DELAY = 256000, + FIFO_RESET = 0x80000000 }; fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> @@ -162,6 +163,9 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> fapi2::delay(P9_PIBRESET_HW_NS_DELAY, P9_PIBRESET_SIM_CYCLE_DELAY); } + FAPI_DBG("FIFO reset"); + FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_FSB_FSB_DOWNFIFO_RESET_FSI, FIFO_RESET)); + if ( i_sbe_start ) { FAPI_DBG("Setting up hreset"); |
