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authorAmit Tendolkar <amit.tendolkar@in.ibm.com>2017-12-04 10:02:28 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-12-11 17:59:23 -0500
commitdb7de0c59ffc6046d9e6c8faa43707a7bc5946e9 (patch)
tree9f4b62fc40d0ede65c658714d75b996cbe0b28ec /src
parent45824ede1fc0942802fb11589514bb8739a15e1d (diff)
downloadtalos-hostboot-db7de0c59ffc6046d9e6c8faa43707a7bc5946e9.tar.gz
talos-hostboot-db7de0c59ffc6046d9e6c8faa43707a7bc5946e9.zip
Change PPE State FFDC into a human readable format in eSEL/PEL
Rewriting error xml and ffdc callback to add PPE State registers to FAPI FFDC such that the default FAPI RC parsers are able to genereate user readable FFDC in the plat commited error logs Change-Id: I156e347bafca6f29b2168fcb5f8e70864d4cb670 RTC: 182225 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50435 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50439 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/ffdc/p9_collect_ppe_state.C389
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_collect_ppe_state.xml49
2 files changed, 391 insertions, 47 deletions
diff --git a/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_ppe_state.C b/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_ppe_state.C
index e62aa5e8f..de032a165 100644
--- a/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_ppe_state.C
+++ b/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_ppe_state.C
@@ -42,6 +42,343 @@
extern "C"
{
+ uint32_t addFfdcDataSprs ( std::vector<PPERegValue_t>& i_sprList,
+ fapi2::ReturnCode& o_rc )
+ {
+ FAPI_INF (">>addFfdcDataSprs: input list count %d", i_sprList.size());
+ uint32_t l_regCount = 0;
+
+ // Init FFDC to a detault pattern
+ uint32_t l_defaultVal = 0xDEADC0DE;
+ fapi2::ffdc_t REG_DEFAULT;
+ REG_DEFAULT.ptr() = static_cast<void*>(&l_defaultVal);
+ REG_DEFAULT.size() = sizeof (l_defaultVal);
+
+ fapi2::ffdc_t REG_MSR = REG_DEFAULT;
+ fapi2::ffdc_t REG_CR = REG_DEFAULT;
+ fapi2::ffdc_t REG_CTR = REG_DEFAULT;
+ fapi2::ffdc_t REG_LR = REG_DEFAULT;
+ fapi2::ffdc_t REG_ISR = REG_DEFAULT;
+ fapi2::ffdc_t REG_SRR0 = REG_DEFAULT;
+ fapi2::ffdc_t REG_SRR1 = REG_DEFAULT;
+ fapi2::ffdc_t REG_TCR = REG_DEFAULT;
+ fapi2::ffdc_t REG_TSR = REG_DEFAULT;
+ fapi2::ffdc_t REG_DACR = REG_DEFAULT;
+ fapi2::ffdc_t REG_DBCR = REG_DEFAULT;
+ fapi2::ffdc_t REG_DEC = REG_DEFAULT;
+ fapi2::ffdc_t REG_IVPR = REG_DEFAULT;
+ fapi2::ffdc_t REG_PIR = REG_DEFAULT;
+ fapi2::ffdc_t REG_PVR = REG_DEFAULT;
+ fapi2::ffdc_t REG_XER = REG_DEFAULT;
+
+ for (auto& it : i_sprList)
+ {
+ ++l_regCount;
+
+ switch (it.number)
+ {
+ // Special SPRs
+ case MSR:
+ REG_MSR.ptr() = static_cast<void*>(&it.value);
+ REG_MSR.size() = sizeof (it.value);
+ break;
+
+ case CR:
+ REG_CR.ptr() = static_cast<void*>(&it.value);
+ REG_CR.size() = sizeof (it.value);
+ break;
+
+ // Major SPRs
+ case CTR:
+ REG_CTR.ptr() = static_cast<void*>(&it.value);
+ REG_CTR.size() = sizeof (it.value);
+ break;
+
+ case LR:
+ REG_LR.ptr() = static_cast<void*>(&it.value);
+ REG_LR.size() = sizeof (it.value);
+ break;
+
+ case ISR:
+ REG_ISR.ptr() = static_cast<void*>(&it.value);
+ REG_ISR.size() = sizeof (it.value);
+ break;
+
+ case SRR0:
+ REG_SRR0.ptr() = static_cast<void*>(&it.value);
+ REG_SRR0.size() = sizeof (it.value);
+ break;
+
+ case SRR1:
+ REG_SRR1.ptr() = static_cast<void*>(&it.value);
+ REG_SRR1.size() = sizeof (it.value);
+ break;
+
+ case TCR:
+ REG_TCR.ptr() = static_cast<void*>(&it.value);
+ REG_TCR.size() = sizeof (it.value);
+ break;
+
+ case TSR:
+ REG_TSR.ptr() = static_cast<void*>(&it.value);
+ REG_TSR.size() = sizeof (it.value);
+ break;
+
+ // Minor SPRs
+ case DACR:
+ REG_DACR.ptr() = static_cast<void*>(&it.value);
+ REG_DACR.size() = sizeof (it.value);
+ break;
+
+ case DBCR:
+ REG_DBCR.ptr() = static_cast<void*>(&it.value);
+ REG_DBCR.size() = sizeof (it.value);
+ break;
+
+ case DEC:
+ REG_DEC.ptr() = static_cast<void*>(&it.value);
+ REG_DEC.size() = sizeof (it.value);
+ break;
+
+ case IVPR:
+ REG_IVPR.ptr() = static_cast<void*>(&it.value);
+ REG_IVPR.size() = sizeof (it.value);
+ break;
+
+ case PIR:
+ REG_PIR.ptr() = static_cast<void*>(&it.value);
+ REG_PIR.size() = sizeof (it.value);
+ break;
+
+ case PVR:
+ REG_PVR.ptr() = static_cast<void*>(&it.value);
+ REG_PVR.size() = sizeof (it.value);
+ break;
+
+ case XER:
+ REG_XER.ptr() = static_cast<void*>(&it.value);
+ REG_XER.size() = sizeof (it.value);
+ break;
+
+ default:
+ l_regCount--;
+ FAPI_ERR ("Unknown PPE SPR %d", it.number);
+ break;
+ }
+ }
+
+ // add data to ffdc only something was collected
+ if (i_sprList.size() != 0)
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_SPR);
+ FAPI_INF ("<< addFfdcDataSprs: %d SPRs added to FFDC", l_regCount);
+ i_sprList.clear ();
+ }
+
+ return l_regCount;
+ }
+
+ uint32_t addFfdcDataXirs ( std::vector<PPERegValue_t>& i_xirList,
+ fapi2::ReturnCode& o_rc )
+ {
+ FAPI_INF (">> addFfdcDataXirs: input list count %d", i_xirList.size());
+ uint32_t l_regCount = 0;
+
+ // Init FFDC to a detault pattern
+ uint32_t l_defaultVal = 0xDEADC0DE;
+ fapi2::ffdc_t REG_DEFAULT;
+ REG_DEFAULT.ptr() = static_cast<void*>(&l_defaultVal);
+ REG_DEFAULT.size() = sizeof (l_defaultVal);
+
+ fapi2::ffdc_t REG_XSR = REG_DEFAULT;
+ fapi2::ffdc_t REG_IAR = REG_DEFAULT;
+ fapi2::ffdc_t REG_IR = REG_DEFAULT;
+ fapi2::ffdc_t REG_EDR = REG_DEFAULT;
+ fapi2::ffdc_t REG_SPRG0 = REG_DEFAULT;
+
+ for (auto& it : i_xirList)
+ {
+ ++l_regCount;
+
+ switch (it.number)
+ {
+ case XSR:
+ REG_XSR.ptr() = static_cast<void*>(&it.value);
+ REG_XSR.size() = sizeof (it.value);
+ break;
+
+ case IAR:
+ REG_IAR.ptr() = static_cast<void*>(&it.value);
+ REG_IAR.size() = sizeof (it.value);
+ break;
+
+ case IR:
+ REG_IR.ptr() = static_cast<void*>(&it.value);
+ REG_IR.size() = sizeof (it.value);
+ break;
+
+ case EDR:
+ REG_EDR.ptr() = static_cast<void*>(&it.value);
+ REG_EDR.size() = sizeof (it.value);
+ break;
+
+ case SPRG0:
+ REG_SPRG0.ptr() = static_cast<void*>(&it.value);
+ REG_SPRG0.size() = sizeof (it.value);
+ break;
+
+ default:
+ l_regCount--;
+ FAPI_ERR ("Unknown PPE XIR %d", it.number);
+ break;
+ }
+ }
+
+ // add data to ffdc only something was collected
+ if ( i_xirList.size() != 0 )
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_XIR);
+ FAPI_INF ("<< addFfdcDataXirs: %d XIRs added to FFDC", l_regCount);
+ i_xirList.clear ();
+ }
+
+ return l_regCount;
+ }
+
+
+ uint32_t addFfdcDataGprs ( std::vector<PPERegValue_t>& i_gprList,
+ fapi2::ReturnCode& o_rc )
+ {
+ FAPI_INF (">> addFfdcDataGprs: input list count %d", i_gprList.size());
+ uint32_t l_regCount = 0;
+
+ // Init FFDC to a detault pattern
+ uint32_t l_defaultVal = 0xDEADC0DE;
+ fapi2::ffdc_t REG_DEFAULT;
+ REG_DEFAULT.ptr() = static_cast<void*>(&l_defaultVal);
+ REG_DEFAULT.size() = sizeof (l_defaultVal);
+
+ fapi2::ffdc_t REG_R0 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R1 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R2 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R3 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R4 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R5 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R6 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R7 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R8 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R9 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R10 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R13 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R28 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R29 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R30 = REG_DEFAULT;
+ fapi2::ffdc_t REG_R31 = REG_DEFAULT;
+
+ for (auto& it : i_gprList)
+ {
+ ++l_regCount;
+
+ switch (it.number)
+ {
+ case R0:
+ REG_R0.ptr() = static_cast<void*>(&it.value);
+ REG_R0.size() = sizeof (it.value);
+ break;
+
+ case R1:
+ REG_R1.ptr() = static_cast<void*>(&it.value);
+ REG_R1.size() = sizeof (it.value);
+ break;
+
+ case R2:
+ REG_R2.ptr() = static_cast<void*>(&it.value);
+ REG_R2.size() = sizeof (it.value);
+ break;
+
+ case R3:
+ REG_R3.ptr() = static_cast<void*>(&it.value);
+ REG_R3.size() = sizeof (it.value);
+ break;
+
+ case R4:
+ REG_R4.ptr() = static_cast<void*>(&it.value);
+ REG_R4.size() = sizeof (it.value);
+ break;
+
+ case R5:
+ REG_R5.ptr() = static_cast<void*>(&it.value);
+ REG_R5.size() = sizeof (it.value);
+ break;
+
+ case R6:
+ REG_R6.ptr() = static_cast<void*>(&it.value);
+ REG_R6.size() = sizeof (it.value);
+ break;
+
+ case R7:
+ REG_R7.ptr() = static_cast<void*>(&it.value);
+ REG_R7.size() = sizeof (it.value);
+ break;
+
+ case R8:
+ REG_R8.ptr() = static_cast<void*>(&it.value);
+ REG_R8.size() = sizeof (it.value);
+ break;
+
+ case R9:
+ REG_R9.ptr() = static_cast<void*>(&it.value);
+ REG_R9.size() = sizeof (it.value);
+ break;
+
+ case R10:
+ REG_R10.ptr() = static_cast<void*>(&it.value);
+ REG_R10.size() = sizeof (it.value);
+ break;
+
+ case R13:
+ REG_R13.ptr() = static_cast<void*>(&it.value);
+ REG_R13.size() = sizeof (it.value);
+ break;
+
+ case R28:
+ REG_R28.ptr() = static_cast<void*>(&it.value);
+ REG_R28.size() = sizeof (it.value);
+ break;
+
+ case R29:
+ REG_R29.ptr() = static_cast<void*>(&it.value);
+ REG_R29.size() = sizeof (it.value);
+ break;
+
+ case R30:
+ REG_R30.ptr() = static_cast<void*>(&it.value);
+ REG_R30.size() = sizeof (it.value);
+ break;
+
+ case R31:
+ REG_R31.ptr() = static_cast<void*>(&it.value);
+ REG_R31.size() = sizeof (it.value);
+ break;
+
+ default:
+ l_regCount--;
+ FAPI_ERR ("Unknown PPE GPR %d", it.number);
+ break;
+ }
+ }
+
+ // add data to ffdc only something was collected
+ if (i_gprList.size () != 0)
+ {
+ FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_GPR);
+ FAPI_INF ("<< addFfdcDataGprs: %d GPRs added to FFDC", l_regCount);
+ i_gprList.clear ();
+ }
+
+ return l_regCount;
+ }
+
fapi2::ReturnCode
p9_collect_ppe_state ( const fapi2::ffdc_t& i_target,
const fapi2::ffdc_t& i_mode,
@@ -50,10 +387,8 @@ extern "C"
{
FAPI_INF (">> p9_collect_ppe_state");
fapi2::ReturnCode l_rc;
-
- fapi2::ffdc_t PPE_REG_NR;
- fapi2::ffdc_t PPE_REG_VAL;
fapi2::ATTR_INITIATED_PM_RESET_Type l_pm_reset_active;
+ fapi2::ffdc_t PPE_BASE_ADDR;
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc_chip =
*(reinterpret_cast<const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> *>
@@ -84,6 +419,7 @@ extern "C"
for (auto& it1 : l_ppe_addresses )
{
fapi2::ReturnCode l_rc_tmp = fapi2::current_err;
+ uint64_t l_addr = it1;
FAPI_INF ("p9_collect_ppe_state: PPE Base Addr 0x%.16llX, 0x%.8X",
it1, l_mode);
@@ -92,51 +428,22 @@ extern "C"
// Ignore l_rc and continue adding whatever was collected
- // @TODO via RTC: 175232
- // Restore current_err to what was passed in
fapi2::current_err = l_rc_tmp;
FAPI_INF ("Adding PPE Addr: 0x%.16llX, SPRs: %d XIRs: %d GPRs: %d",
it1, l_v_sprs.size(), l_v_xirs.size(), l_v_gprs.size());
- for (auto& it : l_v_sprs)
- {
- PPE_REG_NR.ptr() = static_cast<void*>(&it.number);
- PPE_REG_NR.size() = sizeof (it.number);
-
- PPE_REG_VAL.ptr() = static_cast<void*>(&it.value);
- PPE_REG_VAL.size() = sizeof (it.value);
-
- FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_SPR);
- }
-
- l_v_sprs.clear();
-
- for (auto& it : l_v_xirs)
- {
- PPE_REG_NR.ptr() = static_cast<void*>(&it.number);
- PPE_REG_NR.size() = sizeof (it.number);
-
- PPE_REG_VAL.ptr() = static_cast<void*>(&it.value);
- PPE_REG_VAL.size() = sizeof (it.value);
-
- FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_XIR);
- }
-
- l_v_xirs.clear();
-
- for (auto& it : l_v_gprs)
- {
- PPE_REG_NR.ptr() = static_cast<void*>(&it.number);
- PPE_REG_NR.size() = sizeof (it.number);
-
- PPE_REG_VAL.ptr() = static_cast<void*>(&it.value);
- PPE_REG_VAL.size() = sizeof (it.value);
+ // since this accepts multiple PPE addresses, log which PPE Addr the
+ // FFDC Data belongs to, to the FFDC info
- FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_STATE_DATA_GPR);
- }
+ PPE_BASE_ADDR.ptr() = static_cast<void*>(&l_addr);
+ PPE_BASE_ADDR.size() = sizeof (l_addr);
+ FAPI_ADD_INFO_TO_HWP_ERROR (o_rc, RC_PPE_BASE_ADDR_XIXCR);
- l_v_gprs.clear ();
+ // Add all the PPE State Registers to the FFDC
+ addFfdcDataXirs (l_v_xirs, o_rc);
+ addFfdcDataSprs (l_v_sprs, o_rc);
+ addFfdcDataGprs (l_v_gprs, o_rc);
}
FAPI_INF ("<< p9_collect_ppe_state");
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_collect_ppe_state.xml b/src/import/chips/p9/procedures/xml/error_info/p9_collect_ppe_state.xml
index b8b68a5b7..7c7007ade 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_collect_ppe_state.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_collect_ppe_state.xml
@@ -26,24 +26,61 @@
<hwpErrors>
<!--************************************************************************-->
<hwpError>
+ <rc>RC_PPE_BASE_ADDR_XIXCR</rc>
+ <description>PPE Instance Base Address Used for Ramming</description>
+ <ffdc>PPE_BASE_ADDR</ffdc>
+ </hwpError>
+<!--************************************************************************-->
+ <hwpError>
<rc>RC_PPE_STATE_DATA_SPR</rc>
<description>PPE SPR Data</description>
- <ffdc>PPE_REG_NR</ffdc>
- <ffdc>PPE_REG_VAL</ffdc>
+ <ffdc>REG_MSR</ffdc>
+ <ffdc>REG_CR</ffdc>
+ <ffdc>REG_CTR</ffdc>
+ <ffdc>REG_LR</ffdc>
+ <ffdc>REG_ISR</ffdc>
+ <ffdc>REG_SRR0</ffdc>
+ <ffdc>REG_SRR1</ffdc>
+ <ffdc>REG_TCR</ffdc>
+ <ffdc>REG_TSR</ffdc>
+ <ffdc>REG_DACR</ffdc>
+ <ffdc>REG_DBCR</ffdc>
+ <ffdc>REG_DEC</ffdc>
+ <ffdc>REG_IVPR</ffdc>
+ <ffdc>REG_PIR</ffdc>
+ <ffdc>REG_PVR</ffdc>
+ <ffdc>REG_XER</ffdc>
</hwpError>
<!--************************************************************************-->
<hwpError>
<rc>RC_PPE_STATE_DATA_XIR</rc>
<description>PPE XIR Data</description>
- <ffdc>PPE_REG_NR</ffdc>
- <ffdc>PPE_REG_VAL</ffdc>
+ <ffdc>REG_XSR</ffdc>
+ <ffdc>REG_IAR</ffdc>
+ <ffdc>REG_IR</ffdc>
+ <ffdc>REG_EDR</ffdc>
+ <ffdc>REG_SPRG0</ffdc>
</hwpError>
<!--************************************************************************-->
<hwpError>
<rc>RC_PPE_STATE_DATA_GPR</rc>
<description>PPE GPR Data</description>
- <ffdc>PPE_REG_NR</ffdc>
- <ffdc>PPE_REG_VAL</ffdc>
+ <ffdc>REG_R0</ffdc>
+ <ffdc>REG_R1</ffdc>
+ <ffdc>REG_R2</ffdc>
+ <ffdc>REG_R3</ffdc>
+ <ffdc>REG_R4</ffdc>
+ <ffdc>REG_R5</ffdc>
+ <ffdc>REG_R6</ffdc>
+ <ffdc>REG_R7</ffdc>
+ <ffdc>REG_R8</ffdc>
+ <ffdc>REG_R9</ffdc>
+ <ffdc>REG_R10</ffdc>
+ <ffdc>REG_R13</ffdc>
+ <ffdc>REG_R28</ffdc>
+ <ffdc>REG_R29</ffdc>
+ <ffdc>REG_R30</ffdc>
+ <ffdc>REG_R31</ffdc>
</hwpError>
<!--************************************************************************-->
</hwpErrors>
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