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authorAmit Kumar <akumar3@us.ibm.com>2016-01-13 10:24:32 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2016-02-26 17:38:44 -0600
commitda05b018735c570e2da53d9d547e12e92c83c130 (patch)
treedb92c0fad849eb7cca61373748188757b5562470 /src
parentb1d81b724f5dbc9bf24074c722db743979bbde7c (diff)
downloadtalos-hostboot-da05b018735c570e2da53d9d547e12e92c83c130.tar.gz
talos-hostboot-da05b018735c570e2da53d9d547e12e92c83c130.zip
L2 stop_gpe_init
- Move to use of IVPR setting and Hard Reset for starting - IVPR value comes from a HWP attribute written by p9_hcode_image_build. The value written will be for the SGPE Boot Copier and will decouples this procedure from HOMER layout changes. - Added -set_hcode_done option to wrapper to force condition without real HCode - Added SUET actions - add missing p9_pm_hcd_flags.h file - address Gerrit comments (including HB) - Rebased (4) Change-Id: I0b5a94a16b0aff811eb526434ca6d02f51c781a8 RTC: 144279 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23274 Tested-by: Jenkins Server Tested-by: Auto Mirror Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24718 Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm.H23
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C220
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk5
3 files changed, 211 insertions, 37 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H
index a9972c3e1..463f0decb 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H
@@ -49,6 +49,29 @@
#define BIT(b) BITS((b), 1)
#endif
+extern const char* p9_PM_FLOW_MODE_NAME[];
+
+#define PM_FLOW_MODE_NAME \
+ { \
+ "PM_RESET", \
+ "PM_INIT", \
+ "PM_SETUP", \
+ "PM_SETUP_PIB", \
+ "PM_SETUP_ALL", \
+ "PM_RESET_SOFT", \
+ "PM_INIT_SOFT", \
+ "PM_INIT_SPECIAL" \
+ }
+
+#define PM_MODE_NAME_VAR p9_PM_FLOW_MODE_NAME[] = PM_FLOW_MODE_NAME
+
+#define PM_MODE_NAME(_mi_mode)( \
+ p9_PM_FLOW_MODE_NAME[_mi_mode-1] \
+ )
+
+
+
+
//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
index d5f76fdf0..c42294649 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C
@@ -1,13 +1,13 @@
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
-/* $Source: chips/p9/procedures/ipl/hwp/p9_pm_ocb_indir_access.C $ */
+/* $Source: chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C $ */
/* */
/* IBM CONFIDENTIAL */
/* */
/* EKB Project */
/* */
-/* COPYRIGHT 2015 */
+/* COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -32,13 +32,17 @@
/// if PM_RESET
/// - Halt the SGPE
/// if PM_INIT
-/// - Sets the IAR to the SGPE bootloader in HOMER.
-/// - HOMER base (PBABAR0 + 1MB) + 16B
-/// - Starts the SGPE and polls OCC Flag bit for HCode init completion
-/// - Starting the SGPE will cause a "reboot" of functional CMEs
-/// - SGPE will cause Block Copy Engine to pull CPMR code, common rings
+/// - call p9_pm_pfet_init to initialize the PFET controllers from
+/// attribute values
+/// - call p9_pm_pba_init in PM_RESET mode to get the PBA in "boot" mode
+/// - Read the SGPE IVPR value that is in HOMER from Attribute written
+/// by p9_hcode_image_build
+/// - Sreset the SGPE to start the boot copier from .
+/// - Polls OCC Flag bit for HCode init completion
+/// - Starting the SGPE will cause a "reboot" of functional CMEs
+/// - SGPE will cause Block Copy Engine to pull CPMR code, common rings
/// and Core Pstate Parameter Block into CME SRAM
-/// - SGPE checks that CME STOP functions have started as part of the
+/// - SGPE checks that CME STOP functions have started as part of the
/// HCode init complete
/// @endverbatim
@@ -46,13 +50,24 @@
// Includes
// -----------------------------------------------------------------------------
-#include "p9_pm_stop_gpe_init.H"
+#include <p9_hcd_common.H>
+#include <p9_pm_stop_gpe_init.H>
+#include <p9_pm_pba_init.H>
+#include <p9_pm_pfet_init.H>
-// This will be uncommented upon the formal availabilty
+// @todo RTC 147679 This will be uncommented upon the formal availability
+// This is needed to initialize the special wakeup tracking attributes
+// in stop_corecache_setup section
//#include "p9_cpu_special_wakeup.H"
-//#include "p9_pm_pfet_init.H"
+// ----------------------------------------------------------------------
+// Constants
+// ----------------------------------------------------------------------
+
+// Map the auto generated names to clearer ones
+static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1;
+static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2;
// -----------------------------------------------------------------------------
// Function prototypes
@@ -84,43 +99,62 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const p9pm::PM_FLOW_MODE i_mode)
{
- FAPI_IMP("p9_pm_stop_gpe_init start");
-#if 0
-
- const char* PM_MODE_NAME_VAR; /// Defines storage for PM_MODE_NAME
+ FAPI_IMP("> p9_pm_stop_gpe_init");
+ const char* PM_MODE_NAME_VAR; //Defines storage for PM_MODE_NAME
FAPI_INF("Executing p9_stop_gpe_init in mode %s", PM_MODE_NAME(i_mode));
-
// -------------------------------
// Initialization: perform order or dynamic operations to initialize
- // the SLW using necessary Platform or Feature attributes.
- if (i_mode == PM_INIT)
+ // the STOP funciton using necessary Platform or Feature attributes.
+ if (i_mode == p9pm::PM_INIT)
{
- rc = stop_gpe_init(i_target, i_mode);
+
+ // Initialize the PFET controllers
+ FAPI_EXEC_HWP(fapi2::current_err, p9_pm_pfet_init, i_target, i_mode);
+
+ FAPI_ASSERT(fapi2::current_err == fapi2::FAPI2_RC_SUCCESS,
+ fapi2::STOP_GPE_PFETS_FAILED()
+ .set_TARGET(i_target)
+ .set_MODE(i_mode),
+ "PFET setup failed");
+
+
+ // Condition the PBA back to the base boot configuration
+ FAPI_EXEC_HWP(fapi2::current_err, p9_pm_pba_init, i_target, p9pm::PM_RESET);
+
+ FAPI_ASSERT(fapi2::current_err == fapi2::FAPI2_RC_SUCCESS,
+ fapi2::STOP_GPE_PBA_INIT_FAILED()
+ .set_TARGET(i_target)
+ .set_MODE(p9pm::PM_RESET),
+ "PBA setup failed");
+
+ // Boot the STOP GPE
+ FAPI_TRY(stop_gpe_init(i_target), "ERROR: failed to initialize Stop GPE");
}
//-------------------------------
- // Reset: perform reset of SLW engine so that it can reconfigured and
- // reinitialized
- else if (i_mode == PM_RESET)
+ // Reset: perform reset of STOP function including the STOP GPE
+ // so that it can reconfigured and reinitialized
+ else if (i_mode == p9pm::PM_RESET)
{
- rc = stop_gpe_reset(i_target);
+ FAPI_TRY(stop_gpe_reset(i_target), "ERROR: failed to reset Stop GPE");
}
// -------------------------------
// Unsupported Mode
else
{
-
FAPI_ERR("Unknown mode passed to p9_stop_gpe_init. Mode %x ....", i_mode);
- uint32_t& IMODE = i_mode;
- FAPI_SET_HWP_ERROR(rc, RC_PROCPM_STOP_GPE_CODE_BAD_MODE);
-
+ FAPI_ASSERT(false,
+ fapi2::STOP_GPE_BAD_MODE()
+ .set_BADMODE(i_mode),
+ "ERROR; Unknown mode passed to stop_gpe_init. Mode %x",
+ i_mode);
}
-#endif
- FAPI_INF("p9_pm_stop_gpe_init end");
+fapi_try_exit:
+ FAPI_INF("< p9_pm_stop_gpe_init");
return fapi2::current_err;
}
@@ -132,17 +166,60 @@ fapi2::ReturnCode p9_pm_stop_gpe_init(
///
/// @param [in] i_target Chip target
///
-/// @retval FAPI_RC_SUCCESS
-/// @retval ERROR defined in xml
+/// @retval FAPI_RC_SUCCESS else ERROR defined in xml
fapi2::ReturnCode stop_gpe_init(
- const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
- const uint32_t i_mode)
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
+ fapi2::buffer<uint64_t> l_occ_flag;
+ fapi2::buffer<uint64_t> l_xcr;
+ fapi2::buffer<uint64_t> l_xsr;
+ fapi2::buffer<uint64_t> l_ivpr;
+ uint32_t l_ivpr_offset;
+ uint32_t l_timeout_in_MS = 100;
+
+ FAPI_IMP(">> stop_gpe_init......");
+
+ FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET,
+ i_target,
+ l_ivpr_offset),
+ "Error getting ATTR_SGPE_BOOT_COPIER_IVPR_OFFSET");
+
+
+ // Program SGPE IVPR
+ l_ivpr.flush<0>().insertFromRight<0, 32>(l_ivpr_offset);
+ FAPI_INF(" Writing IVPR with 0x%16llX", l_ivpr);
+ FAPI_TRY(putScom(i_target, PU_GPE3_GPEIVPR_SCOM, l_ivpr));
+
+ // Program XCR to ACTIVATE SGPE
+ // @todo 146665 Operations to PPEs should use a p9ppe namespace when created
+ l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1, 3);
+ FAPI_TRY(putScom(i_target, PU_GPE3_PPE_XIXCR, l_xcr));
- FAPI_INF("STOP initialization...");
+ // Now wait for SGPE to not be halted and for the HCode to indicate
+ // to be active.
+ l_occ_flag.flush<0>();
+ l_xsr.flush<0>();
+ do
+ {
+ FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCFLG_SCOM, l_occ_flag));
+ FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_xsr));
+ }
+ while((l_occ_flag.getBit<p9hcd::SGPE_ACTIVE>() != 1) &&
+ (l_xsr.getBit<p9hcd::HALTED_STATE>() != 1) &&
+ (--l_timeout_in_MS != 0));
+
+ // @todo 146665 Operations to PPEs should use a p9ppe namespace when created
+ FAPI_ASSERT((l_timeout_in_MS != 0),
+ fapi2::STOP_GPE_INIT_TIMEOUT()
+ .set_OCCFLGSTAT(l_occ_flag)
+ .set_XSR(l_xsr),
+ "STOP GPE Init timeout");
+
+fapi_try_exit:
+ FAPI_IMP("<< stop_gpe_init......");
return fapi2::current_err;
}
@@ -161,9 +238,44 @@ fapi2::ReturnCode stop_gpe_reset(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
- FAPI_INF("STOP reset...");
+ fapi2::buffer<uint64_t> l_data64;
+ uint32_t l_timeout_in_MS = 100;
+
+
+ FAPI_IMP(">> stop_gpe_reset...");
+
+ // Program XCR to HALT SGPE
+ // @todo This should be replace by a call to a common PPE service class
+ // ppe<PPE_TYPE_GPE>gpe3(3);
+ // gpe3.hard_reset();
+ FAPI_INF(" Send HALT command via XCR...");
+ l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3);
+ FAPI_TRY(putScom(i_target, PU_GPE3_PPE_XIXCR, l_data64));
+
+ //Now wait for SGPE to be halted.
+ // @todo This loop should be replace by a call to a common PPE service class
+ // FAPI_TRY(gpe3.is_halted(&b_halted_state, timeout_value_ns, timeout_value_simcycles));
+ FAPI_INF(" Poll for HALT State via XSR...");
+
+ do
+ {
+ FAPI_TRY(getScom(i_target, PU_GPE3_GPEXIXSR_SCOM, l_data64));
+ }
+ while((l_data64.getBit<p9hcd::HALTED_STATE>() == 0) && (--l_timeout_in_MS != 0));
+
+ FAPI_ASSERT((l_timeout_in_MS != 0),
+ fapi2::STOP_GPE_RESET_TIMEOUT()
+ .set_SGPEXSRNOTHALT(l_data64),
+ "STOP GPE Init timeout");
+
+ FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register...");
+ l_data64.setBit<p9hcd::SGPE_ACTIVE>();
+ FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_CLEAR, l_data64));
+fapi_try_exit:
+ FAPI_IMP("<< stop_gpe_reset...");
return fapi2::current_err;
+
}
// -----------------------------------------------------------------------------
@@ -185,5 +297,43 @@ fapi2::ReturnCode stop_corecache_setup(
FAPI_INF("Executing stop_corecache_setup...");
+ // Get all core chiplets
+ auto l_core_functional_vector =
+ i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+ // Get all cache chiplets
+ auto l_cache_functional_vector =
+ i_target.getChildren<fapi2::TARGET_TYPE_EQ>
+ (fapi2::TARGET_STATE_FUNCTIONAL);
+#if 0
+
+ for (auto l_chplt_trgt : l_core_functional_vector)
+ {
+ // @todo RTC 147679 Enable when special wake-up is available
+ // --------------------------------------
+ // Initialize the special wake-up tracking attributes
+ FAPI_INF("\tInitialize the special wake-up tracking attributes for the cores");
+ FAPI_EXEC_HWP(rc, p9_cpu_special_wakeup,
+ l_chplt_trgt,
+ SPCWKUP_INIT,
+ SPW_ALL);
+ } // core chiplet loop
+
+ // Process all cache chiplets
+ for (auto l_chplt_trgt : l_cache_functional_vector)
+ {
+ // @todo RTC 147679 Enable when special wake-up is available
+ // --------------------------------------
+ // Initialize the special wake-up tracking attributes
+ FAPI_INF("\tInitialize the special wake-up tracking attributes for the caches");
+ FAPI_EXEC_HWP(rc, p9_cpu_special_wakeup,
+ l_chplt_trgt,
+ SPCWKUP_INIT,
+ SPW_ALL);
+
+ } // cache chiplet loop
+
+#endif
+
return fapi2::current_err;
}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk
index bfa63033a..c6768289c 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk
@@ -1,13 +1,13 @@
# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
-# $Source: chips/p9/procedures/ipl/hwp/p9_pm_stop_gpe_init.mk $
+# $Source: chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.mk $
#
# IBM CONFIDENTIAL
#
# EKB Project
#
-# COPYRIGHT 2015
+# COPYRIGHT 2015,2016
# [+] International Business Machines Corp.
#
#
@@ -17,4 +17,5 @@
#
# IBM_PROLOG_END_TAG
PROCEDURE=p9_pm_stop_gpe_init
+$(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib)
$(call BUILD_PROCEDURE)
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