diff options
| author | Mark Wenning <wenning@us.ibm.com> | 2013-03-19 09:21:06 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-04-08 11:33:44 -0500 |
| commit | d582f293ca042a34df6d52bfeb41a4fb2d91f62f (patch) | |
| tree | 4ac41dd1b02bf994e71b9d296708301225561cc3 /src | |
| parent | ea5b40c56908934d7f74e90ff9e2da7f7a1460a6 (diff) | |
| download | talos-hostboot-d582f293ca042a34df6d52bfeb41a4fb2d91f62f.tar.gz talos-hostboot-d582f293ca042a34df6d52bfeb41a4fb2d91f62f.zip | |
HWSV ECID Service implementation to support target/attribute infrastructure
Change-Id: I34116aa25f79971eda7dc14b4f56473819ef9c86
RTC: 35557
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3793
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/usr/hwpf/istepreasoncodes.H | 2 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/makefile | 33 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C | 183 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H | 86 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/slave_sbe.C | 67 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/attribute_types.xml | 31 | ||||
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types.xml | 3 |
7 files changed, 374 insertions, 31 deletions
diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H index fa184a9ea..6175a38c7 100644 --- a/src/include/usr/hwpf/istepreasoncodes.H +++ b/src/include/usr/hwpf/istepreasoncodes.H @@ -116,6 +116,7 @@ enum istepModuleId ISTEP_PROC_ABUS_SCOMINIT = 0x44, ISTEP_PROC_DMI_SCOMINIT = 0x45, ISTEP_MEM_PLL_INITF = 0x46, + ISTEP_PROC_GETECID = 0x47, }; /** @@ -173,6 +174,7 @@ enum istepReasonCode ISTEP_PROC_ABUS_SCOMINIT_FAILED = ISTEP_COMP_ID | 0x2C, ISTEP_PROC_SWITCH_CFSIM_FAILED = ISTEP_COMP_ID | 0x2D, ISTEP_LOAD_SLW_FROM_PNOR_FAILED = ISTEP_COMP_ID | 0x2E, + ISTEP_PROC_GETECID_FAILED = ISTEP_COMP_ID | 0x2F, }; // end ISTEP } diff --git a/src/usr/hwpf/hwp/slave_sbe/makefile b/src/usr/hwpf/hwp/slave_sbe/makefile index a405b273e..9d290f33f 100644 --- a/src/usr/hwpf/hwp/slave_sbe/makefile +++ b/src/usr/hwpf/hwp/slave_sbe/makefile @@ -1,25 +1,25 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. # -# $Source: src/usr/hwpf/hwp/slave_sbe/makefile $ +# $Source: src/usr/hwpf/hwp/slave_sbe/makefile $ # -# IBM CONFIDENTIAL +# IBM CONFIDENTIAL # -# COPYRIGHT International Business Machines Corp. 2012 +# COPYRIGHT International Business Machines Corp. 2012,2013 # -# p1 +# p1 # -# Object Code Only (OCO) source materials -# Licensed Internal Code Source Materials -# IBM HostBoot Licensed Internal Code +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code # -# The source code for this program is not published or other- -# wise divested of its trade secrets, irrespective of what has -# been deposited with the U.S. Copyright Office. +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. # -# Origin: 30 +# Origin: 30 # -# IBM_PROLOG_END_TAG +# IBM_PROLOG_END_TAG ROOTPATH = ../../../../.. MODULE = slave_sbe @@ -38,6 +38,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_getecid ## NOTE: add new object files when you add a new HWP @@ -46,11 +47,13 @@ OBJS = slave_sbe.o \ proc_check_slave_sbe_seeprom_complete.o \ proc_extract_sbe_rc.o \ proc_read_seeprom.o \ - proc_sbe_error.o + proc_sbe_error.o \ + proc_getecid.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_getecid include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C new file mode 100644 index 000000000..2c32fedff --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C @@ -0,0 +1,183 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_getecid.C,v 1.8 2013/03/28 17:21:06 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_getecid.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_getecid.C +// *! DESCRIPTION : Get ECID string from target using SCOM +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_getecid.H" + +extern "C" { + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +// HWP entry point +fapi::ReturnCode proc_getecid( + const fapi::Target& i_target, + ecmdDataBufferBase& io_fuseString) +{ + // return code + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0; + uint64_t attr_data[2]; + + // mark HWP entry + FAPI_IMP("Entering ..."); + + io_fuseString.setBitLength(112); // sets size and zeros out buffer + ecmdDataBufferBase otprom_mode_data(64); + ecmdDataBufferBase ecid_data(64); + + do + { + + // + // clear ECC enable before reading ECID data (read-modify-write OTPROM Mode register) + // + + rc = fapiGetScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data); + if (!rc.ok()) + { + FAPI_ERR("fapiGetScom error (OTPC_M_MODE_REGISTER_0x00010008)"); + break; + } + + rc_ecmd |= otprom_mode_data.clearBit(OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%X setting up OTPROM Mode register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiPutScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom error (OTPC_M_MODE_REGISTER_0x00010008)"); + break; + } + + + // + // extract and manipulate ECID data + // + + rc = fapiGetScom(i_target, ECID_PART_0_0x00018000, ecid_data); + if (!rc.ok()) + { + FAPI_ERR("fapiGetScom error (ECID_PART_0_0x00018000)"); + break; + } + + // 0:63 become 63:0 + rc_ecmd |= ecid_data.reverse(); + // copy bits 0:63 from the scom into 0:63 of the fuseString/attribute data + rc_ecmd |= io_fuseString.insert(ecid_data, 0, 64); + attr_data[0] = ecid_data.getDoubleWord(0); + + if (rc_ecmd) + { + FAPI_ERR("Error 0x%X processing ECID (part 0) data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiGetScom(i_target, ECID_PART_1_0x00018001, ecid_data); + if (!rc.ok()) + { + FAPI_ERR("fapiGetScom error (ECID_PART_1_0x00018001)"); + break; + } + + // 0:63 become 63:0 + rc_ecmd |= ecid_data.reverse(); + // copy bits 0:47 from the scom into 64:111 of the fuseString + // all bits into attribute data + rc_ecmd |= io_fuseString.insert(ecid_data, 64, 48); + attr_data[1] = ecid_data.getDoubleWord(0); + + if (rc_ecmd) + { + FAPI_ERR("Error 0x%X processing ECID (part 1) data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // push fuse string into attribute + rc = FAPI_ATTR_SET(ATTR_ECID, + &i_target, + attr_data); + if (!rc.ok()) + { + FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_ECID)"); + break; + } + + // + // restore ECC enable setting + // + + rc_ecmd |= otprom_mode_data.setBit(OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%X setting up OTPROM Mode register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + rc = fapiPutScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data); + if (!rc.ok()) + { + FAPI_ERR("fapiPutScom error (OTPC_M_MODE_REGISTER_0x00010008)"); + break; + } + + } while(0); + + // mark HWP exit + FAPI_IMP("proc_getecid: Exiting ..."); + return rc; +} + +} // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H new file mode 100644 index 000000000..eea32c40d --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H @@ -0,0 +1,86 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_getecid.H,v 1.7 2013/03/28 17:21:10 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_getecid.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_getecid.H +// *! DESCRIPTION : Get ECID string from target using SCOM +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS: +// *! +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_GETECID_H_ +#define _PROC_GETECID_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi.H> +#include "p8_scom_addresses.H" + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_getecid_FP_t)(const fapi::Target&, ecmdDataBufferBase& fuseString); + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// OTPROM mode register field/bit definitions +const uint32_t OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT = 1; + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +// function: FAPI proc_getecid HWP entry point +// parameters: i_target => P8 chip target +// io_fuseString => ecmdDataBuffer which will return ECID data +// (also written to ATTR_ECID) +// returns: FAPI_RC_SUCCESS if successful, else error +fapi::ReturnCode proc_getecid( + const fapi::Target& i_target, + ecmdDataBufferBase& io_fuseString); + +} // extern "C" + +#endif // _PROC_GETECID_H_ diff --git a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C index 820ae8e31..1f13794ba 100644 --- a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C +++ b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C @@ -55,6 +55,7 @@ #include "slave_sbe.H" #include "proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H" #include "proc_check_slave_sbe_seeprom_complete.H" +#include "proc_getecid.H" using namespace ISTEP; using namespace ISTEP_ERROR; @@ -208,7 +209,8 @@ void* call_proc_check_slave_sbe_seeprom_complete( void *io_pArgs ) TARGETING::Target* l_pProcTarget = *l_proc_iter; TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "target HUID %.8X", TARGETING::get_huid(l_pProcTarget)); + "target HUID %.8X", + TARGETING::get_huid(l_pProcTarget)); if ( l_pProcTarget == l_pMasterProcTarget ) { @@ -262,6 +264,69 @@ void* call_proc_check_slave_sbe_seeprom_complete( void *io_pArgs ) } } // endfor + + // Once the sbe's are up correctly, fetch all the proc ECIDs and + // store them in an attribute. + for (TargetHandleList::const_iterator + l_proc_iter = l_procTargetList.begin(); + l_proc_iter != l_procTargetList.end(); + ++l_proc_iter) + { + // make a local copy of the Processor target + TARGETING::Target* l_pProcTarget = *l_proc_iter; + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "target HUID %.8X", + TARGETING::get_huid(l_pProcTarget)); + + fapi::Target l_fapiProcTarget( fapi::TARGET_TYPE_PROC_CHIP, + l_pProcTarget ); + + // proc_getecid should set the fuse string to 112 bits long. + ecmdDataBufferBase l_fuseString; + + // Invoke the HWP + FAPI_INVOKE_HWP(l_errl, + proc_getecid, + l_fapiProcTarget, + l_fuseString ); + + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : proc_getecid", + " failed, returning errorlog" ); + + // capture the target data in the elog + ErrlUserDetailsTarget(l_pProcTarget).addToLog( l_errl ); + + /*@ + * @errortype + * @reasoncode ISTEP_PROC_GETECID_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_GETECID + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_get_ecid failed. + * + */ + l_stepError.addErrorDetails( ISTEP_PROC_GETECID_FAILED, + ISTEP_PROC_GETECID, + l_errl ); + + errlCommit( l_errl, HWPF_COMP_ID ); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_getecid", + " completed ok"); + + } + } // endfor + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_check_slave_sbe_seeprom_complete exit"); diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 2380043aa..206177122 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -2590,7 +2590,7 @@ <!-- DMI deploy lane spares --> <name>MNFG_DMI_DEPLOY_LANE_SPARES</name> <value>0x00004000</value> - </enumerator> + </enumerator> </enumerationType> <!-- Support for pm_hwp_attributes.xml --> @@ -8272,8 +8272,11 @@ bits6:7 will be consumed together to form COARSE_LVL. </description> <attribute> <id>ECID</id> - <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 -Created from running the mss_get_cen_ecid.C</description> + <description> + Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 + Created from running proc_getecid.C for processors + Created from running mss_get_cen_ecid.C for centaurs + </description> <simpleType> <uint64_t> <default>0</default> @@ -9226,11 +9229,11 @@ Measured in GB</description> 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, 0x80, 0x52, 0xC5, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x01, 0xC0, - 0x02, 0x01, 0x4B, 0x17, 0x40, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 0x02, 0x01, 0x4B, 0x17, 0x40, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 </default> </uint8_t> <array>128</array> @@ -9905,7 +9908,7 @@ Measured in GB</description> <attribute> <id>ENABLED_THREADS</id> <description> - Bitmask of threads to enable for each processor, + Bitmask of threads to enable for each processor, Zero means enable all architected threads </description> <simpleType> @@ -10066,7 +10069,7 @@ Measured in GB</description> called MSB Swap where lane 0 of the TX chip wires to lane n-1 on the RX chip where 'n' is the width of the bus. A basic description of this capability is that the board designer can save layers on the board wiring by crossing the wiring between the two chips in a prescribed manner. In a non-MSB Swapped bus Lane 0 on the TX chip wires to lane 0 on the RX chip, lane 1 to lane 1 and so on. - If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or + If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or arbitrary wiring of TX to RX lanes on different chips is NOT ALLOWED. The Master Chip of two connected chips is defined as the chip with the smaller value of (100*Node + Pos). @@ -10076,12 +10079,12 @@ Measured in GB</description> The Downstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Downstream bus is wired msb to lsb etc. and 0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0). - + The Upstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Upstream bus is wired msb to lsb etc. and 0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0). - + It is up to the platform code to set up each ATTR_EI_BUS_TX_MSBSWAP value for the correct target endpoints. - + </description> <simpleType> <uint8_t> @@ -10733,7 +10736,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> - + <attribute> <id>MEMB_TP_BNDY_PLL_FOR_DCCAL_DATA</id> <description>Ring image for Centaur tp_bndy_pll ring diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 205d431c8..3c319b867 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -360,7 +360,7 @@ <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute> <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute> <!-- End Supporting poreve_memory_attributes.xml --> - + </targetType> <targetType> @@ -438,6 +438,7 @@ <attribute><id>PROC_PCIE_REFCLOCK_ENABLE</id></attribute> <attribute><id>PROC_EX_FUNC_L3_DELTA_DATA</id></attribute> <attribute><id>PROC_EX_FUNC_L3_LENGTH</id></attribute> + <attribute><id>ECID</id></attribute> </targetType> <targetType> |

