PCIe max speed support and risk level support in HDAT structures

Change-Id: I6b3e4a5edca007ca08a83bae6f424c9c5402ce07
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37874
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: VENKATESH SAINATH <venkatesh.sainath@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jayashankar Padath <jayashankar.padath@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

4 files changed, 42 insertions, 6 deletions

diff --git a/src/usr/hdat/hdatiohub.C b/src/usr/hdat/hdatiohub.C
index 6b3643670..cf7e40df9 100644
--- a/src/usr/hdat/hdatiohub.C
+++ b/src/usr/hdat/hdatiohub.C
@@ -247,6 +247,8 @@ uint8_t * HdatIoHubFru::setIOHub(uint8_t * io_virt_addr,
     {
         l_hdatHubEntry->hdatIoHubId =
                                   this->iv_hubArray[l_cnt].hdatIoHubId;
+        l_hdatHubEntry->hdatMaxPCIeLinkSpeed = 
+                                  this->iv_hubArray[l_cnt].hdatMaxPCIeLinkSpeed;
         l_hdatHubEntry->hdatModuleId =
                                   this->iv_hubArray[l_cnt].hdatModuleId;
         l_hdatHubEntry->hdatEcLvl =
@@ -735,6 +737,32 @@ errlHndl_t hdatLoadIoData(const hdatMsAddr_t &i_msAddr,
                 HDAT_ERR("Chip is not in Nimbus,Cumulus");
             }
 
+            TARGETING::Target *l_pSysTarget = NULL;
+            (void) TARGETING::targetService().getTopLevelTarget(l_pSysTarget);
+
+            if(l_pSysTarget == NULL)
+            {
+                HDAT_ERR("Error in getting Top Level Target");
+                assert(l_pSysTarget != NULL);
+            }
+
+            // DD1 workaround for Nimbus
+            if((l_procEcLevel & HDAT_PROC_EC_DD1) && (l_model == TARGETING::MODEL_NIMBUS))
+            {
+                if(l_pSysTarget->getAttr<ATTR_DD1_SLOW_PCI_REF_CLOCK>())
+                {
+                    l_hub->hdatMaxPCIeLinkSpeed = HDAT_PCIE_MAX_SPEED_GEN4;
+                }
+                else
+                {
+                    l_hub->hdatMaxPCIeLinkSpeed = HDAT_PCIE_MAX_SPEED_GEN2;
+                }
+            }
+            else
+            {
+                l_hub->hdatMaxPCIeLinkSpeed = HDAT_PCIE_MAX_SPEED_GEN4;
+            }
+
             l_hub->hdatEcLvl = l_procEcLevel;
             l_hub->hdatProcChipID = l_procOrdId;
             l_hub->hdatHardwareTopology = l_pProcTarget->
diff --git a/src/usr/hdat/hdatiohub.H b/src/usr/hdat/hdatiohub.H
index a7b1eb115..642667b85 100755
--- a/src/usr/hdat/hdatiohub.H
+++ b/src/usr/hdat/hdatiohub.H
@@ -53,9 +53,13 @@ namespace HDAT
 #define HDAT_PHB_LANES  96
 #define NUM_BYTES_PER_LANE 2
 #define NUM_LANES_PER_PHB 16
-
+#define HDAT_PROC_EC_DD1 0x10
+#define HDAT_PCIE_MAX_SPEED_GEN1 1
+#define HDAT_PCIE_MAX_SPEED_GEN2 2
+#define HDAT_PCIE_MAX_SPEED_GEN3 3
+#define HDAT_PCIE_MAX_SPEED_GEN4 4
 const uint16_t HDAT_VPD_VERSION = 0x0020;
-const uint16_t HDAT_IO_VERSION = 0x6A;
+const uint16_t HDAT_IO_VERSION = 0x7B;
 
 const uint32_t HDAT_MAX_IO_CHIPS = 10;
 
@@ -96,8 +100,8 @@ struct hdatHubEntry_t
   uint8_t      hdatReserved3;       // 0x000F Reserved
   uint8_t      hdatFab0PresDetect;  // 0x0010 I/O hub chip fabric 0
                                     // presence detect bits
-  uint8_t      hdatReserved4;       // 0x0011 Reserved
-  uint16_t     hdatModuleId;          // 0x0012 Module type Identification
+  uint8_t      hdatMaxPCIeLinkSpeed;// 0x0011 Max PCIe Link Training Speed
+  uint16_t     hdatModuleId;        // 0x0012 Module type Identification
   uint32_t     hdatEcLvl;           // 0x0014 EC level
   uint32_t     hdatReserved5;       // 0x0018 Affinity domain 2
   uint32_t     hdatReserved6;       // 0x001C Affinity Domain 3
@@ -112,7 +116,7 @@ struct hdatHubEntry_t
   uint32_t     hdatMRID;            // 0x0038 MRU ID of Chip
   uint32_t     hdatMemMapVersion;   // 0x003C Memory Map Version
   uint16_t     hdatLaneEqPHBGen3[HDAT_PHB_LANES]; // 0x0040 from PHB0 to PHB5
-  uint16_t     hdatLaneEqPHBGen4[HDAT_PHB_LANES];  //0x0100 Gen4 PHB for PHB 0-5
+  uint16_t     hdatLaneEqPHBGen4[HDAT_PHB_LANES]; // 0x0100 Gen4 PHB for PHB 0-5
 
 
 
diff --git a/src/usr/hdat/hdatiplparms.C b/src/usr/hdat/hdatiplparms.C
index 900dbf07c..f50626b88 100755
--- a/src/usr/hdat/hdatiplparms.C
+++ b/src/usr/hdat/hdatiplparms.C
@@ -460,7 +460,7 @@ static errlHndl_t hdatGetPortInfo(HDAT::hdatHDIFDataArray_t &o_portArrayHdr,
 
     o_portArrayHdr.hdatOffset    = sizeof(HDAT::hdatHDIFDataArray_t);
     o_portArrayHdr.hdatAllocSize = sizeof(hdatPortCodes_t);
-    o_portArrayHdr.hdatActSize   = sizeof(o_ports);
+    o_portArrayHdr.hdatActSize   = sizeof(hdatPortCodes_t);
     o_portArrayHdr.hdatArrayCnt  = 0;
 
     TARGETING::PredicateCTM l_nodePredicate(TARGETING::CLASS_ENC,
@@ -681,6 +681,9 @@ void HdatIplParms::hdatGetSystemParamters()
         HDAT_ERR(" Error in getting attribute PAYLOAD_IN_MIRROR_MEM");
     }
 
+    this->iv_hdatIPLParams->iv_sysParms.hdatSystemAttributes |= 
+          l_pSysTarget->getAttr<ATTR_RISK_LEVEL>() ? HDAT_RISK_LEVEL_ELEVATED : 0 ;
+
     this->iv_hdatIPLParams->iv_sysParms.hdatMemoryScrubbing = 0;
 
     // Get SPPL information
diff --git a/src/usr/hdat/hdatiplparms.H b/src/usr/hdat/hdatiplparms.H
index bdbfeb5db..c490e6bb1 100755
--- a/src/usr/hdat/hdatiplparms.H
+++ b/src/usr/hdat/hdatiplparms.H
@@ -282,6 +282,7 @@ struct hdatPortCodes_t
 #define HDAT_MULT_TPMDS                            0x80000000
 #define HDAT_SMM_ENABLED                           0x40000000
 #define HDAT_CRYPTO_DISABLED_BIT                   0x20000000
+#define HDAT_RISK_LEVEL_ELEVATED                   0x10000000       
 
 #define HDAT_ECO_ENABLED                           0x80000000
 #define HDAT_ECO_CAPABLE                           0x40000000