pnor: fix support for SP/BMC-less SFC init

also fixes up mismatched IDs for macronix flash parts

Change-Id: I81b89e9a7239669e769864711797830b44351bfd
Signed-off-by: Robert Lippert <rlippert@google.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25731
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

4 files changed, 34 insertions, 22 deletions

diff --git a/src/usr/pnor/HBconfig b/src/usr/pnor/HBconfig
index 3b6843b14..fdbd50725 100644
--- a/src/usr/pnor/HBconfig
+++ b/src/usr/pnor/HBconfig
@@ -43,3 +43,9 @@ config PNOR_TWO_SIDE_SUPPORT
     depends on !PNOR_IS_32MB
     help
         This is used to turn on/off two sided pnor support
+
+config PNOR_INIT_FOUR_BYTE_ADDR
+    default n
+    depends on !BMC_DOES_SFC_INIT
+    help
+        PNOR starts out in 3-byte address mode, hostboot must enable 4-byte mode.
diff --git a/src/usr/pnor/norflash.H b/src/usr/pnor/norflash.H
index 864d7cb24..29ac2f8f0 100644
--- a/src/usr/pnor/norflash.H
+++ b/src/usr/pnor/norflash.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
+/* Contributors Listed Below - COPYRIGHT 2014,2016                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
@@ -48,8 +48,8 @@ enum NorChipIDs
     MICRON_NOR_ID     = 0x20ba2000, /**< Micron NOR */
 
     MACRONIX_MFG_ID   = 0xC2000000, /**< Macronix Mfg ID */
-    MACRONIX32_NOR_ID = 0xC2201A00, /**< Macronix NOR MXxxL51235F */
-    MACRONIX64_NOR_ID = 0xC2201900, /**< Macronix NOR MXxxL25635F */
+    MACRONIX64_NOR_ID = 0xC2201A00, /**< Macronix NOR MXxxL51235F */
+    MACRONIX32_NOR_ID = 0xC2201900, /**< Macronix NOR MXxxL25635F */
 
     /* Note: Simics currently models Micron NOR  */
     VPO_NOR_ID        = 0x20201800, /**< VPO NOR chip ID */
diff --git a/src/usr/pnor/pnor_common.C b/src/usr/pnor/pnor_common.C
index 22841b20c..d2c18e3bb 100644
--- a/src/usr/pnor/pnor_common.C
+++ b/src/usr/pnor/pnor_common.C
@@ -6,6 +6,7 @@
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
 /* Contributors Listed Below - COPYRIGHT 2014,2016                        */
+/* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -99,6 +100,13 @@ errlHndl_t  PNOR::mmioToPhysicalOffset(uint64_t& o_hbbAddress)
         l_hbbMMIO    = (l_hbbMMIO >> 32) & PNOR::LPC_TOP_OF_FLASH_OFFSET;
         o_hbbAddress = ((9*l_hbbMMIO) - (9*PNOR::LPC_SFC_MMIO_OFFSET)
                                  - PNOR::PNOR_SIZE) /8;
+
+#ifdef CONFIG_PNOR_INIT_FOUR_BYTE_ADDR
+        // If the PNOR came up in 3-byte mode, then make sure to mask off
+        // the address appropriately.
+        o_hbbAddress &= 0x00ffffffu;
+#endif
+
 #else                      // @FIXME RTC 132398
         o_hbbAddress = 1;  // @FIXME RTC 132398
 #endif
diff --git a/src/usr/pnor/sfc_ibm.C b/src/usr/pnor/sfc_ibm.C
index 3719b7bc7..a13a378f5 100644
--- a/src/usr/pnor/sfc_ibm.C
+++ b/src/usr/pnor/sfc_ibm.C
@@ -594,27 +594,21 @@ errlHndl_t SfcIBM::hwInit( )
             //*** End Micron
 #endif
 
-#ifdef CONFIG_RHESUS
-            // HACK: Micron N25Q256A13 for use with EM100.
-            { 0x20ba1900, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
-            { 0x20ba1900, SFC_REG_CONF5, 4096 },
-#endif
-
 #ifdef CONFIG_ALLOW_MACRONIX_PNOR
             //*** Macronix 512mb chip specific settings.
-            { PNOR::MACRONIX_NOR_ID, SFC_REG_SPICLK,
+            { PNOR::MACRONIX64_NOR_ID, SFC_REG_SPICLK,
             0 << SFC_REG_SPICLK_OUTDLY_SHFT |
             0 << SFC_REG_SPICLK_INSAMPDLY_SHFT |
             0 << SFC_REG_SPICLK_CLKHI_SHFT |
             0 << SFC_REG_SPICLK_CLKLO_SHFT
             },
-            { PNOR::MACRONIX_NOR_ID, SFC_REG_CONF8,
+            { PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF8,
             2 << SFC_REG_CONF8_CSINACTIVEREAD_SHFT |
             8 << SFC_REG_CONF8_DUMMY_SHFT |
             SPI_JEDEC_FAST_READ << SFC_REG_CONF8_READOP_SHFT
             },
-            { PNOR::MACRONIX_NOR_ID, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
-            { PNOR::MACRONIX_NOR_ID, SFC_REG_CONF5, 4096 },
+            { PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF4, SPI_JEDEC_SECTOR_ERASE },
+            { PNOR::MACRONIX64_NOR_ID, SFC_REG_CONF5, 4096 },
             //*** End Macronix
 #endif
         };
@@ -637,15 +631,20 @@ errlHndl_t SfcIBM::hwInit( )
         }
         if( l_err ) { break; }
 
-#if 0   //@fixme-RTC:109860
-        // Enable 4-byte addressing.
-        l_err = SfcErrlFromRc( iv_sfc.set_4ba( &iv_sfc, 1 ) );
-        if( l_err ) { break; }
+#ifdef CONFIG_PNOR_INIT_FOUR_BYTE_ADDR
+        // Enable 4 byte addressing.  This is safe even if 4BA is already
+        // enabled by the BMC/FSP/etc.
+        SfcCmdReg_t sfc_cmd;
+        sfc_cmd.opcode = SFC_OP_START4BA;
+        sfc_cmd.length = 0;
+        l_err = writeReg(SFC_CMD_SPACE,
+                         SFC_REG_CMD,
+                         sfc_cmd.data32);
+        if(l_err) { break; }
 
-        // Re-initialize internal erase size cached value.
-        l_err = SfcErrlFromRc( iv_sfc.get_erase_size(
-                                     &iv_sfc, &iv_eraseSizeBytes, NULL ) );
-        if( l_err ) { break; }
+        //Poll for complete status
+        l_err = pollOpComplete();
+        if(l_err) { break; }
 #endif
 
 #endif //!CONFIG_BMC_DOES_SFC_INIT
@@ -657,7 +656,6 @@ errlHndl_t SfcIBM::hwInit( )
         if(l_err) { break; }
         TRACFCOMP(g_trac_pnor,"iv_eraseSizeBytes=0x%X",iv_eraseSizeBytes);
 
-
 #ifdef CONFIG_ALLOW_MICRON_PNOR
         if( iv_norChipId == PNOR::MICRON_NOR_ID )
         {