HWP: integrate proc_build_smp into Hostboot

RTC: 42153

Change-Id: I2d68a5d3614480e7fc9113c276c5a6b5440f9990
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1836
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

41 files changed, 10137 insertions, 636 deletions

diff --git a/src/usr/hwpf/hwp/L2_L3_attributes.xml b/src/usr/hwpf/hwp/L2_L3_attributes.xml
index 750081ad4..4e47071f7 100644
--- a/src/usr/hwpf/hwp/L2_L3_attributes.xml
+++ b/src/usr/hwpf/hwp/L2_L3_attributes.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/L2_L3_attributes.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/L2_L3_attributes.xml $                       -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!--
     XML file specifying HWPF attributes.
     These are L2/L3 non-platInit attributes associated with proc EX chiplets
@@ -30,7 +30,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L2_R_T0_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L2 tier0 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -39,7 +39,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L2_R_T1_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L2 tier1 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -48,7 +48,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L2_R_T2_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L2 tier2 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -57,7 +57,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L2_FORCE_R_T2_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L2 force tier2 read epsilon protect (all tiers).</description>
     <valueType>uint8</valueType>
     <enum>OFF = 0x00, ON = 0x01</enum>
@@ -67,7 +67,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L2_W_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L2 write epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -76,7 +76,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L3_R_T0_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L3 tier0 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -85,7 +85,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L3_R_T1_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L3 tier1 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -94,7 +94,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L3_R_T2_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L3 tier2 read epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
@@ -103,7 +103,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L3_FORCE_R_T2_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L3 force tier2 read epsilon protect (all tiers).</description>
     <valueType>uint8</valueType>
     <enum>OFF = 0x00, ON = 0x01</enum>
@@ -113,7 +113,7 @@
   <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_L3_W_EPS</id>
-    <targetType>TARGET_TYPE_EX_CHIPLET</targetType>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>L3 write epsilon register value.</description>
     <valueType>uint32</valueType>
     <writeable/>
diff --git a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C
index 60622ea20..760e2b808 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C
@@ -48,20 +48,23 @@
 
 //  targeting support
 #include    <targeting/common/commontargeting.H>
+#include    <targeting/common/utilFilter.H>
 
 //  fapi support
 #include    <fapi.H>
 #include    <fapiPlatHwpInvoker.H>
 
 #include    "activate_powerbus.H"
+#include    <pbusLinkSvc.H>
 
 //  Uncomment these files as they become available:
-// #include    "proc_build_smp/proc_build_smp.H"
+#include    "proc_build_smp/proc_build_smp.H"
 
 namespace   ACTIVATE_POWERBUS
 {
 
 using   namespace   TARGETING;
+using   namespace   EDI_EI_INITIALIZATION;
 using   namespace   fapi;
 
 
@@ -77,38 +80,118 @@ void    call_proc_build_smp( void    *io_pArgs )
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
                "call_proc_build_smp entry" );
 
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
+    // Get all functional proc chip targets
+    TARGETING::TargetHandleList l_cpuTargetList;
+    getAllChips(l_cpuTargetList, TYPE_PROC);
 
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
+    // Collect all valid abus connections and xbus connections
+    TargetPairs_t l_abusConnections;
+    TargetPairs_t l_xbusConnections;
+    l_errl = PbusLinkSvc::getTheInstance().getPbusConnections(
+                                 l_abusConnections, TYPE_ABUS );
+    if (!l_errl)
+    {
+        l_errl = PbusLinkSvc::getTheInstance().getPbusConnections(
+                                 l_xbusConnections, TYPE_XBUS );
+    }
+
+    // Populate l_proc_Chips vector for each good processor chip
+    //   if a A/X-bus endpoint has a valid connection, then
+    //   obtain the proc chip target of the other endpoint of the
+    //   connection, build the fapi target to update the corresponding
+    //   chip object of this A/X-bus endpoint for the procEntry
+    std::vector<proc_build_smp_proc_chip> l_procChips;
 
-    // cast OUR type of target to a FAPI type of target.
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
+    for ( size_t i = 0; (!l_errl) && (i < l_cpuTargetList.size()); i++ )
+    {
+        proc_build_smp_proc_chip l_procEntry;
+
+        l_procEntry.enable_f0  = false;
+        l_procEntry.enable_f1  = false;
+        l_procEntry.f0_node_id = FBC_NODE_ID_0;
+        l_procEntry.f1_node_id = FBC_NODE_ID_0;
+
+        const TARGETING::Target * l_pTarget = l_cpuTargetList[i];
+        fapi::Target l_fapiproc_target( TARGET_TYPE_PROC_CHIP,
+                       reinterpret_cast<void *>
+                       (const_cast<TARGETING::Target*>(l_pTarget)) );
+
+        l_procEntry.this_chip = l_fapiproc_target;
+
+        TARGETING::TargetHandleList l_abuses;
+        getChildChiplets( l_abuses, l_pTarget, TYPE_ABUS );
+
+        for (size_t j = 0; j < l_abuses.size(); j++)
+        {
+            TARGETING::Target * l_target = l_abuses[j];
+            uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>();
+            TargetPairs_t::iterator l_itr = l_abusConnections.find(l_target);
+            if ( l_itr == l_abusConnections.end() )
+            {
+                continue;
+            }
+
+            const TARGETING::Target *l_pParent = NULL;
+            l_pParent = getParentChip(
+                              (const_cast<TARGETING::Target*>(l_itr->second)));
+            fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP,
+                                         (void *)l_pParent );
+
+            switch (l_srcID)
+            {
+                case 0: l_procEntry.a0_chip = l_fapiproc_parent; break;
+                case 1: l_procEntry.a1_chip = l_fapiproc_parent; break;
+                case 2: l_procEntry.a2_chip = l_fapiproc_parent; break;
+               default: break;
+            }
+        }
+
+        TARGETING::TargetHandleList l_xbuses;
+        getChildChiplets( l_xbuses, l_pTarget, TYPE_XBUS );
+
+        for (size_t j = 0; j < l_xbuses.size(); j++)
+        {
+            TARGETING::Target * l_target = l_xbuses[j];
+            uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>();
+            TargetPairs_t::iterator l_itr = l_xbusConnections.find(l_target);
+            if ( l_itr == l_xbusConnections.end() )
+            {
+                continue;
+            }
+
+            const TARGETING::Target *l_pParent = NULL;
+            l_pParent = getParentChip(
+                              (const_cast<TARGETING::Target*>(l_itr->second)));
+            fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP,
+                                         (void *)l_pParent );
+
+            switch (l_srcID)
+            {
+                case 0: l_procEntry.x0_chip = l_fapiproc_parent; break;
+                case 1: l_procEntry.x1_chip = l_fapiproc_parent; break;
+                case 2: l_procEntry.x2_chip = l_fapiproc_parent; break;
+                case 3: l_procEntry.x3_chip = l_fapiproc_parent; break;
+               default: break;
+            }
+        }
+
+        l_procChips.push_back( l_procEntry );
+    }
 
     //  call the HWP with each fapi::Target
-    FAPI_INVOKE_HWP( l_errl, proc_build_smp, _args_...);
+    FAPI_INVOKE_HWP( l_errl, proc_build_smp, 
+                     l_procChips, SMP_ACTIVATE_PHASE1 );
+
     if ( l_errl )
     {
         TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, 
-                  "ERROR : .........." );
-        errlCommit( l_errl, HWPF_COMP_ID );
+                  "ERROR : proc_build_smp" );
     }
     else
     {
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
-                   "SUCCESS : .........." );
+                   "SUCCESS : proc_build_smp" );
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-#endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
                "call_proc_build_smp exit" );
diff --git a/src/usr/hwpf/hwp/activate_powerbus/makefile b/src/usr/hwpf/hwp/activate_powerbus/makefile
index 0cee08a3e..f65cec5d1 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/makefile
+++ b/src/usr/hwpf/hwp/activate_powerbus/makefile
@@ -1,25 +1,25 @@
-#  IBM_PROLOG_BEGIN_TAG
-#  This is an automatically generated prolog.
-#
-#  $Source: src/usr/hwpf/hwp/activate_powerbus/makefile $
-#
-#  IBM CONFIDENTIAL
-#
-#  COPYRIGHT International Business Machines Corp. 2012
-#
-#  p1
-#
-#  Object Code Only (OCO) source materials
-#  Licensed Internal Code Source Materials
-#  IBM HostBoot Licensed Internal Code
-#
-#  The source code for this program is not published or other-
-#  wise divested of its trade secrets, irrespective of what has
-#  been deposited with the U.S. Copyright Office.
-#
-#  Origin: 30
-#
-#  IBM_PROLOG_END
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+# 
+# $Source: src/usr/hwpf/hwp/activate_powerbus/makefile $
+# 
+# IBM CONFIDENTIAL
+# 
+# COPYRIGHT International Business Machines Corp. 2012
+# 
+# p1
+# 
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+# 
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+# 
+# Origin: 30
+# 
+# IBM_PROLOG_END_TAG 
 
 ROOTPATH = ../../../../..
 
@@ -33,6 +33,9 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 
 ## pointer to common HWP files
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid
 
 ##  NOTE: add the base istep dir here. 
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus
@@ -41,15 +44,19 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus
 ##  NOTE: add a new EXTRAINCDIR when you add a new HWP
 ##  EXAMPLE:
 ##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/<HWP_dir>
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp
 
 
 ##  NOTE: add new object files when you add a new HWP
-OBJS =  activate_powerbus.o
-
+OBJS =  activate_powerbus.o \
+        proc_build_smp.o proc_build_smp_adu.o proc_build_smp_epsilon.o \
+        proc_build_smp_fbc_ab.o proc_build_smp_fbc_cd.o \
+        proc_build_smp_fbc_nohp.o proc_adu_utils.o
         
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ##  EXAMPLE:
 #   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/<HWP_dir>
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp
 
 
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C
new file mode 100644
index 000000000..23682da3e
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C
@@ -0,0 +1,735 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_adu_utils.C,v 1.6 2012/08/21 05:16:27 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_adu_utils.C
+// *! DESCRIPTION : ADU library functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Jeshua Smith  Email: jeshua@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_adu_utils.H"
+
+extern "C"
+{
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+fapi::ReturnCode proc_adu_utils_get_adu_lock_id(
+    const fapi::Target& i_target,
+    uint8_t& o_lock_id)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase data(64);
+    uint8_t lock_id;
+
+    FAPI_DBG("proc_adu_utils_get_adu_lock_id: End");
+
+    do
+    {
+        // read ADU Command register
+        FAPI_DBG("proc_adu_utils_get_adu_lock_id: Reading ADU Command register to retreive lock ID");
+        rc = fapiGetScom(i_target, ADU_COMMAND_0x02020001, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_manage_adu_lock: fapiGetScom error (ADU_COMMAND_0x02020001)");
+            break;
+        }
+
+        // extract lock ID field
+        rc_ecmd |= data.extractToRight(&lock_id,
+                                       ADU_COMMAND_LOCK_ID_START_BIT,
+                                       (ADU_COMMAND_LOCK_ID_END_BIT-
+                                        ADU_COMMAND_LOCK_ID_START_BIT)+1);
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_get_adu_lock_id: Error 0x%x extracting lock id from data buffer",
+                     rc_ecmd);
+            break;
+        }
+        o_lock_id = lock_id & ADU_COMMAND_LOCK_ID_MAX_VALUE;
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_get_adu_lock_id: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_clear_adu_auto_inc(
+    const fapi::Target& i_target)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase data(64);
+
+    FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Start");
+
+    do
+    {
+        // retreive ADU Command register
+        FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Reading ADU Command register");
+        rc = fapiGetScom(i_target, ADU_COMMAND_0x02020001, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: fapiGetScom error (ADU_COMMAND_0x02020001)");
+            break;
+        }
+
+        // clear auto-increment bit
+        rc_ecmd |= data.clearBit(ADU_COMMAND_AUTO_INC_BIT);
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: Error 0x%x forming auto-increment clear data buffer",
+                     rc_ecmd);
+            break;
+        }
+
+        // write ADU Command register
+        FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Writing ADU Command register");
+        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: fapiPutScom error (ADU_COMMAND_0x02020001)");
+            break;
+        }
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_manage_adu_lock(
+    const fapi::Target& i_target,
+    const proc_adu_utils_adu_lock_operation& i_lock_operation,
+    const uint32_t& i_num_attempts)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase lock_control(64);
+    uint32_t attempt_count = 1;
+
+    FAPI_DBG("proc_adu_utils_manage_adu_lock: Start");
+
+    do
+    {
+        // validate input parameters
+        if (i_num_attempts == 0)
+        {
+            FAPI_ERR("proc_adu_utils_manage_adu_lock: Invalid value %d for number of lock manipulation attempts",
+                     i_num_attempts);
+            const uint64_t & ARGS = i_num_attempts;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_ARGS);
+            break;
+        }
+
+        // set up data buffer to perform desired lock manipulation operation
+        if (i_lock_operation == ADU_LOCK_ACQUIRE)
+        {
+            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock acquisition");
+            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCKED_BIT);
+        }
+        else if (i_lock_operation == ADU_LOCK_FORCE_ACQUIRE)
+        {
+            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock acquisition/pick");
+            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCKED_BIT);
+            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCK_PICK_BIT);
+        }
+        else if (i_lock_operation == ADU_LOCK_RELEASE)
+        {
+            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock release");
+        }
+        else
+        {
+            FAPI_ERR("proc_adu_utils_manage_adu_lock: Internal error (unsupported lock operation enum value %d)",
+                     i_lock_operation);
+            const uint64_t & ERR_DATA = i_lock_operation;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INTERNAL_ERR);
+            break;
+        }
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_manage_adu_lock: Error 0x%x setting up lock manipulation control data buffer",
+                     rc_ecmd);
+            break;
+        }
+
+        // perform lock management operation
+        while (1)
+        {
+            // write ADU command register to attempt lock manipulation
+            FAPI_DBG("proc_adu_utils_manage_adu_lock: Writing ADU Command register to attempt lock manipulation");
+            rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, lock_control);
+            // pass back return code to caller unless it specifically indicates
+            // that the ADU lock manipulation was unsuccessful and we're going
+            // to try again
+            if ((rc != fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED) ||
+                (attempt_count == i_num_attempts))
+            {
+                // rc does not indicate success
+                if (!rc.ok())
+                {
+                    // rc does not indicate lock held, exit
+                    if (rc != fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
+                    {
+                        FAPI_ERR("proc_adu_utils_manage_adu_lock: fapiPutScom error (ADU_COMMAND_0x02020001)");
+                        break;
+                    }
+                    // rc indicates lock held, out of attempts
+                    if (attempt_count == i_num_attempts)
+                    {
+                        FAPI_ERR("proc_adu_utils_manage_adu_lock: Desired ADU lock manipulation was not successful after %d attempts",
+                                 i_num_attempts);
+                        break;
+                    }
+                }
+                // rc clean, lock management operation successful
+                FAPI_DBG("proc_adu_utils_manage_adu_lock: Lock manipulation successful");
+                break;
+            }
+
+            // delay to provide time for ADU lock to be released
+            rc = fapiDelay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
+                           PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_manage_adu_lock: fapiDelay error");
+                break;
+            }
+
+            // increment attempt count, loop again
+            attempt_count++;
+            FAPI_DBG("proc_adu_utils_manage_adu_lock: Attempt %d of %d",
+                     attempt_count, i_num_attempts);
+        }
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_manage_adu_lock: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_reset_adu(
+    const fapi::Target& i_target)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase data(64);
+
+    FAPI_DBG("proc_adu_utils_reset_adu: Start");
+
+    do
+    {
+        // assert status clear & state machine bits
+        // leave lock bit asserted
+        FAPI_DBG("proc_adu_utils_reset_adu: Writing ADU Command register to reset ADU");
+        rc_ecmd |= data.setBit(ADU_COMMAND_CLEAR_STATUS_BIT);
+        rc_ecmd |= data.setBit(ADU_COMMAND_RESET_BIT);
+        rc_ecmd |= data.setBit(ADU_COMMAND_LOCKED_BIT);
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_reset_adu: Error 0x%x setting up reset control data buffer",
+                     rc_ecmd);
+            break;
+        }
+
+        // write ADU Command register
+        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_reset_adu: fapiPutScom error (ADU_COMMAND_0x02020001)");
+            break;
+        }
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_reset_adu: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_send_fbc_op(
+    const fapi::Target& i_target,
+    const proc_adu_utils_fbc_op& i_adu_ctl,
+    const bool& i_use_hp,
+    const proc_adu_utils_fbc_op_hp_ctl& i_adu_hp_ctl)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase pmisc_data(64), pmisc_mask(64);
+    ecmdDataBufferBase ctl_data(64);
+    ecmdDataBufferBase cmd_data(64);
+    uint8_t struct_data_to_insert;
+
+    FAPI_DBG("proc_adu_utils_send_fbc_op: Start");
+
+    do
+    {
+        // validate input parameters
+        if (i_adu_ctl.address > PROC_FBC_UTILS_FBC_MAX_ADDRESS)
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %016llX specified for fabric address argument",
+                     i_adu_ctl.address);
+            const uint64_t & ARGS = i_adu_ctl.address;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_ARGS);
+            break;
+        }
+        if (i_use_hp &&
+            (i_adu_hp_ctl.post_quiesce_delay >
+             PROC_ADU_UTILS_ADU_MAX_POST_QUIESCE_DELAY))
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %d specified for hotplug post-quiesce delay argument",
+                     i_adu_hp_ctl.post_quiesce_delay);
+            const uint64_t & ARGS = i_adu_hp_ctl.post_quiesce_delay;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_ARGS);
+            break;
+        }
+        if (i_use_hp &&
+            (i_adu_hp_ctl.pre_init_delay >
+             PROC_ADU_UTILS_ADU_MAX_PRE_INIT_DELAY))
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %d specified for hotplug pre-init delay argument",
+                     i_adu_hp_ctl.pre_init_delay);
+            const uint64_t & ARGS = i_adu_hp_ctl.pre_init_delay;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_ARGS);
+            break;
+        }
+
+
+        // build ADU pMisc Mode register content
+        if (i_use_hp)
+        {
+            FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU pMisc Mode register");
+            // switch AB bit
+            rc_ecmd |= pmisc_data.writeBit(
+                ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT,
+                i_adu_hp_ctl.do_switch_ab);
+            rc_ecmd |= pmisc_mask.setBit(
+                ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT);
+            // switch CD bit
+            rc_ecmd |= pmisc_data.writeBit(
+                ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT,
+                i_adu_hp_ctl.do_switch_cd);
+            rc_ecmd |= pmisc_mask.setBit(
+                ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT);
+            rc.setEcmdError(rc_ecmd);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x setting up ADU pMisc Mode register data buffer",
+                         rc_ecmd);
+                break;
+            }
+            // write ADU pMisc Mode register content
+            rc = fapiPutScomUnderMask(i_target,
+                                      ADU_PMISC_MODE_0x0202000B,
+                                      pmisc_data,
+                                      pmisc_mask);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutUnderMask error (ADU_PMISC_MODE_0x0202000B)");
+                break;
+            }
+        }
+
+        // build ADU Control register content
+        FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU Control register");
+        // ttype field
+        struct_data_to_insert = i_adu_ctl.ttype;
+        rc_ecmd |= ctl_data.insertFromRight(
+            &struct_data_to_insert,
+            ADU_CONTROL_FBC_TTYPE_START_BIT,
+            (ADU_CONTROL_FBC_TTYPE_END_BIT-
+             ADU_CONTROL_FBC_TTYPE_START_BIT+1));
+        // read/write bit
+        if (i_adu_ctl.cmd_type == ADU_FBC_OP_CMD_RD_ADDR_DATA)
+        {
+            rc_ecmd |= ctl_data.setBit(ADU_CONTROL_FBC_RNW_BIT);
+        }
+        // tsize field
+        struct_data_to_insert = i_adu_ctl.tsize;
+        rc_ecmd |= ctl_data.insertFromRight(
+            &struct_data_to_insert,
+            ADU_CONTROL_FBC_TSIZE_START_BIT,
+            (ADU_CONTROL_FBC_TSIZE_END_BIT-
+             ADU_CONTROL_FBC_TSIZE_START_BIT+1));
+        // address field
+        rc_ecmd |= ctl_data.insertFromRight((uint32_t)
+            (i_adu_ctl.address >>
+             ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT),
+            ADU_CONTROL_FBC_ADDRESS_START_BIT,
+            (ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT-1-
+             ADU_CONTROL_FBC_ADDRESS_START_BIT+1));
+        rc_ecmd |= ctl_data.insertFromRight((uint32_t)
+            (i_adu_ctl.address &
+             ADU_CONTROL_FBC_ADDRESS_SPLIT_MASK),
+            ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT,
+            (ADU_CONTROL_FBC_ADDRESS_END_BIT-
+             ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT+1));
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x setting up ADU Control register data buffer",
+                     rc_ecmd);
+            break;
+        }
+        // write ADU Control register content
+        rc = fapiPutScom(i_target, ADU_CONTROL_0x02020000, ctl_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutScom error (ADU_CONTROL_0x02020000)");
+            break;
+        }
+
+        // build ADU Command register content
+        FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU Command register");
+        // start operation bit
+        rc_ecmd |= cmd_data.setBit(ADU_COMMAND_START_OP_BIT);
+        // address only bit
+        if (i_adu_ctl.cmd_type == ADU_FBC_OP_CMD_ADDR_ONLY)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_ADDRESS_ONLY_BIT);
+        }
+        // lock bit
+        rc_ecmd |= cmd_data.setBit(ADU_COMMAND_LOCKED_BIT);
+        // scope field
+        struct_data_to_insert = i_adu_ctl.scope;
+        rc_ecmd |= cmd_data.insertFromRight(
+            &struct_data_to_insert,
+            ADU_COMMAND_FBC_SCOPE_START_BIT,
+            (ADU_COMMAND_FBC_SCOPE_END_BIT-
+             ADU_COMMAND_FBC_SCOPE_START_BIT+1));
+        // auto-increment bit
+        if (i_adu_ctl.use_autoinc)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_AUTO_INC_BIT);
+        }
+        // drop priority
+        struct_data_to_insert = i_adu_ctl.drop_priority;
+        rc_ecmd |= cmd_data.insertFromRight(
+            &struct_data_to_insert,
+            ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT,
+            (ADU_COMMAND_FBC_DROP_PRIORITY_END_BIT-
+             ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT+1));
+        // fabric init policy controls
+        if (i_adu_ctl.init_policy == ADU_FBC_OP_FBC_INIT_OVERRIDE)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_INIT_OVERRIDE_BIT);
+        }
+        else if (i_adu_ctl.init_policy == ADU_FBC_OP_FBC_INIT_WAIT_LOW)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_INIT_WAIT_LOW_BIT);
+        }
+        // perform token manager quiesce?
+        if (i_use_hp && i_adu_hp_ctl.do_tm_quiesce)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_TM_QUIESCE_BIT);
+        }
+        // send fabric queisce command before programmed command?
+        // set cycle delay to apply after quiesce before programmed command
+        if (i_use_hp && i_adu_hp_ctl.do_pre_quiesce)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_PRE_QUIESCE_BIT);
+            rc_ecmd |= cmd_data.insertFromRight(
+                &i_adu_hp_ctl.post_quiesce_delay,
+                ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT,
+                (ADU_COMMAND_FBC_POST_QUIESCE_COUNT_END_BIT-
+                 ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT+1));
+        }
+        // send fabric init command after programmed command?
+        // set cycle delay to apply after programmed command before init
+        if (i_use_hp && i_adu_hp_ctl.do_post_init)
+        {
+            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_POST_INIT_BIT);
+            rc_ecmd |= cmd_data.insertFromRight(
+                &i_adu_hp_ctl.pre_init_delay,
+                ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT,
+                (ADU_COMMAND_FBC_PRE_INIT_COUNT_END_BIT-
+                 ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT+1));
+        }
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x forming data buffer",
+                     rc_ecmd);
+            break;
+        }
+
+        // write ADU Command register content
+        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, cmd_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutScom error (ADU_COMMAND_0x02020000)");
+            break;
+        }
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_send_fbc_op: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_get_adu_status(
+    const fapi::Target& i_target,
+    proc_adu_utils_adu_status& o_status_act)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase status_data(64);
+
+    FAPI_DBG("proc_adu_utils_check_adu_status: Start");
+
+    do
+    {
+        // read ADU Status register
+        FAPI_DBG("proc_adu_utils_check_adu_status: Reading ADU Status register");
+        rc = fapiGetScom(i_target, ADU_STATUS_0x02020002, status_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_check_adu_status: fapiGetScom error (ADU_STATUS_0x02020002)");
+            break;
+        }
+
+        // fill actual structure
+        o_status_act.busy =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_BUSY_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.wait_cmd_arbit =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_WAIT_CMD_ARBIT_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.addr_done =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_ADDR_DONE_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.data_done =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_DATA_DONE_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.wait_resp =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_WAIT_RESP_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.overrun_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_OVERRUN_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.autoinc_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_AUTOINC_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.command_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_COMMAND_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.address_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_ADDRESS_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.command_hang_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_COMMAND_HANG_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.data_hang_err =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_DATA_HANG_ERR_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+        o_status_act.pbinit_missing =
+            status_data.isBitSet(ADU_STATUS_FBC_ALTD_INIT_MISSING_BIT) ?
+            ADU_STATUS_BIT_SET :
+            ADU_STATUS_BIT_CLEAR;
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_check_adu_status: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_set_adu_data_registers(
+    const fapi::Target& i_target,
+    const uint64_t& i_write_data,
+    const bool& i_override_itag,
+    const bool& i_write_itag,
+    const bool& i_override_ecc,
+    const uint8_t& i_write_ecc)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase ecc_data(64);
+
+    FAPI_DBG("proc_adu_utils_set_adu_data_registers: Start");
+
+    do
+    {
+        // write ADU Force ECC Register first if directed
+        // this ordering is required to fully support auto-increment mode
+        if (i_override_itag ||
+            i_override_ecc)
+        {
+            FAPI_DBG("proc_adu_utils_set_adu_data_registers: Writing ADU Force ECC register");
+            if (i_override_itag)
+            {
+                rc_ecmd |= ecc_data.setBit(ADU_FORCE_ECC_DATA_ITAG_BIT);
+            }
+            if (i_override_ecc)
+            {
+                // set ECC override bit, duplicate override ECC
+                rc_ecmd |= ecc_data.setBit(ADU_FORCE_ECC_DATA_TX_ECC_OVERWRITE_BIT);
+                rc_ecmd |= ecc_data.insertFromRight(
+                    i_write_ecc,
+                    ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT,
+                    ADU_FORCE_ECC_DATA_TX_ECC_HI_END_BIT-
+                    ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT+1);
+                rc_ecmd |= ecc_data.insertFromRight(
+                    i_write_ecc,
+                    ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT,
+                    ADU_FORCE_ECC_DATA_TX_ECC_LO_END_BIT-
+                    ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT+1);
+            }
+            rc.setEcmdError(rc_ecmd);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_set_adu_data_registers: Error 0x%x forming override ECC data buffer",
+                         rc_ecmd);
+                break;
+            }
+
+            // write ADU Force ECC register
+            rc = fapiPutScom(i_target, ADU_FORCE_ECC_0x02020010, ecc_data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_set_adu_data_registers: fapiPutScom error (ADU_FORCE_ECC_0x02020010)");
+                break;
+            }
+        }
+
+        // write ADU Data register
+        // this will generate new command in auto-increment mode
+        FAPI_DBG("proc_adu_utils_set_adu_data_registers: Writing ADU Data register");
+        rc_ecmd |= data.insertFromRight((uint32_t)
+            (i_write_data >> ADU_DATA_SPLIT_BIT),
+            ADU_DATA_START_BIT,
+            (ADU_DATA_SPLIT_BIT-1-
+             ADU_DATA_START_BIT+1));
+        rc_ecmd |= data.insertFromRight((uint32_t)
+            (i_write_data & ADU_DATA_SPLIT_MASK),
+            ADU_DATA_SPLIT_BIT,
+            (ADU_DATA_END_BIT-
+             ADU_DATA_SPLIT_BIT+1));
+        rc.setEcmdError(rc_ecmd);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_set_adu_data_registers: Error 0x%x forming data buffer",
+                     rc_ecmd);
+            break;
+        }
+
+        // write ADU Data register
+        rc = fapiPutScom(i_target, ADU_DATA_0x02020003, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_set_adu_data_registers: fapiPutScom error (ADU_DATA_0x02020003)");
+            break;
+        }
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_set_adu_data_registers: End");
+    return rc;
+}
+
+
+fapi::ReturnCode proc_adu_utils_get_adu_data_registers(
+    const fapi::Target& i_target,
+    const bool& i_get_itag,
+    uint64_t& o_read_data,
+    bool& o_read_itag)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase ecc_data(64);
+
+    FAPI_DBG("proc_adu_utils_get_adu_data_registers: Start");
+
+    do
+    {
+        // read ADU Force ECC Register first if directed
+        // this ordering is required to fully support auto-increment mode
+        if (i_get_itag)
+        {
+            // read ADU Force ECC register
+            FAPI_DBG("proc_adu_utils_get_adu_data_registers: Reading ADU Force ECC register");
+            rc = fapiGetScom(i_target, ADU_FORCE_ECC_0x02020010, ecc_data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_adu_utils_get_adu_data_registers: fapiGetScom error (ADU_FORCE_ECC_0x02020010)");
+                break;
+            }
+            o_read_itag = ecc_data.isBitSet(ADU_FORCE_ECC_DATA_ITAG_BIT);
+        }
+
+        // read ADU Data register
+        // this will generate new command in auto-increment mode
+        FAPI_DBG("proc_adu_utils_get_adu_data_registers: Reading ADU Data register");
+        rc = fapiGetScom(i_target, ADU_DATA_0x02020003, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_adu_utils_get_adu_data_registers: fapiGetScom error (ADU_DATA_0x02020003)");
+            break;
+        }
+        o_read_data = data.getDoubleWord(0);
+
+    } while(0);
+
+    FAPI_DBG("proc_adu_utils_get_adu_data_registers: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H
new file mode 100644
index 000000000..3f9ce139f
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H
@@ -0,0 +1,519 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_adu_utils.H,v 1.4 2012/08/21 05:16:30 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_adu_utils.H
+// *! DESCRIPTION : ADU library functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *! BACKUP NAME : Jeshua Smith  Email: jeshua@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+// *! The functions contained in this library provide a mechanism to issue
+// *! fabric commands from the P8 Alter Display Unit (ADU).
+// *!
+// *! To perform a read operation on the fabric:
+// *!   o Obtain lock protecting ADU resources:
+// *!         proc_adu_utils_manage_adu_lock()
+// *!   o Clear ADU Status registers, reset ADU state machine:
+// *!         proc_adu_utils_reset_adu()
+// *!   o Program fabric command/address into ADU control logic & issue command
+// *!         proc_adu_utils_send_fbc_op()
+// *!   o Poll ADU status bits to ensure read data has arrived:
+// *!         proc_adu_utils_get_adu_status()
+// *!   o Read ADU data registers to retrieve data:
+// *!         proc_adu_utils_get_adu_data_registers()
+// *!   o Clear ADU lock:
+// *!         proc_adu_utils_manage_adu_lock()
+// *!
+// *! To perform a write operation on the fabric:
+// *!   o Obtain lock protecting ADU resources:
+// *!         proc_adu_utils_manage_adu_lock()
+// *!   o Clear ADU Status registers, reset ADU state machine:
+// *!         proc_adu_utils_reset_adu()
+// *!   o Write ADU data registers to set data to be written:
+// *!         proc_adu_utils_set_adu_data_registers()
+// *!   o Program fabric command/address into ADU control logic & issue command
+// *!         proc_adu_utils_send_fbc_op()
+// *!   o Poll ADU status bits to ensure read data has arrived:
+// *!         proc_adu_utils_get_adu_status()
+// *!   o Clear ADU lock:
+// *!         proc_adu_utils_manage_adu_lock()
+// *!
+// *! Additional functions are provided to:
+// *!   o Check ADU lock owner:
+// *!         proc_adu_utils_get_adu_lock_id()
+// *!   o Manage ADU auto-increment function
+// *!         proc_adu_utils_clear_adu_auto_inc()
+// *!
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//
+// TODO:
+//   o check if ADU data register read fails when locked?
+//     if not seems stray read operation can increment pointer?
+//
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_ADU_UTILS_H_
+#define _PROC_ADU_UTILS_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "proc_fbc_utils.H"
+#include "p8_scom_addresses.H"
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// ADU status bit comparison constants
+enum proc_adu_utils_status_bit
+{
+    ADU_STATUS_BIT_CLEAR = 0,    // status bit is clear (=0)
+    ADU_STATUS_BIT_SET = 1,      // status bit is set (=1)
+    ADU_STATUS_BIT_DONT_CARE = 2 // status bit is a don't care (=0 or =1)
+};
+
+// ADU fabric operation type
+enum proc_adu_utils_fbc_op_type
+{
+    ADU_FBC_OP_CMD_RD_ADDR_DATA = 0, // read command, address & data phase
+    ADU_FBC_OP_CMD_ADDR_ONLY = 1,    // address phase only
+    ADU_FBC_OP_CMD_WR_ADDR_DATA = 2  // write command, address & data phase
+};
+
+// ADU fabric init command issue policy control
+enum proc_adu_utils_fbc_init_policy
+{
+    ADU_FBC_OP_FBC_INIT_NO_OVERRIDE = 0x0, // don't issue command if fabric
+                                           // init line is low
+    ADU_FBC_OP_FBC_INIT_OVERRIDE = 0x1,    // issue command even if fabric
+                                           // init line is low
+    ADU_FBC_OP_FBC_INIT_WAIT_LOW = 0x2     // wait until fabric init line is
+                                           // low to issue command
+};
+
+// ADU supported fabric ttypes
+enum proc_adu_utils_fbc_ttype
+{
+    ADU_FBC_OP_TTYPE_PBOP = 0x3F,     // PB operation
+    ADU_FBC_OP_TTYPE_PMISC = 0x31,    // pervasive misc
+    ADU_FBC_OP_TTYPE_CI_PR_W = 0x37,  // cache-inhibited partial write
+    ADU_FBC_OP_TTYPE_DMA_PR_W = 0x26, // DMA partial write
+    ADU_FBC_OP_TTYPE_CI_PR_RD = 0x34, // cache-inhibited partial read
+    ADU_FBC_OP_TTYPE_DMA_PR_RD = 0x35 // DMA partial read
+};
+
+// ADU supported fabric tsize encodings
+enum proc_adu_utils_fbc_tsize
+{
+    ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN = 0x08,   // pbop disable_all
+                                                  // (dis command, dis data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_PBOP_EN_RCMD_FP_EN = 0x09,   // pbop enable_rcmd_only
+                                                  // (en command, dis data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_PBOP_EN_DATA_FP_EN = 0x0A,   // pbop enable_data_only
+                                                  // (dis command, en data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_PBOP_EN_ALL_FP_EN = 0x0B,    // pbop enable_all
+                                                  // (en command, en data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_DIS = 0x00,  // pbop disable_all
+                                                  // (dis command, dis data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_PBOP_EN_RCMD_FP_DIS = 0x01,  // pbop enable_rcmd_only
+                                                  // (en command, dis data)
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_PBOP_EN_DATA_FP_DIS = 0x02,  // pbop enable_data_only
+                                                  // (dis command, en data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_PBOP_EN_ALL_FP_DIS = 0x03,   // pbop enable_all
+                                                  // (en command, en data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_FPBOP_DIS_ALL_FP_EN = 0x48,  // fpbop disable_all
+                                                  // (dis command, dis data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_RCMD_FP_EN = 0x49,  // fpbop enable_rcmd_only
+                                                  // (en command, dis data)
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_DATA_FP_EN = 0x4A,  // fpbop enable_data_only
+                                                  // (dis command, en data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_ALL_FP_EN = 0x4B,   // fpbop enable_all
+                                                  // (en command, en data),
+                                                  // MC fast-path enable
+    ADU_FBC_OP_TSIZE_FPBOP_DIS_ALL_FP_DIS = 0x40, // fpbop disable_all
+                                                  // (dis command, dis data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_RCMD_FP_DIS = 0x41, // fpbop enable_rcmd_only
+                                                  // (en command, dis data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_DATA_FP_DIS = 0x42, // fpbop enable_data_only
+                                                  // (dis command, en data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_FPBOP_EN_ALL_FP_DIS  = 0x43, // fpbop enable_all
+                                                  // (en command, en data),
+                                                  // MC fast-path disable
+    ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB = 0x01,      // pervasive misc switch AB
+    ADU_FBC_OP_TSIZE_1B = 0x01,                   // one byte transfer size
+    ADU_FBC_OP_TSIZE_2B = 0x02,                   // two byte transfer size
+    ADU_FBC_OP_TSIZE_3B = 0x03,                   // three byte transfer size
+    ADU_FBC_OP_TSIZE_4B = 0x04,                   // four byte transfer size
+    ADU_FBC_OP_TSIZE_8B = 0x08                    // eight byte transfer size
+};
+
+
+// ADU supported fabric priority encodings
+enum proc_adu_utils_fbc_drop_priority
+{
+    ADU_FBC_OP_DROP_PRIORITY_LOW = 0x0, // lowest priority command request
+                                        // (highest issue rate, first to be
+                                        // dropped)
+    ADU_FBC_OP_DROP_PRIORITY_MED = 0x1, // medium priority command request
+                                        // (next highest issue rate, can be
+                                        // dropped after low priority commands)
+    ADU_FBC_OP_DROP_PRIORITY_HIGH = 0x2 // high priority command request
+                                        // (slowest issue rate, can only be
+                                        // dropped after low & medium priority
+                                        // commands)
+};
+
+// ADU suppored fabric scope encodings
+enum proc_adu_utils_fbc_scope
+{
+    ADU_FBC_OP_SCOPE_NODAL = 0x0,         // nodal scope, physical broadcast to
+                                          // all units on local chip
+    ADU_FBC_OP_SCOPE_GROUP = 0x1,         // group scope, physical broadcast to
+                                          // all units on local physical group
+    ADU_FBC_OP_SCOPE_SYSTEM = 0x2,        // system scope, physical broadcast to
+                                          // all units in SMP
+    ADU_FBC_OP_SCOPE_REMOTE_GROUP = 0x3,  // remote group scope, physical
+                                          // broadcast to all units in remote
+                                          // group
+    ADU_FBC_OP_SCOPE_FOREIGN_LINK0 = 0x4, // foreign scope, physical broadcast
+                                          // is all units on the local chip on
+                                          // local SMP and remote chip on
+                                          // remote SMP (foreign link ID 0)
+    ADU_FBC_OP_SCOPE_FOREIGN_LINK1 = 0x5, // foreign scope, physical broadcast
+                                          // is all units on the local chip on
+                                          // local SMP and remote chip on
+                                          // remote SMP (foreign link ID 1)
+    ADU_FBC_OP_SCOPE_FOREIGN_LINK2 = 0x6, // foreign scope, physical broadcast
+                                          // is all units on the local chip on
+                                          // local SMP and remote chip on
+                                          // remote SMP (foreign link ID 2)
+    ADU_FBC_OP_SCOPE_FOREIGN_LINK3 = 0x7  // foreign scope, physical broadcast
+                                          // is all units on the local chip on
+                                          // local SMP and remote chip on
+                                          // remote SMP (foreign link ID 3)
+};
+
+// ADU lock operations
+enum proc_adu_utils_adu_lock_operation
+{
+    ADU_LOCK_ACQUIRE,       // acquire lock
+    ADU_LOCK_FORCE_ACQUIRE, // acquire lock (with lock pick)
+    ADU_LOCK_RELEASE        // release lock
+};
+
+// ADU fabric operation control information
+struct proc_adu_utils_fbc_op {
+    proc_adu_utils_fbc_ttype ttype;                 // fabric ttype
+    proc_adu_utils_fbc_tsize tsize;                 // fabric tsize
+    uint64_t address;                               // fabric address
+    proc_adu_utils_fbc_scope scope;                 // fabric scope
+    proc_adu_utils_fbc_drop_priority drop_priority; // fabric drop priority
+    proc_adu_utils_fbc_op_type cmd_type;            // command type
+    proc_adu_utils_fbc_init_policy init_policy;     // fabric init issue policy
+    bool use_autoinc;                               // use ADU auto-increment?
+};
+
+// ADU fabric hotplug operation control information
+struct proc_adu_utils_fbc_op_hp_ctl {
+    bool do_tm_quiesce;          // quiesce fabric token manager prior to
+                                 // issuing programmed command?
+    bool do_pre_quiesce;         // send fabric quiesce command prior to
+                                 // issuing programmed command?
+    bool do_post_init;           // send fabric init command after issuing
+                                 // programmed command
+    uint32_t post_quiesce_delay; // cycle delay to pause after pre-quiesce
+                                 // command (clean cresp) before issuing
+                                 // programmed command
+    uint32_t pre_init_delay;     // cycle delay to pause after programmed
+                                 // command (clean cresp) before issuing
+                                 // post-init command
+    bool do_switch_ab;           // enable AB switch?
+    bool do_switch_cd;           // enable CD switch?
+};
+
+// ADU status structure
+struct proc_adu_utils_adu_status {
+    proc_adu_utils_status_bit busy;             // altd_busy
+    proc_adu_utils_status_bit wait_cmd_arbit;   // altd_wait_cmd_arbit
+    proc_adu_utils_status_bit addr_done;        // altd_addr_done
+    proc_adu_utils_status_bit data_done;        // altd_data_done
+    proc_adu_utils_status_bit wait_resp;        // altd_wait_resp
+    proc_adu_utils_status_bit overrun_err;      // altd_overrun_error
+    proc_adu_utils_status_bit autoinc_err;      // altd_autoinc_error
+    proc_adu_utils_status_bit command_err;      // altd_command_error
+    proc_adu_utils_status_bit address_err;      // altd_address_error
+    proc_adu_utils_status_bit command_hang_err; // altd_pb_op_hang_error
+    proc_adu_utils_status_bit data_hang_err;    // altd_pb_data_hang_error
+    proc_adu_utils_status_bit pbinit_missing;   // altd_pbinit_missing
+};
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// ADU operation delay times for HW/sim
+const uint32_t PROC_ADU_UTILS_ADU_HW_NS_DELAY = 10000;
+const uint32_t PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY = 10000;
+
+// field width definitions
+const uint32_t PROC_ADU_UTILS_ADU_MAX_POST_QUIESCE_DELAY = ((1ULL << 20)-1ULL);
+const uint32_t PROC_ADU_UTILS_ADU_MAX_PRE_INIT_DELAY = ((1ULL << 10)-1ULL);
+
+// auto-increment constant definitions
+const uint32_t PROC_ADU_UTILS_AUTO_INCREMENT_BOUNDARY_MASK = 0x7FFFFULL;
+const uint32_t PROC_ADU_UTILS_AUTO_INCREMENT_BOUNDARY = 0x7FFF8ULL;
+
+// ADU Control register field/bit definitions
+const uint32_t ADU_CONTROL_FBC_TTYPE_START_BIT = 0;
+const uint32_t ADU_CONTROL_FBC_TTYPE_END_BIT = 5;
+const uint32_t ADU_CONTROL_FBC_RNW_BIT = 6;
+const uint32_t ADU_CONTROL_FBC_TSIZE_START_BIT = 7;
+const uint32_t ADU_CONTROL_FBC_TSIZE_END_BIT = 13;
+const uint32_t ADU_CONTROL_FBC_ADDRESS_START_BIT = 14;
+const uint32_t ADU_CONTROL_FBC_ADDRESS_END_BIT = 63;
+
+const uint32_t ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT = 32;
+const uint32_t ADU_CONTROL_FBC_ADDRESS_SPLIT_MASK = 0xFFFFFFFFULL;
+
+// ADU Command register field/bit definitions
+const uint32_t ADU_COMMAND_START_OP_BIT = 2;
+const uint32_t ADU_COMMAND_CLEAR_STATUS_BIT = 3;
+const uint32_t ADU_COMMAND_RESET_BIT = 4;
+const uint32_t ADU_COMMAND_ADDRESS_ONLY_BIT = 6;
+const uint32_t ADU_COMMAND_LOCK_PICK_BIT = 10;
+const uint32_t ADU_COMMAND_LOCKED_BIT = 11;
+const uint32_t ADU_COMMAND_LOCK_ID_START_BIT = 12;
+const uint32_t ADU_COMMAND_LOCK_ID_END_BIT = 15;
+const uint32_t ADU_COMMAND_LOCK_ID_MAX_VALUE = 0xF;
+const uint32_t ADU_COMMAND_FBC_SCOPE_START_BIT = 16;
+const uint32_t ADU_COMMAND_FBC_SCOPE_END_BIT = 18;
+const uint32_t ADU_COMMAND_AUTO_INC_BIT = 19;
+const uint32_t ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT = 20;
+const uint32_t ADU_COMMAND_FBC_DROP_PRIORITY_END_BIT = 21;
+const uint32_t ADU_COMMAND_FBC_INIT_OVERRIDE_BIT = 23;
+const uint32_t ADU_COMMAND_FBC_INIT_WAIT_LOW_BIT = 25;
+const uint32_t ADU_COMMAND_FBC_TM_QUIESCE_BIT = 26;
+const uint32_t ADU_COMMAND_FBC_PRE_QUIESCE_BIT = 27;
+const uint32_t ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT = 28;
+const uint32_t ADU_COMMAND_FBC_POST_QUIESCE_COUNT_END_BIT = 47;
+const uint32_t ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT = 50;
+const uint32_t ADU_COMMAND_FBC_PRE_INIT_COUNT_END_BIT = 59;
+const uint32_t ADU_COMMAND_FBC_POST_INIT_BIT = 63;
+
+// ADU Status register field/bit definitions
+const uint32_t ADU_STATUS_FBC_ALTD_BUSY_BIT = 0;
+const uint32_t ADU_STATUS_FBC_ALTD_WAIT_CMD_ARBIT_BIT = 1;
+const uint32_t ADU_STATUS_FBC_ALTD_ADDR_DONE_BIT = 2;
+const uint32_t ADU_STATUS_FBC_ALTD_DATA_DONE_BIT = 3;
+const uint32_t ADU_STATUS_FBC_ALTD_WAIT_RESP_BIT = 4;
+const uint32_t ADU_STATUS_FBC_ALTD_OVERRUN_ERR_BIT = 5;
+const uint32_t ADU_STATUS_FBC_ALTD_AUTOINC_ERR_BIT = 6;
+const uint32_t ADU_STATUS_FBC_ALTD_COMMAND_ERR_BIT = 7;
+const uint32_t ADU_STATUS_FBC_ALTD_ADDRESS_ERR_BIT = 8;
+const uint32_t ADU_STATUS_FBC_ALTD_COMMAND_HANG_ERR_BIT = 9;
+const uint32_t ADU_STATUS_FBC_ALTD_DATA_HANG_ERR_BIT = 10;
+const uint32_t ADU_STATUS_FBC_ALTD_INIT_MISSING_BIT = 18;
+
+// ADU Force ECC register field/bit definitions
+const uint32_t ADU_FORCE_ECC_DATA_ITAG_BIT = 0;
+const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT = 1;
+const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_HI_END_BIT = 8;
+const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT = 9;
+const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_END_BIT = 16;
+const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_OVERWRITE_BIT = 17;
+
+// ADU pMISC Mode register field/bit definitions
+const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30;
+const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31;
+
+// ADU Data register field/bit definitions
+const uint32_t ADU_DATA_START_BIT = 0;
+const uint32_t ADU_DATA_END_BIT = 63;
+
+const uint32_t ADU_DATA_SPLIT_BIT = 32;
+const uint32_t ADU_DATA_SPLIT_MASK = 0xFFFFFFFFULL;
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+// function: read ADU Command register, get ADU lock identifier
+// parameters: i_target  => P8 chip target
+//             o_lock_id => lock ID read
+// returns: FAPI_RC_SUCCESS if SCOM read is successful,
+//          else error
+fapi::ReturnCode proc_adu_utils_get_adu_lock_id(
+    const fapi::Target& i_target,
+    uint8_t& o_lock_id);
+
+// function: read-modify-write ADU Command register to clear auto-increment
+//           mode (necessary to complete operation at 0.5M boundary)
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target => P8 chip target
+// returns: FAPI_RC_SUCCESS if read-modify-write sequence is successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          else error
+fapi::ReturnCode proc_adu_utils_clear_adu_auto_inc(
+    const fapi::Target& i_target);
+
+// function: manipulate state of ADU atomic lock (set/pick/clear)
+// parameters: i_target         => P8 chip target
+//             i_lock_operation => lock operation to perform
+//             i_num_attempts   => number of lock manipulation attempts to
+//                                 make before giving up (will only
+//                                 continue to attempt if SCOM return code
+//                                 indicates failure due to lock state)
+// returns: FAPI_RC_SUCCESS if lock manipulation is successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid number of attempts
+//              is specified,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs,
+//          else error
+fapi::ReturnCode proc_adu_utils_manage_adu_lock(
+    const fapi::Target& i_target,
+    const proc_adu_utils_adu_lock_operation& i_lock_operation,
+    const uint32_t& i_num_attempts);
+
+// function: write ADU Command register to clear the ADU Status register and
+//           reset the ADU state machine
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target => P8 chip target
+// returns: FAPI_RC_SUCCESS if ADU reset is successful
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          else error
+fapi::ReturnCode proc_adu_utils_reset_adu(
+    const fapi::Target& i_target);
+
+// function: initiate fabric command via writes to ADU Command & Control
+//           registers
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target     => P8 chip target
+//             i_adu_ctl    => struct defining fabric command type & ADU control
+//                             parameters
+//             i_use_hp     => perform actions specified in hotplug control
+//                             argument?
+//             i_adu_hp_ctl => struct defining hotplug control parameters
+// returns: FAPI_RC_SUCCESS if ADU Command/Control register writes are
+//              successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid/out-of-range input
+//              parameters are specified,
+//          else error
+fapi::ReturnCode proc_adu_utils_send_fbc_op(
+    const fapi::Target& i_target,
+    const proc_adu_utils_fbc_op& i_adu_ctl,
+    const bool& i_use_hp,
+    const proc_adu_utils_fbc_op_hp_ctl& i_adu_hp_ctl);
+
+// function: read ADU Status register, return structure encapsulating
+//           error/status bits
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target      => P8 chip target
+//             o_status_act  => struct defining state of status/error bits
+// returns: FAPI_RC_SUCCESS if status register read is successful,
+//          else error
+fapi::ReturnCode proc_adu_utils_get_adu_status(
+    const fapi::Target& i_target,
+    proc_adu_utils_adu_status& o_status_act);
+
+// function: write ADU Data & Force ECC registers (to set outbound data to be
+//           delivered to the fabric)
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target        => P8 chip target
+//             i_write_data    => 64-bits of data to be written
+//             i_override_itag => set value of itag (65th) bit?
+//             i_write_itag    => value of itag (65th) bit to be written if
+//                                i_override_itag=true
+//             i_override_ecc  => set override ECC value?
+//             i_write_ecc     => value of ECC to be written if
+//                                i_override_ecc=true
+// returns: FAPI_RC_SUCCESS if register writes are successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          else error
+fapi::ReturnCode proc_adu_utils_set_adu_data_registers(
+    const fapi::Target& i_target,
+    const uint64_t& i_write_data,
+    const bool& i_override_itag,
+    const bool& i_write_itag,
+    const bool& i_override_ecc,
+    const uint8_t& i_write_ecc);
+
+// function: read ADU Data & Force ECC registers (to get inbound data
+//           delivered from the fabric)
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target     => P8 chip target
+//             i_get_itag   => get value of itag (65th) bit?
+//             o_read_data  => 64-bits of data read
+//             o_read_itag  => value of itag (65th) bit read (only valid
+//                             if i_get_itag=true)
+// returns: FAPI_RC_SUCCESS if register reads are successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          else error
+fapi::ReturnCode proc_adu_utils_get_adu_data_registers(
+    const fapi::Target& i_target,
+    const bool& i_get_itag,
+    uint64_t& o_read_data,
+    bool& o_read_itag);
+
+} // extern "C"
+
+#endif // _PROC_ADU_UTILS_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml
new file mode 100644
index 000000000..9fbd949ae
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml
@@ -0,0 +1,36 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_adu_utils library -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_ADU_UTILS_INVALID_ARGS</rc>
+    <description>Invalid or out-of-range argument value(s) presented to proc_adu_utils library routine.</description>
+    <ffdc>ARGS</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_ADU_UTILS_INTERNAL_ERR</rc>
+    <description>Unexpected internal program logic error</description>
+    <ffdc>ERR_DATA</ffdc>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
new file mode 100644
index 000000000..99dbcf9c5
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
@@ -0,0 +1,924 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp.C,v 1.4 2012/09/24 10:55:02 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp.C
+// *! DESCRIPTION : Perform fabric configuration (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp.H"
+#include "proc_build_smp_epsilon.H"
+#include "proc_build_smp_fbc_nohp.H"
+#include "proc_build_smp_fbc_ab.H"
+#include "proc_build_smp_fbc_cd.H"
+#include "proc_build_smp_adu.H"
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: wrapper function to call all system attribute query functions
+//           (fabric configuration/frequencies/etc)
+// parameters: io_smp_chip => structure encapsulating single chip in SMP topology
+// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
+//              are valid,
+//          RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_PUMP_TYPE_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency
+//              ratio is unsupported,
+//          RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is
+//              invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_process_system(
+    proc_build_smp_system& io_smp)
+{
+    // return code
+    fapi::ReturnCode rc;
+    // temporary attribute storage
+    uint8_t temp_attr;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_process_system: Start");
+
+    do
+    {
+        // get PB frequency attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying PB frequency attribute");
+        rc = FAPI_ATTR_GET(ATTR_FREQ_PB,
+                           NULL,
+                           io_smp.freq_pb);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_PB");
+            break;
+        }
+
+        // get A bus frequency attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying A bus frequency attribute");
+        rc = FAPI_ATTR_GET(ATTR_FREQ_A,
+                           NULL,
+                           io_smp.freq_a);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_A");
+            break;
+        }
+
+        // get X bus frequency attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying X bus frequency attribute");
+        rc = FAPI_ATTR_GET(ATTR_FREQ_X,
+                           NULL,
+                           io_smp.freq_x);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_X");
+            break;
+        }
+
+        // get core floor frequency attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying core floor frequency attribute");
+        rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_FLOOR,
+                           NULL,
+                           io_smp.freq_core_floor);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_FLOOR");
+            break;
+        }
+
+        // get PCIe frequency attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying PCIe frequency attribute");
+        rc = FAPI_ATTR_GET(ATTR_FREQ_PCIE,
+                           NULL,
+                           io_smp.freq_pcie);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_PCIE");
+            break;
+        }
+
+        // get X bus width attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying X bus width attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_X_BUS_WIDTH,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_X_BUS_WIDTH)");
+            break;
+        }
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 1:
+                io_smp.x_bus_8B = false;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_X_BUS_WIDTH = 4B");
+                break;
+            case 2:
+                io_smp.x_bus_8B = true;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_X_BUS_WIDTH = 8B");
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid X bus width attribute value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // get PB pump type attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying PB pump mode attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_PUMP_MODE,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_PUMP_MODE)");
+            break;
+        }
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 1:
+                io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE1;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_PUMP_MODE = NODAL_IS_CHIP_GROUP_IS_GROUP");
+                break;
+            case 2:
+                io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE2;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_PUMP_MODE = NODAL_AND_GROUP_IS_GROUP");
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid fabric pump mode attribute value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_PUMP_MODE_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // get MCS interleaving attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying MC interleave attribute");
+        rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_ALL_MCS_IN_INTERLEAVING_GROUP)");
+            break;
+        }
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 0:
+                io_smp.all_mcs_interleaved = false;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_ALL_MCS_IN_INTERLEAVING_GROUP = false");
+                break;
+            case 1:
+                FAPI_DBG("proc_build_smp_process_system: ATTR_ALL_MCS_IN_INTERLEAVING_GROUP = true");
+                io_smp.all_mcs_interleaved = true;
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid MCS interleaving value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // get epsilon attributes
+        FAPI_DBG("proc_build_smp_process_system: Querying epsilon table type attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_TABLE_TYPE,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_TABLE_TYPE)");
+            break;
+        }
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 1:
+                io_smp.eps_cfg.table_type = PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_TABLE_TYPE = LE");
+                break;
+            case 2:
+                io_smp.eps_cfg.table_type = PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_TABLE_TYPE = HE");
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid epsilon table type attribute value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        FAPI_DBG("proc_build_smp_process_system: Querying epsilon guardband attributes");
+        // set default value (+20%)
+        temp_attr = 0x0;
+        rc = FAPI_ATTR_SET(ATTR_PROC_EPS_GB_DIRECTION,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_EPS_GB_DIRECTION)");
+            break;
+        }
+
+        io_smp.eps_cfg.gb_percentage = 20;
+        rc = FAPI_ATTR_SET(ATTR_PROC_EPS_GB_PERCENTAGE,
+                           NULL,
+                           io_smp.eps_cfg.gb_percentage);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_EPS_GB_PERCENTAGE)");
+            break;
+        }
+
+        // retrieve guardband attributes
+        // if user overrides are set, the user overrides will take presedence over writes above
+        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_GB_DIRECTION,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_GB_DIRECTION)");
+            break;
+        }
+
+        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_GB_PERCENTAGE,
+                           NULL,
+                           io_smp.eps_cfg.gb_percentage);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_GB_PERCENTAGE)");
+            break;
+        }
+
+        // print attribute values
+        FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_PERCENTAGE = 0x%X",
+                 io_smp.eps_cfg.gb_percentage);
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 0:
+                io_smp.eps_cfg.gb_positive = true;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_DIRECTION = +");
+                break;
+            case 1:
+                io_smp.eps_cfg.gb_positive = false;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_DIRECTION = -");
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid epsilon guardband direction attribute value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // manage safe mode attribute
+        FAPI_DBG("proc_build_smp_process_system: Querying async safe mode attribute");
+        // set default value (performance mode)
+        temp_attr = 0x0;
+        rc = FAPI_ATTR_SET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_FABRIC_ASYNC_SAFE_MODE)");
+            break;
+        }
+
+        // retrieve safe mode attribute
+        // if user overrides is set, it will take presedence over write above
+        rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE,
+                           NULL,
+                           temp_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_ASYNC_SAFE_MODE)");
+            break;
+        }
+
+        // translate to output value
+        switch (temp_attr)
+        {
+            case 0:
+                io_smp.async_safe_mode = false;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_ASYNC_SAFE_MODE = false");
+                break;
+            case 1:
+                io_smp.async_safe_mode = true;
+                FAPI_DBG("proc_build_smp_process_system: ATTR_FABRIC_PROC_ASYNC_SAFE_MODE = true");
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_process_system: Invalid fabric async safe mode attribute value 0x%02X",
+                         temp_attr);
+                const uint8_t& ATTR_DATA = temp_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // determine epsilon table index based on pb/core floor frequency ratio
+        // breakpoint ratio: core floor 4.8, pb 2.4 (cache floor :: pb = 8/8)
+        FAPI_DBG("proc_build_smp_process_system: Calculating core floor to nest frequency ratio");
+        if ((io_smp.freq_core_floor) >= (2 * io_smp.freq_pb))
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8;
+        }
+        // breakpoint ratio: core floor 4.2, pb 2.4 (cache floor :: pb = 7/8)
+        else if ((4 * io_smp.freq_core_floor) >= (7 * io_smp.freq_pb))
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8;
+        }
+        // breakpoint ratio: core floor 3.6, pb 2.4 (cache floor :: pb = 6/8)
+        else if ((2 * io_smp.freq_core_floor) >= (3 * io_smp.freq_pb))
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8;
+        }
+        // breakpoint ratio: core floor 3.0, pb 2.4 (cache floor :: pb = 5/8)
+        else if ((4 * io_smp.freq_core_floor) >= (5 * io_smp.freq_pb))
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8;
+        }
+        // breakpoint ratio: core floor 2.4, pb 2.4 (cache floor :: pb = 4/8)
+        else if (io_smp.freq_core_floor >= io_smp.freq_pb)
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8;
+        }
+        // breakpoint ratio: core floor 1.2, pb 2.4 (cache floor :: pb = 2/8)
+        else if ((2 * io_smp.freq_core_floor) >= io_smp.freq_pb)
+        {
+            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8;
+        }
+        // under-range, raise error
+        else
+        {
+            FAPI_ERR("proc_build_smp_process_system: Unsupported core floor/PB frequency ratio (=%d/%d)",
+                     io_smp.freq_core_floor, io_smp.freq_pb);
+            const uint32_t& FREQ_PB = io_smp.freq_pb;
+            const uint32_t& FREQ_CORE_FLOOR = io_smp.freq_core_floor;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR);
+            break;
+        }
+    } while(0);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_process_system: End");
+    return rc;
+};
+
+
+//------------------------------------------------------------------------------
+// function: wrapper function to call all chip attribute query functions
+//           (fabric configuration/node/position)
+// parameters: i_proc_chip => pointer to HWP input structure for this chip
+//             io_smp_chip => structure encapsulating single chip in SMP topology
+// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
+//              are valid,
+//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_process_chip(
+    proc_build_smp_proc_chip* i_proc_chip,
+    proc_build_smp_chip& io_smp_chip)
+{
+    // return code
+    fapi::ReturnCode rc;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_process_chip: Start");
+
+    do
+    {
+        // set HWP input pointer
+        io_smp_chip.chip = i_proc_chip;
+
+        // display target information for this chip
+        FAPI_DBG("proc_build_smp_process_chip: Target: %s",
+                 io_smp_chip.chip->this_chip.toEcmdString());
+
+        // get PCIe/DSMP mux attributes
+        FAPI_DBG("proc_build_smp_process_chip: Querying PCIe/DSMP mux attribute");
+        rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip),
+                                                  io_smp_chip.pcie_not_f_link);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_pcie_dsmp_mux_attrs");
+            break;
+        }
+
+        // get node ID attribute
+        FAPI_DBG("proc_build_smp_process_chip: Querying node ID attribute");
+        rc = proc_fab_smp_get_node_id_attr(&(io_smp_chip.chip->this_chip),
+                                           io_smp_chip.node_id);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_node_id_attr");
+            break;
+        }
+
+        // get chip ID attribute
+        FAPI_DBG("proc_build_smp_process_chip: Querying chip ID attribute");
+        rc = proc_fab_smp_get_chip_id_attr(&(io_smp_chip.chip->this_chip),
+                                           io_smp_chip.chip_id);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_chip_id_attr");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_process_chip: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set chip master status (node/system) for PB operations
+// parameters: i_first_chip_in_sys  => first chip processed in system?
+//             i_first_chip_in_node => first chip processed in node?
+//             i_op                 => procedure operation phase/mode
+//             io_smp_chip          => structure encapsulating single chip in
+//                                     SMP topology
+//             io_smp               => structure encapsulating SMP
+//             o_master_chip_sys    => indication that this chip is current
+//                                     system master
+// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges
+//              are valid,
+//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
+//              is detected based on chip state and input paramters,
+//          RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation
+//              is specified
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_master_config(
+    const bool i_first_chip_in_sys,
+    const bool i_first_chip_in_node,
+    const proc_build_smp_operation i_op,
+    proc_build_smp_chip& io_smp_chip,
+    proc_build_smp_system& io_smp,
+    bool & o_master_chip_sys)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+    bool error = false;
+    o_master_chip_sys = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_master_config: Start");
+
+    do
+    {
+        // retrieve CURR state of node/system master designation from HW
+        rc = proc_build_smp_get_hotplug_curr_reg(io_smp_chip,
+                                                 true,
+                                                 data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_master_config: Error from proc_build_smp_get_hotplug_curr_reg");
+            break;
+        }
+
+        io_smp_chip.master_chip_sys_curr =
+            (data.isBitSet(PB_HP_MODE_MASTER_CHIP_BIT));
+
+        io_smp_chip.master_chip_node_curr =
+            (data.isBitSet(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT));
+
+        // check/set expectation for NEXT state based on current HW programming
+        // as well as input parameters
+        // HBI
+        if (i_op == SMP_ACTIVATE_PHASE1)
+        {
+            // check input state
+            if (!io_smp_chip.master_chip_sys_curr ||
+                io_smp_chip.master_chip_node_curr)
+            {
+                error = true;
+            }
+            // set next state based on input parameters
+            io_smp_chip.master_chip_sys_next = i_first_chip_in_sys;
+            io_smp_chip.master_chip_node_next = i_first_chip_in_node;
+
+            // set current system master pointer
+            if (!io_smp.master_chip_curr_set &&
+                io_smp_chip.master_chip_sys_curr)
+            {
+                o_master_chip_sys = true;
+            }
+        }
+        // FSP
+        else if (i_op == SMP_ACTIVATE_PHASE2)
+        {
+            // if designated as new master, should already be one
+            if (!io_smp_chip.master_chip_sys_curr &&
+                i_first_chip_in_sys)
+            {
+                error = true;
+            }
+
+            // set next state based on input parameters
+            io_smp_chip.master_chip_sys_next = i_first_chip_in_sys;
+            io_smp_chip.master_chip_node_next = io_smp_chip.master_chip_node_curr;
+
+            // set current system master pointer
+            if (!io_smp.master_chip_curr_set &&
+                io_smp_chip.master_chip_sys_curr)
+            {
+                o_master_chip_sys = true;
+            }
+        }
+        // unsupported operation
+        else
+        {
+            FAPI_ERR("proc_build_smp_set_master_config: Unsupported operation presented");
+            const uint8_t& OP = i_op;
+            FAPI_SET_HWP_ERROR(
+                rc,
+                RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR);
+            break;
+        }
+
+        // error for supported operation
+        if (error)
+        {
+           FAPI_ERR("proc_build_smp_set_master_config: Node/system master designation error");
+           const uint8_t& OP = i_op;
+           const bool& MASTER_CHIP_SYS_CURR = io_smp_chip.master_chip_sys_curr;
+           const bool& MASTER_CHIP_NODE_CURR = io_smp_chip.master_chip_node_curr;
+           const bool& FIRST_CHIP_IN_SYS = i_first_chip_in_sys;
+           const bool& FIRST_CHIP_IN_NODE = i_first_chip_in_node;
+           FAPI_SET_HWP_ERROR(
+               rc,
+               RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR);
+           break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_master_config: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: insert chip structure into proper position within SMP model based
+//           on its fabric node/chip ID
+// parameters: io_smp_chip          => structure encapsulating single chip in
+//                                     SMP topology
+//             i_first_chip_in_sys  => first chip processed in system?
+//             i_op                 => procedure operation phase/mode
+//             io_smp               => structure encapsulating full SMP
+// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges
+//              are valid,
+//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
+//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
+//              fabric node/chip IDs are detected,
+//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
+//              is detected based on chip state and input paramters,
+//          RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation
+//              is specified
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_insert_chip(
+    proc_build_smp_chip& io_smp_chip,
+    const bool i_first_chip_in_sys,
+    const proc_build_smp_operation i_op,
+    proc_build_smp_system& io_smp)
+{
+    // return code
+    fapi::ReturnCode rc;
+    // node/chip ID
+    proc_fab_smp_node_id node_id = io_smp_chip.node_id;
+    proc_fab_smp_chip_id chip_id = io_smp_chip.chip_id;
+    // first chip found in node?
+    bool first_chip_in_node  = false;
+    // chip is current SMP master?
+    bool master_chip_sys_curr;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_insert_chip: Start");
+
+    do
+    {
+        FAPI_DBG("proc_build_smp_insert_chip: Inserting n%d p%d",
+                 node_id, chip_id);
+
+        // search to see if node structure already exists for the node ID
+        // associated with this chip
+        std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator
+            n_iter;
+        n_iter = io_smp.nodes.find(node_id);
+        // no matching node found, create one
+        if (n_iter == io_smp.nodes.end())
+        {
+            FAPI_DBG("proc_build_smp_insert_chip: No matching node found, inserting new node structure");
+            proc_build_smp_node n;
+            n.node_id = io_smp_chip.node_id;
+            std::pair<
+                std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator,
+                bool> ret;
+            ret = io_smp.nodes.insert(
+                std::pair<proc_fab_smp_node_id, proc_build_smp_node>
+                (node_id, n));
+            n_iter = ret.first;
+            if (!ret.second)
+            {
+                FAPI_ERR("proc_build_smp_insert_chip: Error encountered adding node to SMP");
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR);
+                break;
+            }
+            // first chip in node
+            first_chip_in_node = true;
+        }
+
+        // search to see if match exists in this node for the chip ID associated
+        // with this chip
+        std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator
+            p_iter;
+        p_iter = io_smp.nodes[node_id].chips.find(chip_id);
+        // matching chip ID & node ID already found, flag an error
+        if (p_iter != io_smp.nodes[node_id].chips.end())
+        {
+            FAPI_ERR("proc_build_smp_insert_chip: Duplicate fabric node ID / chip ID found");
+            const uint8_t& NODE_ID = node_id;
+            const uint8_t& CHIP_ID = chip_id;
+            FAPI_SET_HWP_ERROR(rc,
+                RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR);
+            break;
+        }
+
+        // determine node/system master status
+        FAPI_DBG("proc_build_smp_insert_chip: Determining node/system master status");
+        rc = proc_build_smp_set_master_config(i_first_chip_in_sys,
+                                              first_chip_in_node,
+                                              i_op,
+                                              io_smp_chip,
+                                              io_smp,
+                                              master_chip_sys_curr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_insert_chip: Error from proc_fab_smp_set_master_config");
+            break;
+        }
+
+        // insert chip into SMP
+        io_smp.nodes[node_id].chips[chip_id] = io_smp_chip;
+        // save pointer to current system master chip?
+        if (master_chip_sys_curr)
+        {
+            io_smp.master_chip_curr_set = true;
+            io_smp.master_chip_curr_node_id = node_id;
+            io_smp.master_chip_curr_chip_id = chip_id;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_insert_chip: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: wrapper function to process all HWP input structures and build
+//           SMP data structure
+// parameters: i_proc_chips => vector of HWP input structures (one entry per
+//                             chip in SMP)
+//             i_op         => procedure operation phase/mode
+//             io_smp       => fully specified structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if all processing is successful,
+//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
+//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
+//              fabric node/chip IDs are detected,
+//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
+//              is detected based on chip state and input paramters,
+//          RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation
+//              is specified
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_process_chips(
+    std::vector<proc_build_smp_proc_chip>& i_proc_chips,
+    const proc_build_smp_operation i_op,
+    proc_build_smp_system& io_smp)
+{
+    // return code
+    fapi::ReturnCode rc;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_process_chips: Start");
+
+    // loop over all chips passed from platform to HWP
+    std::vector<proc_build_smp_proc_chip>::iterator i;
+    for (i = i_proc_chips.begin(); i != i_proc_chips.end(); i++)
+    {
+        // process platform provided data in chip argument,
+        // query chip specific attributes
+        proc_build_smp_chip smp_chip;
+        rc = proc_build_smp_process_chip(&(*i),
+                                         smp_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_process_chip");
+            break;
+        }
+
+        // insert chip into SMP data structure given node & chip ID
+        rc = proc_build_smp_insert_chip(smp_chip,
+                                        (i == i_proc_chips.begin()),
+                                        i_op,
+                                        io_smp);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_insert_chip");
+            break;
+        }
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_process_chips: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: proc_setup_bars HWP entry point
+//           NOTE: see comments above function prototype in header
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp(
+    std::vector<proc_build_smp_proc_chip> & i_proc_chips,
+    const proc_build_smp_operation i_op)
+{
+    fapi::ReturnCode rc;
+    proc_build_smp_system smp;
+    smp.master_chip_curr_set = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp: Start");
+
+    do
+    {
+        // query system specific attributes
+        rc = proc_build_smp_process_system(smp);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp: Error from proc_build_smp_process_system");
+            break;
+        }
+
+        // process HWP input vector of chip structures
+        rc = proc_build_smp_process_chips(i_proc_chips, i_op, smp);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp: Error from proc_build_smp_process_chips");
+            break;
+        }
+
+        // initialize fabric configuration
+        if (i_op == SMP_ACTIVATE_PHASE1)
+        {
+            // program nest epsilon attributes/registers
+            rc = proc_build_smp_set_epsilons(smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_epsilons");
+                break;
+            }
+
+            // set fabric configuration registers (non-hotplug)
+            rc = proc_build_smp_set_fbc_nohp(smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_nohp");
+                break;
+            }
+
+            // set fabric configuration registers (hotplug, switch CD set)
+            rc = proc_build_smp_set_fbc_cd(smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_cd");
+                break;
+            }
+        }
+
+        // activate SMP
+        // set fabric configuration registers (hotplug, switch AB set)
+        rc = proc_build_smp_set_fbc_ab(smp, i_op);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_ab");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
new file mode 100644
index 000000000..66ce8b5a2
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
@@ -0,0 +1,302 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp.H,v 1.6 2012/09/24 04:59:17 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp.H
+// *! DESCRIPTION : Perform fabric configuration (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS:
+// *!
+// *! Perform fabric SMP build/reconfiguration operations.
+// *!
+// *! Platform Notes:
+// *!     This HWP has multiple IPL use cases.  In all all cases the HWP input
+// *!     is expected to contain an entry for each chip within the scope of
+// *!     the new SMP to be constructed (with valid information for all
+// *!     active links that are fully contained within the new SMP).
+// *!
+// *!     The proc_build_smp_operation HWP input defines the desired
+// *!     reconfiguration option to be performed:
+// *!
+// *!         SMP_ACTIVATE_PHASE1 (HBI):
+// *!             o init epsilon registers,
+// *!             o program FBC configuration dependent registers (switch C/D)
+// *!             o join all single chip 'island' fabrics into drawer level
+// *!                SMP (switch A/B)
+// *!
+// *!         SMP_ACTIVATE_PHASE2 (FSP):
+// *!             o join collection of drawer level SMPs into full system SMP
+// *!               (switch A/B)
+// *!
+//------------------------------------------------------------------------------
+// *! TODO:: epsilon: table updates for  Venice (current: Murano only)
+// *! TODO:: epsilon: need updated pre-epsilon values (current: P7 values)
+// *! TODO:: switch CD: hang rate for foreign links & other lab tuned settings
+// *!        (current: placeholder settings from Murano sim)
+// *! TODO:: phase 2 execution for Venice (FSP drawer integration)
+// *! TODO:: support for manufacturing AVP mode configurations
+// *! TODO:: attributes for PBIEX EX inits in winkle image (scan)
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_H_
+#define _PROC_BUILD_SMP_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <vector>
+#include <map>
+#include <fapi.H>
+#include "proc_fab_smp.H"
+#include "p8_scom_addresses.H"
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// HWP argument, define supported execution modes
+enum proc_build_smp_operation
+{
+    // call from HBI (init epsilons, switch C/D + A/B)
+    // used to initialize scope of HBI drawer
+    SMP_ACTIVATE_PHASE1 = 1,
+    // call from FSP (only switch A/B)
+    // used to stitch drawers/CCM
+    SMP_ACTIVATE_PHASE2 = 2
+};
+
+// HWP argument structure defining properties of this chip
+// and links which should be considered in this invocation (X/A/F)
+struct proc_build_smp_proc_chip
+{
+    // target for this chip
+    fapi::Target this_chip;
+
+    // targets defining A link connected chips
+    fapi::Target a0_chip;
+    fapi::Target a1_chip;
+    fapi::Target a2_chip;
+
+    // targets defining X link connected chips
+    fapi::Target x0_chip;
+    fapi::Target x1_chip;
+    fapi::Target x2_chip;
+    fapi::Target x3_chip;
+
+    // parameters defining F link connected SMPs
+    bool enable_f0;
+    proc_fab_smp_node_id f0_node_id;
+    bool enable_f1;
+    proc_fab_smp_node_id f1_node_id;
+};
+
+// structure to represent fabric connectivty & properites for a single chip
+// in the SMP topology
+struct proc_build_smp_chip
+{
+    // associated HWP input structure
+    proc_build_smp_proc_chip* chip;
+
+    // chip properties/attributes:
+    // fabric chip/node ID
+    proc_fab_smp_chip_id chip_id;
+    proc_fab_smp_node_id node_id;
+    // node/system master designation (curr)
+    bool master_chip_node_curr;
+    bool master_chip_sys_curr;
+    // node/system master designation (next)
+    bool master_chip_node_next;
+    bool master_chip_sys_next;
+    // select for PCIe/DSMP mux (one per link)
+    bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS];
+};
+
+// structure to represent properties for a single node in the SMP topology
+struct proc_build_smp_node
+{
+    // chips which reside in this node
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip> chips;
+
+    // node properties/attributes:
+    // fabric node ID
+    proc_fab_smp_node_id node_id;
+};
+
+// core floor/nest frequency ratio cutpoints
+enum proc_build_smp_core_floor_ratio
+{
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8 = 0,
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8 = 1,
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8 = 2,
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8 = 3,
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8 = 4,
+    PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8 = 5
+};
+
+// structure to encapsulate system epsilon configuration
+struct proc_build_smp_eps_cfg
+{
+    // epsilon configuration inputs
+    bool gb_positive;
+    uint8_t gb_percentage;
+    proc_fab_smp_eps_table_type table_type;
+    // target epsilon values
+    uint32_t r_t0;    // read, tier0 (np)
+    uint32_t r_t1;    // read, tier1 (gp)
+    uint32_t r_t2;    // read, tier2 (sp)
+    uint32_t r_f;     // read, foreign (f)
+    uint32_t w_t2;    // write, tier2 (sp)
+    uint32_t w_f;     // write, foreign (f)
+    uint32_t p;       // pre
+};
+
+// structure to represent collection of nodes in SMP topology
+struct proc_build_smp_system
+{
+    // nodes which reside in this SMP
+    std::map<proc_fab_smp_node_id, proc_build_smp_node> nodes;
+    // system master chip (curr)
+    bool master_chip_curr_set;
+    proc_fab_smp_node_id master_chip_curr_node_id;
+    proc_fab_smp_chip_id master_chip_curr_chip_id;
+
+    // system properties/attributes:
+    // system frequencies (MHz):
+    uint32_t freq_pb;
+    uint32_t freq_a;
+    uint32_t freq_x;
+    uint32_t freq_core_floor;
+    uint32_t freq_pcie;
+    // core floor/pb frequency ratio
+    proc_build_smp_core_floor_ratio core_floor_ratio;
+
+    // program async boundary crossings to safe mode
+    bool async_safe_mode;
+    // X bus width
+    bool x_bus_8B;
+    // fabric pump mode
+    proc_fab_smp_pump_mode pump_mode;
+    // AVP test modes
+    bool avp_mode;
+    // MCS interleaving configuration
+    bool all_mcs_interleaved;
+    // system epsilon configuration
+    proc_build_smp_eps_cfg eps_cfg;
+};
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode
+(*proc_build_smp_FP_t)(std::vector<proc_build_smp_proc_chip>&,
+                       const proc_build_smp_operation);
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// PB shadow register constant definition
+const uint8_t PROC_BUILD_SMP_NUM_SHADOWS = 3;
+
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: perform fabric SMP reconfiguration operations
+// parameters: i_proc_chips => vector of structures defining properties of each
+//                             chip and links which should be considered in
+//                             this invocation (A/X/F)
+//                             NOTE: first chip in vector will become the
+//                                   fabric master after the reconfiguration
+//             i_op  => enumerated type representing SMP build phase
+//                      (SMP_ACTIVATE_PHASE1 = HBI,
+//                       SMP_ACTIVATE_PHASE2 = FSP)
+// returns: FAPI_RC_SUCCESS if SMP build operation is successful,
+//          RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_PUMP_TYPE_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency
+//              ratio is unsupported,
+//          RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
+//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
+//              fabric node/chip IDs are detected,
+//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
+//              is detected based on chip state and input paramters,
+//          RC_PROC_BUILD_SMP_INVALID_OPERATION if an unsupported operation
+//              is specified
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if HP shadow registers are not
+//              equivalent,
+//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
+//              table type/content is detected,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
+//              small/large,
+//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
+//              is unsuccessful,
+//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
+//              specifies invalid aggregate link setup,
+//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
+//              is invalid,
+//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
+//              is invalid,
+//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
+//              is invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp(
+    std::vector<proc_build_smp_proc_chip> & i_proc_chips,
+    const proc_build_smp_operation i_op);
+
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
new file mode 100644
index 000000000..591496f77
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
@@ -0,0 +1,668 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_adu.C,v 1.3 2012/09/24 05:02:10 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_adu.C
+// *! DESCRIPTION : Interface for ADU operations required to support fabric
+// *!               configuration actions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp_adu.H"
+#include "proc_adu_utils.H"
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: acquire ADU atomic lock to guarantee exclusive use of its
+//           resources
+// parameters: i_target         => P8 chip target
+//             i_adu_lock_tries => number of lock acquisistions to attempt
+//             i_adu_pick_lock  => attempt lock pick if lock acquisition
+//                                 is unsuccessful after i_adu_lock_tries?
+// returns: FAPI_RC_SUCCESS if lock is successfully acquired,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid number of lock attempts
+//              is specified,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_adu_acquire_lock(
+    const fapi::Target& i_target,
+    const uint32_t& i_adu_lock_tries,
+    const bool& i_adu_pick_lock)
+{
+    fapi::ReturnCode rc;
+    proc_adu_utils_adu_lock_operation lock_op = ADU_LOCK_ACQUIRE;
+
+    FAPI_DBG("proc_build_smp_adu_acquire_lock: Start");
+
+    do
+    {
+        // attempt ADU lock acquisition
+        FAPI_DBG("proc_build_smp_adu_acquire_lock: Calling library to acquire ADU lock");
+        rc = proc_adu_utils_manage_adu_lock(i_target,
+                                            lock_op,
+                                            i_adu_lock_tries);
+
+        // return code specifically indicates lock acquisition was not
+        // successful because ADU lock is held by another entity
+        if (rc == fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
+        {
+            FAPI_INF("proc_build_smp_adu_acquire_lock: Unable to acquire ADU lock after %d tries",
+                     i_adu_lock_tries);
+
+            // give up if lock pick is not specified
+            if (!i_adu_pick_lock)
+            {
+                FAPI_ERR("proc_build_smp_adu_acquire_lock: ADU lock acquisition unsuccessful, giving up without attempting to pick lock");
+                break;
+            }
+            // otherwise make single lock pick attempt
+            else
+            {
+                FAPI_DBG("proc_build_smp_adu_acquire_lock: Calling library to pick ADU lock");
+                lock_op = ADU_LOCK_FORCE_ACQUIRE;
+                rc = proc_adu_utils_manage_adu_lock(i_target,
+                                                    lock_op,
+                                                    1);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_adu_acquire_lock: Error from proc_adu_utils_manage_adu_lock");
+                    break;
+                }
+            }
+        }
+        // flag error on any other return code that is not OK
+        else if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_adu_acquire_lock: Error from proc_adu_utils_manage_adu_lock");
+            break;
+        }
+    } while(0);
+
+    FAPI_DBG("proc_build_smp_adu_acquire_lock: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: reset ADU state machines and status register
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target => P8 chip target
+// returns: FAPI_RC_SUCCESS if fabric is not stopped,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_adu_reset(
+    const fapi::Target& i_target)
+{
+    fapi::ReturnCode rc;
+
+    FAPI_DBG("proc_build_smp_adu_reset: Start");
+    do
+    {
+        // call ADU library function
+        FAPI_DBG("proc_build_smp_adu_reset: Calling library to reset ADU");
+        rc = proc_adu_utils_reset_adu(i_target);
+        if (!rc.ok()) {
+            FAPI_ERR("proc_build_smp_adu_reset: Error from proc_adu_utils_reset_adu");
+        }
+    } while(0);
+
+    FAPI_DBG("proc_build_smp_adu_reset: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: release ADU atomic lock
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target           => P8 chip target
+//             i_adu_unlock_tries => number of lock releases to attempt
+// returns: FAPI_RC_SUCCESS if lock is successfully released,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid number of unlock attempts
+//              is specified,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_adu_release_lock(
+    const fapi::Target& i_target,
+    const uint32_t& i_adu_unlock_tries)
+{
+    fapi::ReturnCode rc;
+
+    FAPI_DBG("proc_build_smp_adu_release_lock: Start");
+
+    do
+    {
+        // attempt ADU lock acquisition
+        FAPI_DBG("proc_build_smp_adu_release_lock: Calling library to release ADU lock");
+        rc = proc_adu_utils_manage_adu_lock(i_target,
+                                            ADU_LOCK_RELEASE,
+                                            i_adu_unlock_tries);
+
+        // return code specifically indicates lock release was not
+        // successful because ADU lock is held by another entity
+        if (rc == fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
+        {
+            FAPI_INF("proc_build_smp_adu_release_lock: Unable to release ADU lock after %d tries",
+                     i_adu_unlock_tries);
+            FAPI_ERR("proc_build_smp_adu_release_lock: ADU lock release unsuccessful");
+            break;
+        }
+        // flag error on any other return code that is not OK
+        else if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_adu_release_lock: Error from proc_adu_utils_manage_adu_lock");
+            break;
+        }
+    } while(0);
+
+    FAPI_DBG("proc_build_smp_adu_release_lock: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: check ADU status matches expected state/value
+//           NOTE: intended to be run while holding ADU lock
+// parameters: i_target         => P8 chip target
+//             i_read_not_write => desired operation (read=true, write=false)
+// returns: FAPI_RC_SUCCESS if status matches expected value,
+//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if status mismatches,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_adu_check_status(
+    const fapi::Target& i_target)
+{
+    fapi::ReturnCode rc;
+    proc_adu_utils_adu_status status_exp, status_act;
+    bool match = false;
+
+    FAPI_DBG("proc_build_smp_adu_check_status: Start");
+    do
+    {
+        // build expected status structure
+        status_exp.busy             = ADU_STATUS_BIT_CLEAR;
+        status_exp.wait_cmd_arbit   = ADU_STATUS_BIT_CLEAR;
+        status_exp.addr_done        = ADU_STATUS_BIT_SET;
+        status_exp.data_done        = ADU_STATUS_BIT_CLEAR;
+        status_exp.wait_resp        = ADU_STATUS_BIT_CLEAR;
+        status_exp.overrun_err      = ADU_STATUS_BIT_CLEAR;
+        status_exp.autoinc_err      = ADU_STATUS_BIT_CLEAR;
+        status_exp.command_err      = ADU_STATUS_BIT_CLEAR;
+        status_exp.address_err      = ADU_STATUS_BIT_CLEAR;
+        status_exp.command_hang_err = ADU_STATUS_BIT_CLEAR;
+        status_exp.data_hang_err    = ADU_STATUS_BIT_CLEAR;
+        status_exp.pbinit_missing   = ADU_STATUS_BIT_DONT_CARE;
+
+        // retreive actual status value
+        FAPI_DBG("proc_build_smp_adu_check_status: Calling library to read ADU status");
+        rc = proc_adu_utils_get_adu_status(i_target,
+                                           status_act);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_adu_check_status: Error from proc_adu_utils_get_adu_status");
+            break;
+        }
+
+        // check status bits versus expected pattern
+        match =
+            (((status_exp.busy == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.busy == status_act.busy)) &&
+             ((status_exp.wait_cmd_arbit == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.wait_cmd_arbit == status_act.wait_cmd_arbit)) &&
+             ((status_exp.addr_done == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.addr_done == status_act.addr_done)) &&
+             ((status_exp.data_done == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.data_done == status_act.data_done)) &&
+             ((status_exp.wait_resp == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.wait_resp == status_act.wait_resp)) &&
+             ((status_exp.overrun_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.overrun_err == status_act.overrun_err)) &&
+             ((status_exp.autoinc_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.autoinc_err == status_act.autoinc_err)) &&
+             ((status_exp.command_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.command_err == status_act.command_err)) &&
+             ((status_exp.address_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.address_err == status_act.address_err)) &&
+             ((status_exp.command_hang_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.command_hang_err == status_act.command_hang_err)) &&
+             ((status_exp.data_hang_err == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.data_hang_err == status_act.data_hang_err)) &&
+             ((status_exp.pbinit_missing == ADU_STATUS_BIT_DONT_CARE) ||
+              (status_exp.pbinit_missing == status_act.pbinit_missing)));
+        if (!match)
+        {
+            FAPI_ERR("proc_adu_utils_check_adu_status: Status mismatch detected");
+            FAPI_ERR("proc_adu_utils_check_adu_status: ADU Status bits:");
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_BUSY           = %d",
+                     (status_act.busy == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_WAIT_CMD_ARBIT = %d",
+                     (status_act.wait_cmd_arbit == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_ADDR_DONE      = %d",
+                     (status_act.addr_done == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_DATA_DONE      = %d",
+                     (status_act.data_done == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_WAIT_RESP      = %d",
+                     (status_act.wait_resp == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status: ADU Error bits:");
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_OVERRUN_ERROR        = %d",
+                     (status_act.overrun_err == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_AUTOINC_ERROR        = %d",
+                     (status_act.autoinc_err == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_COMMAND_ERROR        = %d",
+                     (status_act.command_err == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_ADDRESS_ERROR        = %d",
+                     (status_act.address_err == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_COMMAND_HANG_ERROR   = %d",
+                     (status_act.command_hang_err == ADU_STATUS_BIT_SET)?(1)
+                                                                        :(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_DATA_HANG_ERROR      = %d",
+                     (status_act.data_hang_err == ADU_STATUS_BIT_SET)?(1):(0));
+            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_PBINIT_MISSING_ERROR = %d",
+                     (status_act.pbinit_missing == ADU_STATUS_BIT_SET)?(1):(0));
+            const proc_adu_utils_adu_status & STATUS_DATA = status_act;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH);
+            break;
+        }
+    } while(0);
+
+    FAPI_DBG("proc_build_smp_adu_check_status: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_quiesce_pb(
+    proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    // ADU status/control information
+    proc_adu_utils_fbc_op adu_ctl;
+    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl_unused;
+    bool adu_is_dirty = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_quiesce_pb: Start");
+
+    do
+    {
+        // build ADU control structure
+        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PBOP;
+        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN;
+        adu_ctl.address = 0x0ULL;
+        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
+        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
+        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
+        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_NO_OVERRIDE;
+        adu_ctl.use_autoinc = false;
+
+        // acquire ADU lock
+        // only required to obtain lock for this chip, as this function will
+        // only be executed when fabric is configured as single chip island
+        rc = proc_build_smp_adu_acquire_lock(
+            i_smp_chip.chip->this_chip,
+            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS,
+            PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_acquire_lock");
+            break;
+        }
+        // NOTE: lock is now held, if an operation fails from this point
+        //       to the end of the procedure:
+        //       o attempt to cleanup/release lock (so that procedure does not
+        //         leave the ADU in a locked state)
+        //       o return rc of original fail
+        adu_is_dirty = true;
+
+        // reset ADU
+        rc = proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_reset");
+            break;
+        }
+
+        // launch command
+        rc = proc_adu_utils_send_fbc_op(i_smp_chip.chip->this_chip,
+                                        adu_ctl,
+                                        false,
+                                        adu_hp_ctl_unused);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_adu_utils_send_fbc_op");
+            break;
+        }
+
+        // check status
+        rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_check_status");
+            break;
+        }
+
+        // release ADU lock
+        rc = proc_build_smp_adu_release_lock(
+            i_smp_chip.chip->this_chip,
+            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_release_lock");
+            break;
+        }
+    } while(0);
+
+    // if error has occurred and ADU is dirty,
+    // attempt to reset ADU and free lock (propogate rc of original fail)
+    if (!rc.ok() && adu_is_dirty)
+    {
+        (void) proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
+        (void) proc_build_smp_adu_release_lock(i_smp_chip.chip->this_chip, 1);
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_quiesce_pb: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_switch_cd(
+    proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    // ADU status/control information
+    proc_adu_utils_fbc_op adu_ctl;
+    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl;
+    bool adu_is_dirty = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_switch_cd: Start");
+
+    do
+    {
+        // acquire ADU lock
+        // only required to obtain lock for this chip, as this function will
+        // only be executed when fabric is configured as single chip island
+        rc = proc_build_smp_adu_acquire_lock(
+            i_smp_chip.chip->this_chip,
+            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS,
+            PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_acquire_lock");
+            break;
+        }
+        // NOTE: lock is now held, if an operation fails from this point
+        //       to the end of the procedure:
+        //       o attempt to cleanup/release lock (so that procedure does not
+        //         leave the ADU in a locked state)
+        //       o return rc of original fail
+        adu_is_dirty = true;
+
+        // reset ADU
+        rc = proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_reset");
+            break;
+        }
+
+        // build ADU control structure
+        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC;
+        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB;
+        adu_ctl.address = 0x0ULL;
+        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
+        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
+        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
+        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_NO_OVERRIDE;
+        adu_ctl.use_autoinc = false;
+
+        adu_hp_ctl.do_tm_quiesce = false;
+        adu_hp_ctl.do_pre_quiesce = true;
+        adu_hp_ctl.do_post_init = true;
+        adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY;
+        adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY;
+        adu_hp_ctl.do_switch_ab = false;
+        adu_hp_ctl.do_switch_cd = true;
+
+        // launch command
+        rc = proc_adu_utils_send_fbc_op(i_smp_chip.chip->this_chip,
+                                        adu_ctl,
+                                        true,
+                                        adu_hp_ctl);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_adu_utils_send_fbc_op");
+            break;
+        }
+
+        // check status
+        rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_check_status");
+            break;
+        }
+
+        // release ADU lock
+        rc = proc_build_smp_adu_release_lock(
+            i_smp_chip.chip->this_chip,
+            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_release_lock");
+            break;
+        }
+    } while(0);
+
+    // if error has occurred and ADU is dirty,
+    // attempt to reset ADU and free lock (propogate rc of original fail)
+    if (!rc.ok() && adu_is_dirty)
+    {
+        (void) proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
+        (void) proc_build_smp_adu_release_lock(i_smp_chip.chip->this_chip, 1);
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_switch_cd: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_switch_ab(
+    proc_build_smp_chip& i_master_smp_chip,
+    proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
+    // ADU status/control information
+    proc_adu_utils_fbc_op adu_ctl;
+    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl;
+    bool adu_is_dirty = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_switch_ab: Start");
+
+    do
+    {
+        // loop through all chips, lock & reset ADU
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                // acquire ADU lock
+                rc = proc_build_smp_adu_acquire_lock(
+                    p_iter->second.chip->this_chip,
+                    PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS,
+                    PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_acquire_lock");
+                    break;
+                }
+                // NOTE: lock is now held, if an operation fails from this point
+                //       to the end of the procedure:
+                //       o attempt to cleanup/release lock (so that procedure does not
+                //         leave the ADU in a locked state)
+                //       o return rc of original fail
+                adu_is_dirty = true;
+
+                // reset ADU
+                rc = proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_reset");
+                    break;
+                }
+            }
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // build ADU control structure
+        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC;
+        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB;
+        adu_ctl.address = 0x0ULL;
+        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
+        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
+        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
+        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_NO_OVERRIDE;
+        adu_ctl.use_autoinc = false;
+
+        adu_hp_ctl.do_tm_quiesce = false;
+        adu_hp_ctl.do_pre_quiesce = true;
+        adu_hp_ctl.do_post_init = true;
+        adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY;
+        adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY;
+        adu_hp_ctl.do_switch_ab = true;
+        adu_hp_ctl.do_switch_cd = false;
+
+        // launch command
+        rc = proc_adu_utils_send_fbc_op(i_master_smp_chip.chip->this_chip,
+                                        adu_ctl,
+                                        true,
+                                        adu_hp_ctl);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_ab: Error from proc_adu_utils_send_fbc_op");
+            break;
+        }
+
+        // check status
+        rc = proc_build_smp_adu_check_status(i_master_smp_chip.chip->this_chip);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_check_status");
+            break;
+        }
+
+        // loop through all chips, unlock ADUs
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                // release ADU lock
+                rc = proc_build_smp_adu_release_lock(
+                    p_iter->second.chip->this_chip,
+                    PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_release_lock");
+                    break;
+                }
+            }
+        }
+    } while(0);
+
+
+    // if error has occurred and any ADU is dirty,
+    // attempt to reset all ADUs and free locks (propogate rc of original fail)
+    if (!rc.ok() && adu_is_dirty)
+    {
+        // loop through all chips, unlock ADUs
+        for (n_iter = i_smp.nodes.begin();
+             n_iter != i_smp.nodes.end();
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 p_iter != n_iter->second.chips.end();
+                 p_iter++)
+            {
+                (void) proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
+                (void) proc_build_smp_adu_release_lock(
+                    p_iter->second.chip->this_chip,
+                    1);
+            }
+        }
+    }
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_switch_ab: End");
+    return rc;
+}
+
+
+} // extern "C"
+
+
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
new file mode 100644
index 000000000..64ba94e0d
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
@@ -0,0 +1,131 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_adu.H,v 1.2 2012/09/05 03:11:26 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_adu.H
+// *! DESCRIPTION : Interface for ADU operations required to support fabric
+// *!               configuration actions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_ADU_H_
+#define _PROC_BUILD_SMP_ADU_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+#include "proc_build_smp.H"
+
+//------------------------------------------------------------------------------
+// Constants
+//------------------------------------------------------------------------------
+
+const uint32_t PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS = 1;
+const bool PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK = false;
+const uint32_t PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY = 128;
+const uint32_t PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY = 128;
+
+const uint32_t PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS = 5;
+const bool PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK = true;
+const uint32_t PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY = 4096;
+const uint32_t PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY = 512;
+
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: perform fabric quiesce on a single chip
+// parameters: i_smp_chip => structure encapsulating chip
+// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected
+//              by ADU library code,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs in ADU library code,
+//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
+//              for switch operation,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_quiesce_pb(
+    proc_build_smp_chip& i_smp_chip);
+
+//------------------------------------------------------------------------------
+// function: perform fabric C/D configuration switch on a single chip
+// parameters: i_smp_chip => structure encapsulating chip
+// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected
+//              by ADU library code,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs in ADU library code,
+//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
+//              for switch operation,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_switch_cd(
+    proc_build_smp_chip& i_smp_chip);
+
+
+//------------------------------------------------------------------------------
+// function: perform fabric A/B configuration switch on all chips present in
+//           SMP (defined by i_smp)
+//           NOTE: ADU atomic lock will be obtained for all chips prior to
+//                 issuing switch from master chip (defined by
+//                 i_master_smp_chip)
+// parameters: i_master_smp_chip => structure encapsulating current SMP master
+//                                  chip
+//             i_smp             => structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
+//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
+//              ADU atomic lock,
+//          RC_PROC_ADU_UTILS_INVALID_ARGS if invalid parameters are detected
+//              by ADU library code,
+//          RC_PROC_ADU_UTILS_INTERNAL_ERR if an unexpected internal
+//              logic error occurs in ADU library code,
+//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
+//              for switch operation,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_switch_ab(
+    proc_build_smp_chip& i_master_smp_chip,
+    proc_build_smp_system& i_smp);
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_ADU_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
new file mode 100644
index 000000000..0c05f5861
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
@@ -0,0 +1,1336 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_epsilon.C,v 1.4 2012/09/24 05:02:40 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_epsilon.C
+// *! DESCRIPTION : Epsilon calculation/application functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp_epsilon.H"
+
+extern "C" {
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: utility function to round to ceiling
+// parameters: i_n => numerator
+//             i_d => denominator
+// returns: ceiling of i_n / i_d (integer)
+//------------------------------------------------------------------------------
+uint32_t proc_build_smp_round_ceiling(
+    uint32_t i_n,
+    uint32_t i_d)
+{
+    return((i_n / i_d) + ((i_n % i_d)?(1):(0)));
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to apply positive/negative scaing factor
+//           to base epsilon value
+// parameters: i_gb_positive   => set guardband direction (true=positive,
+//                                false=negative)
+//             i_gb_percentage => scaling factor (e.g. 20% = 20)
+//             io_target_value => target epsilon value, after
+//                                application of scaling factor
+//                                NOTE: scaling will be clamped to
+//                                minimum/maximum value
+// returns: void
+//------------------------------------------------------------------------------
+void proc_build_smp_guardband_epsilon(
+    const bool i_gb_positive,
+    const uint8_t i_gb_percentage,
+    uint32_t & io_target_value)
+{
+    uint32_t delta = proc_build_smp_round_ceiling(io_target_value * i_gb_percentage, 100);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_guardband_epsilon: Start");
+
+    // apply guardband
+    if (i_gb_positive)
+    {
+        // clamp to maximum value if necessary
+        if (delta > (PROC_BUILD_SMP_EPSILON_MAX_VALUE - io_target_value))
+        {
+            FAPI_DBG("proc_build_smp_guardband_epsilon: Guardband application generated out-of-range target value, clamping to maximum value!");
+            io_target_value = PROC_BUILD_SMP_EPSILON_MAX_VALUE;
+        }
+        else
+        {
+            io_target_value += delta;
+        }
+    }
+    else
+    {
+        // clamp to minimum value if necessary
+        if (delta >= io_target_value)
+        {
+            FAPI_DBG("proc_build_smp_guardband_epsilon: Guardband application generated out-of-range target value, clamping to minimum value!");
+            io_target_value = PROC_BUILD_SMP_EPSILON_MIN_VALUE;
+        }
+        else
+        {
+            io_target_value -= delta;
+        }
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_guardband_epsilon: End");
+    return;
+}
+
+
+//------------------------------------------------------------------------------
+// function: check if target epsilon value is less than maximum realizable
+//           value given underlying register storage
+// parameters: i_target_value => desired epsilon value
+//             i_max_hw_value => largest value which can be represented by
+//                               underlying register storage
+//             i_must_fit     => raise error if true and target value
+//                               cannot be represented in underlying storage
+//             o_does_fit     => boolean indicating comparison result
+// returns: FAPI_RC_SUCCESS if value can be represented in HW storage (or
+//              i_must_fit is false)
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if value is out of range and
+//              i_must_fit is true
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_check_epsilon(
+    const uint32_t i_target_value,
+    const uint32_t i_max_hw_value,
+    const bool i_must_fit,
+    bool& o_does_fit)
+{
+    fapi::ReturnCode rc;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_check_epsilon: Start");
+
+    do
+    {
+        o_does_fit = (i_max_hw_value > i_target_value);
+
+        if (i_must_fit && !o_does_fit)
+        {
+            FAPI_ERR("proc_build_smp_check_epsilon: Desired value (= %d) is greater than maximum value supported by HW (= %d)",
+                     i_target_value, i_max_hw_value);
+            const uint32_t& VALUE = i_target_value;
+            const uint32_t& MAX_HW_VALUE = i_max_hw_value;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR);
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_check_epsilon: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set L2 unit epsilon configuration attributes
+// parameters: i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all attributes are set to valid values,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_l2(
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    bool r_t0_fits = false;
+    bool r_t1_fits = false;
+    bool r_t2_fits = false;
+    bool w_t2_fits = false;
+    uint32_t attr_value;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_l2: Start");
+
+    do
+    {
+        //
+        // NOTE: L2 epsilon valus will only be pushed into attributes by
+        //       this procedure.  Hostboot will run on scan flush (safe) values,
+        //       and runtime values pushed into attributes will be applied
+        //       via winkle image.
+        //
+        // 10012814 = L2 Epsilon Config Register
+        //   0:8  = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //   9:17 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //  18:28 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
+        //  29:35 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target_value+1)
+        //     36 = force t2 (0 = MODE1 = use scope to choose tier,
+        //                    1 = MODE2 = use r_t2 value for all read protection
+        //
+
+        // target read tier2 & write tier2 epsilon values must be representable
+        // in HW storage, error out if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t2,
+            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2,
+            true,
+            r_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from proc_build_smp_check_epsilon (r_t2)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.w_t2,
+            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2,
+            true,
+            w_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from proc_build_smp_check_epsilon (w_t2)");
+            break;
+        }
+
+        // check read tier0, read tier1 target values
+        // don't error if these don't fit, as we will just force use of tier2
+        // in this case
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t0,
+            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0,
+            false,
+            r_t0_fits);
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t1,
+            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1,
+            false,
+            r_t1_fits);
+
+        // set attributes based on unit implementation
+        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T2_EPS");
+        attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2)?
+                      (0):(i_eps_cfg.r_t2+1));
+        rc = FAPI_ATTR_SET(
+            ATTR_L2_R_T2_EPS,
+            NULL,
+            attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T2_EPS)");
+            break;
+        }
+
+        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_W_EPS");
+        attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2)?
+                      (0):(i_eps_cfg.w_t2+1));
+        rc = FAPI_ATTR_SET(
+            ATTR_L2_W_EPS,
+            NULL,
+            attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_W_EPS)");
+            break;
+        }
+
+        // force tier2 if necessary
+        if (!r_t0_fits || !r_t1_fits)
+        {
+            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_FORCE_R_T2_EPS");
+            uint8_t attr_value = PROC_BUILD_SMP_EPSILON_L2_FORCE_T2;
+            rc = FAPI_ATTR_SET(
+                ATTR_L2_FORCE_R_T2_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_FORCE_R_T2_EPS)");
+                break;
+            }
+        }
+        // otherwise, write explicit read tier0, read tier1 attribute values
+        else
+        {
+            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T0_EPS");
+            attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0)?
+                          (0):(i_eps_cfg.r_t0+1));
+            rc = FAPI_ATTR_SET(
+                ATTR_L2_R_T0_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T0_EPS)");
+                break;
+            }
+
+            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T1_EPS");
+            attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1)?
+                          (0):(i_eps_cfg.r_t1+1));
+            rc = FAPI_ATTR_SET(
+                ATTR_L2_R_T1_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T1_EPS)");
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_l2: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set L3 unit epsilon configuration attributes
+// parameters: i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all attributes are set to valid values,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_l3(
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    bool r_t0_fits = false;
+    bool r_t1_fits = false;
+    bool r_t2_fits = false;
+    bool w_t2_fits = false;
+    uint32_t attr_value;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_l3: Start");
+
+    do
+    {
+        //
+        // NOTE: L3 epsilon valus will only be pushed into attributes by
+        //       this procedure.  Hostboot will run on scan flush (safe) values,
+        //       and runtime values pushed into attributes will be applied
+        //       via winkle image.
+        //
+        // 10010829 = L3 Read Epsilon Config Register
+        //    0:8 = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //   9:17 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //  18:28 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
+        //  29:30 = force t2 (00 = MODE1 = use scope to choose tier,
+        //                    01 = MODE2 = use r_t2 value for all read protection
+        //
+        // 1001082A = L3 Write Epsilon Config Register
+        //    0:6 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target value+1)
+        //
+
+        // target read tier2 & write epsilon values must be representable
+        // in HW storage, error if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t2,
+            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2,
+            true,
+            r_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from proc_build_smp_check_epsilon (r_t2)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.w_t2,
+            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2,
+            true,
+            w_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from proc_build_smp_check_epsilon (w_t2)");
+            break;
+        }
+
+        // check read tier0, read tier1 target values
+        // don't error if these don't fit, as we will just force use of tier2
+        // in this case
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t0,
+            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0,
+            false,
+            r_t0_fits);
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t1,
+            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1,
+            false,
+            r_t1_fits);
+
+        // set attributes based on unit implementation
+        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T2_EPS");
+        attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2)?
+                      (0):(i_eps_cfg.r_t2+1));
+        rc = FAPI_ATTR_SET(
+            ATTR_L3_R_T2_EPS,
+            NULL,
+            attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T2_EPS)");
+            break;
+        }
+
+        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_W_EPS");
+        attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2)?
+                      (0):(i_eps_cfg.w_t2+1));
+        rc = FAPI_ATTR_SET(
+            ATTR_L3_W_EPS,
+            NULL,
+            attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_W_EPS");
+            break;
+        }
+
+        // force tier2 if necessary
+        if (!r_t0_fits || !r_t1_fits)
+        {
+            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_FORCE_R_T2_EPS");
+            uint8_t attr_value = PROC_BUILD_SMP_EPSILON_L3_FORCE_T2;
+            rc = FAPI_ATTR_SET(
+                ATTR_L3_FORCE_R_T2_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_FORCE_R_T2_EPS)");
+                break;
+            }
+        }
+        // otherwise, write explicit read tier0, read tier1 attribute values
+        else
+        {
+            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T0_EPS");
+            attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0)?
+                          (0):(i_eps_cfg.r_t0+1));
+            rc = FAPI_ATTR_SET(
+                ATTR_L3_R_T0_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T0_EPS)");
+                break;
+            }
+
+            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T1_EPS");
+            attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1)?
+                          (0):(i_eps_cfg.r_t1+1));
+            rc = FAPI_ATTR_SET(
+                ATTR_L3_R_T1_EPS,
+                NULL,
+                attr_value);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T1_EPS)");
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_l3: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set MCS unit epsilon registers for all configured chiplets
+//           on target chip
+// parameters: i_target  => chip target
+//             i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all settings are programmed correctly,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_mcs(
+    fapi::Target & i_target,
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    bool r_t0_fits = false;
+    bool r_t1_fits = false;
+    bool r_t2_fits = false;
+    bool r_f_fits  = false;
+    ecmdDataBufferBase data(64);
+    std::vector<fapi::Target> mcs_chiplets;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_mcs: Start");
+
+    do
+    {
+        //
+        // 02011816 = MCS Epsilon Register
+        //    0:7 = jitter (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
+        //   8:15 = r_t0   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
+        //  16:23 = r_t1   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
+        //  24:31 = r_t2   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
+        //  32:39 = r_f    (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
+        //
+
+        // all target values must be representable in HW storage, error if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t0,
+            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0,
+            true,
+            r_t0_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t0)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t1,
+            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1,
+            true,
+            r_t1_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t1)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t2,
+            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2,
+            true,
+            r_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t2)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_f,
+            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F,
+            true,
+            r_f_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_f)");
+            break;
+        }
+
+        // form data buffer
+        rc_ecmd |= data.insertFromRight(
+            PROC_BUILD_SMP_EPSILON_MCS_JITTER,
+            MCEPS_JITTER_EPSILON_START_BIT,
+            (MCEPS_JITTER_EPSILON_END_BIT-
+             MCEPS_JITTER_EPSILON_START_BIT+1));
+
+        rc_ecmd |= data.insertFromRight(
+            proc_build_smp_round_ceiling(i_eps_cfg.r_t0, 4)+1,
+            MCEPS_NODAL_EPSILON_START_BIT,
+            (MCEPS_NODAL_EPSILON_END_BIT-
+             MCEPS_NODAL_EPSILON_START_BIT+1));
+
+        rc_ecmd |= data.insertFromRight(
+            proc_build_smp_round_ceiling(i_eps_cfg.r_t1, 4)+1,
+            MCEPS_GROUP_EPSILON_START_BIT,
+            (MCEPS_GROUP_EPSILON_END_BIT-
+             MCEPS_GROUP_EPSILON_START_BIT+1));
+
+        rc_ecmd |= data.insertFromRight(
+            proc_build_smp_round_ceiling(i_eps_cfg.r_t2, 4)+1,
+            MCEPS_SYSTEM_EPSILON_START_BIT,
+            (MCEPS_SYSTEM_EPSILON_END_BIT-
+             MCEPS_SYSTEM_EPSILON_START_BIT+1));
+
+        rc_ecmd |= data.insertFromRight(
+            proc_build_smp_round_ceiling(i_eps_cfg.r_f, 4)+1,
+            MCEPS_FOREIGN_EPSILON_START_BIT,
+            (MCEPS_FOREIGN_EPSILON_END_BIT-
+             MCEPS_FOREIGN_EPSILON_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error 0x%x setting up MCEPS data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // determine configured MCS chiplets
+        rc = fapiGetChildChiplets(i_target,
+                                  fapi::TARGET_TYPE_MCS_CHIPLET,
+                                  mcs_chiplets);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from fapiGetChildChiplets");
+            break;
+
+        }
+
+        // loop over configured MCS chiplets and set epsilon configuration
+        for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin();
+             i != mcs_chiplets.end();
+             i++)
+        {
+            rc = fapiPutScom(*i, MCS_MCEPS_0x02011816, data);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_epsilons_mcs: fapiPutScom error (MCS_MCEPS_0x02011816)");
+                break;
+            }
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_mcs: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set NX CQ (NX/AS) unit epsilon registers
+// parameters: i_target  => chip target
+//             i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all settings are programmed correctly,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_nx(
+    fapi::Target & i_target,
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    bool w_t2_fits = false;
+    ecmdDataBufferBase data(64), mask(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_nx: Start");
+
+    do
+    {
+        //
+        // 0201309D = NX CQ Epsilon Scale register
+        //    0:5 = w_t2 (MAX = all 0s =  448, MIN = 1, HW = target_value/7)
+        //
+
+        // target write tier2 epsilon value must be representable
+        // in HW storage, error out if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.w_t2,
+            PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2,
+            true,
+            w_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_nx: Error from proc_build_smp_check_epsilon (w_t2)");
+            break;
+        }
+
+        // program write epsilon register based on unit implementation
+        uint32_t hw_value = proc_build_smp_round_ceiling(i_eps_cfg.w_t2, 7);
+        if (hw_value == 64)
+        {
+            hw_value = 0;
+        }
+
+        rc_ecmd |= data.insertFromRight(
+            hw_value,
+            NX_CQ_EPSILON_SCALE_EPSILON_START_BIT,
+            (NX_CQ_EPSILON_SCALE_EPSILON_END_BIT-
+             NX_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
+        rc_ecmd |= mask.setBit(
+            NX_CQ_EPSILON_SCALE_EPSILON_START_BIT,
+            (NX_CQ_EPSILON_SCALE_EPSILON_END_BIT-
+             NX_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_nx: Error 0x%x setting up NX CQ Epsilon Scale register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register (use mask to avoid overriding other configuration
+        // settings in register)
+        rc = fapiPutScomUnderMask(i_target,
+                                  NX_CQ_EPS_0x0201309D,
+                                  data,
+                                  mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_nx: fapiPutScomUnderMask error (NX_CQ_EPS_0x0201309D)");
+            break;
+        }
+    } while(0);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_nx: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set HCA unit epsilon registers
+// parameters: i_target  => chip target
+//             i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all settings are programmed correctly,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_hca(
+    fapi::Target & i_target,
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    bool w_t2_fits = false;
+    ecmdDataBufferBase data(64), mask(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_hca: Start");
+
+    do
+    {
+        //
+        // 0201094F = HCA Mode Register
+        //  21:29 = w_t2 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //
+
+        // all target values must be representable in HW storage, error if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.w_t2,
+            PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2,
+            true,
+            w_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_hca: Error from proc_build_smp_check_epsilon (w_t2)");
+            break;
+        }
+
+        // form data buffer
+        rc_ecmd |= data.insertFromRight(
+            ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2)?
+             (0):(i_eps_cfg.w_t2+1)),
+            HCA_MODE_EPSILON_START_BIT,
+            (HCA_MODE_EPSILON_END_BIT-
+             HCA_MODE_EPSILON_START_BIT+1));
+        rc_ecmd |= mask.setBit(
+            HCA_MODE_EPSILON_START_BIT,
+            (HCA_MODE_EPSILON_END_BIT-
+             HCA_MODE_EPSILON_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_hca: Error 0x%x setting up HCA Mode data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register (use mask to avoid overriding other configuration
+        // settings in register)
+        rc = fapiPutScomUnderMask(i_target, HCA_MODE_0x0201094F, data, mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_hca: fapiPutScomUnderMask error (HCA_MODE_0x0201094F)");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_hca: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set CAPP unit epsilon registers
+// parameters: i_target  => chip target
+//             i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all settings are programmed correctly,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_capp(
+    fapi::Target & i_target,
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    bool r_t0_fits = false;
+    bool r_t1_fits = false;
+    bool r_t2_fits = false;
+    bool w_t2_fits = false;
+    ecmdDataBufferBase data(64), mask(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_capp: Start");
+
+    do
+    {
+        //
+        // 0201301B = CAPP CXA Snoop Control register
+        //   3:11 = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //  15:23 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
+        //  25:35 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
+        //      0 = force t2 (0 = MODE1 = use scope to choose tier,
+        //                    0 = MODE2 = use r_t2 value for all read protection
+        //
+        // 02013018 = CAPP APC Master PB Control register
+        //  39:45 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target value+1)
+        //
+
+        // target read tier2 & write tier2 epsilon values must be representable
+        // in HW storage, error out if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t2,
+            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2,
+            true,
+            r_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error from proc_build_smp_check_epsilon (r_t2)");
+            break;
+        }
+
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.w_t2,
+            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2,
+            true,
+            w_t2_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error from proc_build_smp_check_epsilon (w_t2)");
+            break;
+        }
+
+        // check read tier0, read tier1 target values
+        // don't error if these don't fit, as we will just force use of tier2
+        // in this case
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t0,
+            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0,
+            false,
+            r_t0_fits);
+        (void) proc_build_smp_check_epsilon(
+            i_eps_cfg.r_t1,
+            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1,
+            false,
+            r_t1_fits);
+
+        // program write epsilon register based on unit implementation
+        rc_ecmd |= data.insertFromRight(
+            ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2)?
+             (0):(i_eps_cfg.w_t2+1)),
+            CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT,
+            (CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT-
+             CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT+1));
+        rc_ecmd |= mask.setBit(
+            CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT,
+            (CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT-
+             CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error 0x%x setting up CAPP APC Master Control register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register (use mask to avoid overriding other configuration
+        // settings in register)
+        rc = fapiPutScomUnderMask(i_target,
+                                  CAPP_APC_MASTER_PB_CTL_0x02013018,
+                                  data,
+                                  mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP_APC_MASTER_PB_CTL_0x02013018)");
+            break;
+        }
+
+        // program read epsilon register based on unit implementation
+        rc_ecmd = data.flushTo0();
+        rc_ecmd = mask.flushTo0();
+
+        rc_ecmd |= data.insertFromRight(
+            ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2)?
+             (0):(i_eps_cfg.r_t2+1)),
+            CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT,
+            (CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT-
+             CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT+1));
+        rc_ecmd |= mask.setBit(
+            CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT,
+            (CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT-
+             CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT+1));
+
+        // force tier2 if necessary
+        if (!r_t0_fits || !r_t1_fits)
+        {
+            rc_ecmd |= data.writeBit(
+                CAPP_CXA_SNP_READ_EPSILON_MODE_BIT,
+                PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2);
+            rc_ecmd |= mask.setBit(
+                CAPP_CXA_SNP_READ_EPSILON_MODE_BIT);
+        }
+        else
+        {
+            rc_ecmd |= data.insertFromRight(
+                ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0)?
+                 (0):(i_eps_cfg.r_t0+1)),
+                CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT,
+                (CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT-
+                 CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT+1));
+            rc_ecmd |= mask.setBit(
+                CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT,
+                (CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT-
+                 CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT+1));
+
+            rc_ecmd |= data.insertFromRight(
+                ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1)?
+                 (0):(i_eps_cfg.r_t1+1)),
+                CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT,
+                (CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT-
+                 CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT+1));
+            rc_ecmd |= mask.setBit(
+                CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT,
+                (CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT-
+                 CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT+1));
+        }
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error 0x%x setting up CAPP CXA Snoop Control register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register (use mask to avoid overriding other configuration
+        // settings in register)
+        rc = fapiPutScomUnderMask(i_target,
+                                  CAPP_CXA_SNOOP_CTL_0x0201301B,
+                                  data,
+                                  mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP_CXA_SNOOP_CTL_0x0201301B)");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_capp: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: set MCD unit epsilon registers
+// parameters: i_target  => chip target
+//             i_eps_cfg => system epsilon configuration structure
+// returns: ECMD_SUCCESS if all settings are programmed correctly,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons_mcd(
+    fapi::Target & i_target,
+    const proc_build_smp_eps_cfg & i_eps_cfg)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    bool p_fits = false;
+    ecmdDataBufferBase data(64), mask(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons_mcd: Start");
+
+    do
+    {
+        //
+        // 0201340B = MCD Recovery Pre Epsilon Configuration register
+        //  52:63 = p (MAX = all 1s = 66520, MIN = 0, HW = target_value/16)
+        //
+
+        // target pre epsilon value must be representable
+        // in HW storage, error out if not
+        rc = proc_build_smp_check_epsilon(
+            i_eps_cfg.p,
+            PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P,
+            true,
+            p_fits);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcd: Error from proc_build_smp_check_epsilon (p)");
+            break;
+        }
+
+        // program write epsilon register based on unit implementation
+        rc_ecmd |= data.insertFromRight(
+            proc_build_smp_round_ceiling(i_eps_cfg.p, 16),
+            MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT,
+            (MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT-
+             MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT+1));
+        rc_ecmd |= mask.setBit(
+            MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT,
+            (MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT-
+             MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcd: Error 0x%x setting up MCD Recovery Pre Epsilon Configuration register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register (use mask to avoid overriding other configuration
+        // settings in register)
+        rc = fapiPutScomUnderMask(i_target,
+                                  MCD_PRE_EPS_0x0201340B,
+                                  data,
+                                  mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_mcd: fapiPutScomUnderMask error (MCD_PRE_EPS_0x0201340B)");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons_mcd: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: calculate target epsilon settings to apply based on
+//           system configuration
+// parameters: io_smp => structure encapsulating SMP (including system
+//                       frequency/epsilon configuration parameter values),
+//                       target epsilon values will be filled by this subroutine
+// returns: FAPI_RC_SUCCESS if target settings are valid,
+//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
+//              table type/content is detected,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_epsilons(
+    proc_build_smp_system & io_smp)
+{
+    fapi::ReturnCode rc;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_calc_epsilons: Start");
+
+    do
+    {
+        // perform table lookup based on system table type
+        FAPI_DBG("proc_build_smp_calc_epsilons: core floor freq = %d, PB freq = %d, table index = %d",
+                 io_smp.freq_core_floor,
+                 io_smp.freq_pb,
+                 io_smp.core_floor_ratio);
+
+        switch(io_smp.eps_cfg.table_type)
+        {
+            case PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE:
+                if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1)
+                {
+                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T0_HE[io_smp.core_floor_ratio];
+                }
+                else
+                {
+                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T1_HE[io_smp.core_floor_ratio];
+                }
+                io_smp.eps_cfg.r_t1 = PROC_BUILD_SMP_EPSILON_R_T1_HE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.r_t2 = PROC_BUILD_SMP_EPSILON_R_T2_HE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.r_f  = PROC_BUILD_SMP_EPSILON_R_F_HE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_HE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.w_f  = PROC_BUILD_SMP_EPSILON_W_F_HE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.p    = PROC_BUILD_SMP_EPSILON_P_HE[io_smp.core_floor_ratio];
+                break;
+            case PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE:
+                if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1)
+                {
+                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T0_LE[io_smp.core_floor_ratio];
+                }
+                else
+                {
+                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T1_LE[io_smp.core_floor_ratio];
+                }
+                io_smp.eps_cfg.r_t1 = PROC_BUILD_SMP_EPSILON_R_T1_LE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.r_t2 = PROC_BUILD_SMP_EPSILON_R_T2_LE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.r_f  = PROC_BUILD_SMP_EPSILON_R_F_LE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_LE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.w_f  = PROC_BUILD_SMP_EPSILON_W_F_LE[io_smp.core_floor_ratio];
+                io_smp.eps_cfg.p    = PROC_BUILD_SMP_EPSILON_P_LE[io_smp.core_floor_ratio];
+                break;
+            default:
+                FAPI_ERR("proc_build_smp_calc_epsilons: Invalid epsilon table type");
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR);
+                break;
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // dump base epsilon values
+        FAPI_DBG("proc_build_smp_calc_epsilons: Base epsilon values read from table:");
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T0 = %d", io_smp.eps_cfg.r_t0);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T1 = %d", io_smp.eps_cfg.r_t1);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T2 = %d", io_smp.eps_cfg.r_t2);
+        FAPI_DBG("proc_build_smp_calc_epsilons:   R_F = %d", io_smp.eps_cfg.r_f);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  W_T2 = %d", io_smp.eps_cfg.w_t2);
+        FAPI_DBG("proc_build_smp_calc_epsilons:   W_F = %d", io_smp.eps_cfg.w_f);
+        FAPI_DBG("proc_build_smp_calc_epsilons:     P = %d", io_smp.eps_cfg.p);
+
+        // apply guardband to base epsilon values
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.r_t0);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.r_t1);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.r_t2);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.r_f);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.w_t2);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.w_f);
+        proc_build_smp_guardband_epsilon(
+            io_smp.eps_cfg.gb_positive,
+            io_smp.eps_cfg.gb_percentage,
+            io_smp.eps_cfg.p);
+
+        // dump scaled epsilon values
+        FAPI_DBG("proc_build_smp_calc_epsilons: Scaled epsilon values based on %s%d%% guardband:",
+                 (io_smp.eps_cfg.gb_positive)?("+"):("-"),
+                 io_smp.eps_cfg.gb_percentage);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T0 = %d", io_smp.eps_cfg.r_t0);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T1 = %d", io_smp.eps_cfg.r_t1);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T2 = %d", io_smp.eps_cfg.r_t2);
+        FAPI_DBG("proc_build_smp_calc_epsilons:   R_F = %d", io_smp.eps_cfg.r_f);
+        FAPI_DBG("proc_build_smp_calc_epsilons:  W_T2 = %d", io_smp.eps_cfg.w_t2);
+        FAPI_DBG("proc_build_smp_calc_epsilons:   W_F = %d", io_smp.eps_cfg.w_f);
+        FAPI_DBG("proc_build_smp_calc_epsilons:     P = %d", io_smp.eps_cfg.p);
+
+        // check relationship of epsilon counters
+        // rules:
+        //   read tier values are strictly increasing
+        //   read tier2 value is greater than read foreign value
+        //   write tier2 value is greater than write foreign value
+        if ((io_smp.eps_cfg.r_t0 > io_smp.eps_cfg.r_t1) ||
+            (io_smp.eps_cfg.r_t1 > io_smp.eps_cfg.r_t2) ||
+            (io_smp.eps_cfg.r_f  > io_smp.eps_cfg.r_t2) ||
+            (io_smp.eps_cfg.w_f  > io_smp.eps_cfg.w_t2))
+        {
+            FAPI_ERR("proc_build_smp_calc_epsilons: Invalid relationship between base epsilon values");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR);
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_epsilons: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_set_epsilons(
+    proc_build_smp_system & i_smp)
+{
+    fapi::ReturnCode rc;
+    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_epsilons: Start");
+
+    do
+    {
+        // calculate epsilons
+        rc = proc_build_smp_calc_epsilons(i_smp);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_calc_epsilons");
+            break;
+        }
+
+        // set system level attributes
+        // L2
+        rc = proc_build_smp_set_epsilons_l2(i_smp.eps_cfg);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_l2");
+            break;
+        }
+
+        // L3
+        rc = proc_build_smp_set_epsilons_l3(i_smp.eps_cfg);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_l3");
+            break;
+        }
+
+        // process each chip in SMP, program unit epsilon registers
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                fapi::Target target = p_iter->second.chip->this_chip;
+
+                // MCS
+                rc = proc_build_smp_set_epsilons_mcs(target, i_smp.eps_cfg);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_mcs");
+                    break;
+                }
+
+                // NX
+                rc = proc_build_smp_set_epsilons_nx(target, i_smp.eps_cfg);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_nx");
+                    break;
+                }
+
+                // HCA
+                rc = proc_build_smp_set_epsilons_hca(target, i_smp.eps_cfg);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_hca");
+                    break;
+                }
+
+                // CAPP
+                rc = proc_build_smp_set_epsilons_capp(target, i_smp.eps_cfg);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_capp");
+                    break;
+                }
+
+                // MCD
+                rc = proc_build_smp_set_epsilons_mcd(target, i_smp.eps_cfg);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_mcd");
+                    break;
+                }
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_epsilons: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
new file mode 100644
index 000000000..50b244482
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
@@ -0,0 +1,195 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_epsilon.H,v 1.2 2012/09/05 03:11:55 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_epsilon.H
+// *! DESCRIPTION : Epsilon calculation/application functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_EPSILON_H_
+#define _PROC_BUILD_SMP_EPSILON_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp.H"
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+//
+// table of base epsilon values
+//
+
+const uint32_t PROC_BUILD_SMP_EPSILON_MIN_VALUE = 0x1;
+const uint32_t PROC_BUILD_SMP_EPSILON_MAX_VALUE = 0xFFFFFFFF;
+
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = {    6,    6,    7,    8,    9,   17 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = {   42,   44,   46,   49,   53,   75 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = {   85,   87,   89,   92,   96,  118 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[]  = {   57,   59,   61,   64,   68,   90 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[]    = {   30,   31,   31,   32,   34,   41 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[]  = {   13,   13,   14,   15,   16,   23 };
+const uint32_t PROC_BUILD_SMP_EPSILON_P_HE[]    = {  925, 1605, 1605, 1605, 1605, 1605 };
+
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = {    6,    6,    7,    8,    9,   17 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_LE[] = {    6,    6,    7,    8,    9,   17 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_LE[] = {   62,   63,   65,   68,   73,   94 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_F_LE[]  = {   57,   59,   61,   64,   68,   90 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_LE[]    = {    3,    3,    4,    5,    6,   14 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_F_LE[]  = {   13,   13,   14,   15,   16,   23 };
+const uint32_t PROC_BUILD_SMP_EPSILON_P_LE[]    = {  925, 1605, 1605, 1605, 1605, 1605 };
+
+
+//
+// unit specific epsilon range constants
+//
+
+// L2
+const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2 = 2048;
+const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2 = 128;
+
+const uint8_t  PROC_BUILD_SMP_EPSILON_L2_FORCE_T2 = 0x1;
+
+// L3
+const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2 = 2048;
+const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2 = 128;
+
+const uint8_t  PROC_BUILD_SMP_EPSILON_L3_FORCE_T2 = 0x1;
+
+// MCS
+const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0 = 1016;
+const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1 = 1016;
+const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2 = 1016;
+const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F  = 1016;
+
+const uint8_t  PROC_BUILD_SMP_EPSILON_MCS_JITTER = 0x1;
+
+// NX
+const uint32_t PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2 = 448;
+
+// HCA
+const uint32_t PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2 = 512;
+
+// CAPP
+const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2 = 512;
+const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2 = 128;
+
+const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2 = 0x1;
+
+// MCD
+const uint32_t PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P = 65520;
+
+
+//
+// unit specific register field/bit definition constants
+//
+
+// MCS MCEPS register field/bit definitions
+const uint32_t MCEPS_JITTER_EPSILON_START_BIT = 0;
+const uint32_t MCEPS_JITTER_EPSILON_END_BIT = 7;
+const uint32_t MCEPS_NODAL_EPSILON_START_BIT = 8;
+const uint32_t MCEPS_NODAL_EPSILON_END_BIT = 15;
+const uint32_t MCEPS_GROUP_EPSILON_START_BIT = 16;
+const uint32_t MCEPS_GROUP_EPSILON_END_BIT = 23;
+const uint32_t MCEPS_SYSTEM_EPSILON_START_BIT = 24;
+const uint32_t MCEPS_SYSTEM_EPSILON_END_BIT = 31;
+const uint32_t MCEPS_FOREIGN_EPSILON_START_BIT = 32;
+const uint32_t MCEPS_FOREIGN_EPSILON_END_BIT = 39;
+
+// NX CQ Epsilon Scale register field/bit definitions
+const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_START_BIT = 0;
+const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_END_BIT = 5;
+
+// HCA Mode register field/bit definitions
+const uint32_t HCA_MODE_EPSILON_START_BIT = 21;
+const uint32_t HCA_MODE_EPSILON_END_BIT = 29;
+
+// CAPP CXA Snoop Control register field/bit definitions
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT = 3;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT = 11;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT = 15;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT = 23;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT = 25;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT = 35;
+const uint32_t CAPP_CXA_SNP_READ_EPSILON_MODE_BIT = 0;
+
+// CAPP APC Master PB Control register field/bit definitions
+const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT = 39;
+const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT = 45;
+
+// MCD Recovery Pre Epsilon Configuration register field/bit definitions
+const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT = 52;
+const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT = 63;
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: utility function to round to ceiling
+// parameters: i_n => numerator
+//             i_d => denominator
+// returns: ceiling of i_n / i_d (integer)
+//------------------------------------------------------------------------------
+uint32_t proc_build_smp_round_ceiling(
+    uint32_t i_n,
+    uint32_t i_d);
+
+
+//------------------------------------------------------------------------------
+// function: set target epsilon values into system attributes/HW
+// parameters: i_smp => structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if application is successful
+//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
+//              table type/content is detected,
+//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
+//              range given underlying HW storage,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_epsilons(
+    proc_build_smp_system & i_smp);
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_EPSILON_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml
new file mode 100644
index 000000000..0157ffda3
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml
@@ -0,0 +1,112 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_build_smp -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR</rc>
+    <description>Internal Error.  Error encountered adding node to SMP structure.</description>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR</rc>
+    <description>Multiple chips found with identifcal fabric node/chip ID attribute values.</description>
+    <ffdc>NODE_ID</ffdc>
+    <ffdc>CHIP_ID</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR</rc>
+    <description>Unsupported SMP build operation presented.</description>
+    <ffdc>OP</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR</rc>
+    <description>Node or system master chip designation error.</description>
+    <ffdc>OP</ffdc>
+    <ffdc>MASTER_CHIP_SYS_CURR</ffdc>
+    <ffdc>MASTER_CHIP_NODE_CURR</ffdc>
+    <ffdc>FIRST_CHIP_IN_SYS</ffdc>
+    <ffdc>FIRST_CHIP_IN_NODE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR</rc>
+    <description>Target epsilon value exceeds maximum value supported by HW capabilities.</description>
+    <ffdc>VALUE</ffdc>
+    <ffdc>MAX_HW_VALUE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR</rc>
+    <description>Invalid epsilon table type or content detected.</description>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR</rc>
+    <description>Command rate pacing table lookup error.</description>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR</rc>
+    <description>Unsupported core floor to PB frequency ratio.</description>
+    <ffdc>FREQ_PB</ffdc>
+    <ffdc>FREQ_CORE_FLOOR</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR</rc>
+    <description>Unsupported core floor frequency enumerated value.</description>
+    <ffdc>CORE_FLOOR_RATIO</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR</rc>
+    <description>Invalid chips per group configuration detected.</description>
+    <ffdc>SIZE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR</rc>
+    <description>Invalid aggregate link configuration detected.</description>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR</rc>
+    <description>Inconsistent state in hotplug (CURR) shadow copies.</description>
+    <ffdc>ADDRESS0</ffdc>
+    <ffdc>ADDRESS1</ffdc>
+    <ffdc>DATA0</ffdc>
+    <ffdc>DATA1</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_X_CMD_RATE_ERR</rc>
+    <description>Target link command rate value is out of range.</description>
+    <ffdc>CMD_RATE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_A_CMD_RATE_ERR</rc>
+    <description>Target link command rate value is out of range.</description>
+    <ffdc>CMD_RATE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_F_CMD_RATE_ERR</rc>
+    <description>Target link command rate value is out of range.</description>
+    <ffdc>CMD_RATE</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH</rc>
+    <description>Status mismatch detected on ADU operation executed for SMP configuration.</description>
+    <ffdc>STATUS_DATA</ffdc>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C
new file mode 100644
index 000000000..1f4051fa2
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C
@@ -0,0 +1,1379 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_ab.C,v 1.3 2012/09/24 05:00:55 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_ab.C
+// *! DESCRIPTION : Fabric configuration (hotplug, AB) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp_fbc_ab.H"
+#include "proc_build_smp_epsilon.H"
+#include "proc_build_smp_adu.H"
+
+extern "C" {
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: read PB A Link Framer Configuration register and determine
+//           OW packing setup
+// parameters: i_smp_chip        => structure encapsulating SMP chip
+//             o_owpack          => OW packing enabled?
+//             o_owpack_priority => OW pack priority enabled?
+// returns: FAPI_RC_SUCCESS if SCOM is successful & output pack values are
+//              valid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_get_a_owpack_config(
+    const proc_build_smp_chip& i_smp_chip,
+    bool & o_owpack,
+    bool & o_owpack_priority)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_get_a_owpack_config: Start");
+
+    do
+    {
+        // read PB A Link Framer Configuration register
+        rc = fapiGetScom(i_smp_chip.chip->this_chip,
+                         PB_A_FMR_CFG_0x08010813,
+                         data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_get_a_owpack_config: fapiGetScom error (PB_A_FMR_CFG_0x08010813)");
+            break;
+        }
+
+        // set outputs
+        o_owpack = data.isBitSet(PB_A_FMR_CFG_OW_PACK_BIT);
+        o_owpack_priority = data.isBitSet(PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT);
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_get_a_owpack_config: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: read PB F Link Framer Configuration register and determine
+//           OW packing setup
+// parameters: i_smp_chip        => structure encapsulating SMP chip
+//             o_owpack          => OW packing enabled?
+//             o_owpack_priority => OW pack priority enabled?
+// returns: FAPI_RC_SUCCESS if SCOM is successful & output pack values are
+//              valid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_get_f_owpack_config(
+    const proc_build_smp_chip& i_smp_chip,
+    bool & o_owpack,
+    bool & o_owpack_priority)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_get_f_owpack_config: Start");
+
+    do
+    {
+        // read PB A Link Framer Configuration register
+        rc = fapiGetScom(i_smp_chip.chip->this_chip,
+                         PB_F_FMR_CFG_0x09010813,
+                         data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_get_f_owpack_config: fapiGetScom error (PB_F_FMR_CFG_0x09010813)");
+            break;
+        }
+
+        // set outputs
+        o_owpack = data.isBitSet(PB_F_FMR_CFG_OW_PACK_BIT);
+        o_owpack_priority = data.isBitSet(PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT);
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_get_f_owpack_config: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: read PB Link Mode register and extract per-link training delays
+// parameters: i_smp_chip         => structure encapsulating SMP chip
+//             i_num_links        => number of links to process
+//             i_scom_addr        => address for SCOM register containing link
+//                                   delay values
+//             i_link_delay_start => per-link delay field start bit offsets
+//             i_link_delay_end   => per-link delay field end bit offsets
+//             o_link_delays      => array of link round trip delay values
+// returns: FAPI_RC_SUCCESS if SCOM is successful & output link delays are
+//              valid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_get_link_delays(
+    const proc_build_smp_chip& i_smp_chip,
+    const uint8_t i_num_links,
+    const uint32_t i_scom_addr,
+    const uint32_t i_link_delay_start[],
+    const uint32_t i_link_delay_end[],
+    uint16_t o_link_delays[])
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_get_link_delays: Start");
+
+    do
+    {
+        // read PB Link Mode register
+        rc = fapiGetScom(i_smp_chip.chip->this_chip,
+                         i_scom_addr,
+                         data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_get_link_delays: fapiGetScom error (%08X)",
+                     i_scom_addr);
+            break;
+        }
+
+        // extract & return link training delays
+        for (uint8_t l = 0; l < i_num_links; l++)
+        {
+            rc_ecmd |= data.extractToRight(
+                &(o_link_delays[l]),
+                i_link_delay_start[l],
+                (i_link_delay_end[l]-
+                 i_link_delay_start[l]+1));
+
+            if (rc_ecmd)
+            {
+                FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer",
+                         rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_get_link_delays: Start");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: determine link address/data & aggregate mode setup
+// parameters: i_smp_chip         => structure encapsulating SMP chip
+//             i_num_links        => number of links to process
+//             i_num_ids          => maximum number of ID values
+//             i_scom_addr        => address for SCOM register containing link
+//                                   delay values
+//             i_link_delay_start => per-link delay field start bit offsets
+//             i_link_delay_end   => per-link delay field end bit offsets
+//             i_link_en          => per-link enable values
+//             i_link_id          => per-link ID values
+//             o_link_addr_dis    => per-link address disable values
+//                                   (true=address only, false=address/data)
+//             o_link_aggregate   => enable aggregate link mode?
+// returns: FAPI_RC_SUCCESS if output values are valid,
+//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
+//              specifies invalid aggregate link setup,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_link_setup(
+    const proc_build_smp_chip& i_smp_chip,
+    const uint8_t i_num_links,
+    const uint8_t i_num_ids,
+    const uint32_t i_scom_addr,
+    const uint32_t i_link_delay_start[],
+    const uint32_t i_link_delay_end[],
+    const bool i_link_en[],
+    const uint8_t i_link_id[],
+    bool o_link_addr_dis[],
+    bool &o_link_aggregate)
+{
+    fapi::ReturnCode rc;
+    // mark precisely which links target each ID
+    bool id_active[i_num_ids][i_num_links];
+    // mark number of links targeting each ID
+    uint8_t id_active_count[i_num_ids];
+    // link round trip delay values
+    uint16_t link_delays[i_num_links];
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_calc_link_setup: Start");
+
+    do
+    {
+        // init local arrays
+        for (uint8_t id = 0; id < i_num_ids; id++)
+        {
+            id_active_count[id] = 0;
+            for (uint8_t l = 0; l < i_num_links; l++)
+            {
+                id_active[id][l] = false;
+            }
+        }
+
+        // process all links
+        for (uint8_t l = 0; l < i_num_links; l++)
+        {
+            // mark link ID
+            if (i_link_en[l])
+            {
+                id_active_count[i_link_id[l]]++;
+                id_active[i_link_id[l]][l] = true;
+            }
+            // set default value for link address disable (enable coherency)
+            o_link_addr_dis[l] = false;
+        }
+
+        // calculate aggregate setting, check for errors
+        o_link_aggregate = false;
+        for (uint8_t id = 0; id < i_num_ids; id++)
+        {
+            // more than one link pointed at current destination ID
+            if (id_active_count[id] > 1)
+            {
+                // design only supports one set of aggregate links per chip
+                if (o_link_aggregate)
+                {
+                    FAPI_ERR("proc_build_smp_calc_link_setup: Invalid aggregate link configuration");
+                    FAPI_SET_HWP_ERROR(
+                        rc,
+                        RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR);
+                    break;
+                }
+                o_link_aggregate = true;
+
+                // flip default value for link address disable
+                // (disable coherency)
+                for (uint8_t l = 0; l < i_num_links; l++)
+                {
+                    if (id_active[id][l])
+                    {
+                        o_link_addr_dis[l] = true;
+                    }
+                }
+
+                // select link with the lowest round trip latency value
+                // to carry coherency
+                rc = proc_build_smp_get_link_delays(i_smp_chip,
+                                                    i_num_links,
+                                                    i_scom_addr,
+                                                    i_link_delay_start,
+                                                    i_link_delay_end,
+                                                    link_delays);
+                if (rc)
+                {
+                    FAPI_ERR("proc_build_smp_calc_link_setup: Error from proc_build_smp_get_link_delays");
+                    break;
+                }
+
+                // search link delays to find smallest value
+                uint8_t coherent_link_id = 0;
+                uint16_t min_delay = 0xFFFF;
+                for (uint8_t l = 0; l < i_num_links; l++)
+                {
+                    if (i_link_en[l] && (link_delays[l] <= min_delay))
+                    {
+                        coherent_link_id = l;
+                        min_delay = link_delays[l];
+                    }
+                }
+
+                // assign this link to carry coherency
+                o_link_addr_dis[coherent_link_id] = false;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_link_setup: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to calculate X link reflected command rate
+// parameters: i_freq_x      => X-bus frequency
+//             i_freq_pb     => PB frequency
+//             i_x_is_8B     => boolean representing X bus width
+//                              (true=8B, false=4B)
+//             i_x_aggregate => X aggregate mode enabled?
+//             o_x_cmd_rate  => output X link command rate
+// returns: FAPI_RC_SUCCESS if output command rate is in range,
+//          else RC_PROC_BUILD_SMP_X_CMD_RATE_ERR
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_x_cmd_rate(
+    const uint32_t i_freq_x,
+    const uint32_t i_freq_pb,
+    const bool i_x_is_8B,
+    const bool i_x_aggregate,
+    uint8_t & o_x_cmd_rate)
+{
+    fapi::ReturnCode rc;
+    uint32_t n = i_freq_pb;
+    uint32_t d = i_freq_x / 2;
+    uint32_t cmd_rate;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_calc_x_cmd_rate: Start");
+
+    do
+    {
+        if (i_x_is_8B)
+        {
+            d *= 2;
+        }
+
+        if (i_x_aggregate)
+        {
+            n *= 5;
+        }
+        else
+        {
+            n *= 7;
+        }
+
+        cmd_rate = proc_build_smp_round_ceiling(n, d);
+        if ((cmd_rate < PB_HPX_MODE_X_CMD_RATE_MIN_VALUE) ||
+            (cmd_rate > PB_HPX_MODE_X_CMD_RATE_MAX_VALUE))
+        {
+            FAPI_ERR("proc_build_smp_calc_x_cmd_rate: X link command rate is out of range");
+            const uint32_t & CMD_RATE = cmd_rate;
+            FAPI_SET_HWP_ERROR(rc,
+                               RC_PROC_BUILD_SMP_X_CMD_RATE_ERR);
+            break;
+        }
+    } while(0);
+
+    o_x_cmd_rate = (uint8_t) cmd_rate;
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_x_cmd_rate: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to calculate A link reflected command rate
+// parameters: i_freq_a             => A-bus frequency
+//             i_freq_pb            => PB frequency
+//             i_a_ow_pack          => A link OW packing enabled?
+//             i_a_ow_pack_priority => A link OW packing priority set?
+//             i_a_aggregate        => A aggregate mode enabled?
+//             o_a_cmd_rate         => output A link command rate
+// returns: FAPI_RC_SUCCESS if output command rate is in range,
+//          else RC_PROC_BUILD_SMP_A_CMD_RATE_ERR
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_a_cmd_rate(
+    const uint32_t i_freq_a,
+    const uint32_t i_freq_pb,
+    const bool i_a_ow_pack,
+    const bool i_a_ow_pack_priority,
+    const bool i_a_aggregate,
+    uint8_t & o_a_cmd_rate)
+{
+    fapi::ReturnCode rc;
+    uint32_t n = i_freq_pb;
+    uint32_t d = i_freq_a / 4;
+    uint32_t n_ow_pack = 0;
+    uint32_t cmd_rate;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_calc_a_cmd_rate: Start");
+
+    do
+    {
+        if (i_a_ow_pack)
+        {
+            n_ow_pack = (i_a_ow_pack_priority?1:0) + 3;
+        }
+        if (i_a_aggregate)
+        {
+            n_ow_pack += 3;
+        }
+        else
+        {
+            n_ow_pack += 4;
+        }
+
+        n *= (2 * n_ow_pack);
+
+        cmd_rate = proc_build_smp_round_ceiling(n, d);
+        if ((cmd_rate < PB_HP_MODE_A_CMD_RATE_MIN_VALUE) ||
+            (cmd_rate > PB_HP_MODE_A_CMD_RATE_MAX_VALUE))
+        {
+            FAPI_ERR("proc_build_smp_calc_a_cmd_rate: A link command rate is out of range");
+            const uint32_t & CMD_RATE = cmd_rate;
+            FAPI_SET_HWP_ERROR(rc,
+                               RC_PROC_BUILD_SMP_A_CMD_RATE_ERR);
+            break;
+        }
+    } while(0);
+
+    o_a_cmd_rate = (uint8_t) cmd_rate;
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_a_cmd_rate: Start");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to calculate F link reflected command rate
+// parameters: i_freq_f             => F-bus frequency
+//             i_freq_pb            => PB frequency
+//             i_f_ow_pack          => F link OW packing enabled?
+//             i_f_ow_pack_priority => F link OW packing priority set?
+//             i_f_aggregate        => F aggregate mode enabled?
+//             o_f_cmd_rate         => output F link command rate
+// returns: FAPI_RC_SUCCESS if output command rate is in range,
+//          else RC_PROC_BUILD_SMP_F_CMD_RATE_ERR
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_f_cmd_rate(
+    const uint32_t i_freq_f,
+    const uint32_t i_freq_pb,
+    const bool i_f_ow_pack,
+    const bool i_f_ow_pack_priority,
+    const bool i_f_aggregate,
+    uint8_t & o_f_cmd_rate)
+{
+    fapi::ReturnCode rc;
+    uint32_t n = i_freq_pb;
+    uint32_t d = i_freq_f;
+    uint32_t n_ow_pack = 0;
+    uint32_t cmd_rate;
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_f_cmd_rate: Start");
+
+    do
+    {
+        if (i_f_ow_pack)
+        {
+            n_ow_pack = (i_f_ow_pack_priority?1:0) + 3;
+        }
+        if (i_f_aggregate)
+        {
+            n_ow_pack += 3;
+            n_ow_pack *= 30;
+        }
+        else
+        {
+            n_ow_pack += 4;
+            n_ow_pack *= 29;
+        }
+
+        n *= (2 * n_ow_pack);
+        d *= 25;
+
+        cmd_rate = proc_build_smp_round_ceiling(n, d);
+        if ((cmd_rate < PB_HP_MODE_F_CMD_RATE_MIN_VALUE) ||
+            (cmd_rate > PB_HP_MODE_F_CMD_RATE_MAX_VALUE))
+        {
+            FAPI_ERR("proc_build_smp_calc_f_cmd_rate: F link command rate is out of range");
+            const uint32_t & CMD_RATE = cmd_rate;
+            FAPI_SET_HWP_ERROR(rc,
+                               RC_PROC_BUILD_SMP_F_CMD_RATE_ERR);
+            break;
+        }
+
+    } while(0);
+
+    o_f_cmd_rate = (uint8_t) cmd_rate;
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_f_cmd_rate: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to program set of PB hotplug registers
+// parameters: i_smp_chip      => structure encapsulating SMP chip
+//             i_curr_not_next => choose CURR/NEXT register set (true=CURR,
+//                                false=NEXT)
+//             i_hp_not_hpx    => choose HP/HPX register set (true=HP,
+//                                false=HPX)
+//             i_data          => data buffer containing write data
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_hotplug_reg(
+    const proc_build_smp_chip& i_smp_chip,
+    const bool i_curr_not_next,
+    const bool i_hp_not_hpx,
+    ecmdDataBufferBase& i_data)
+{
+    fapi::ReturnCode rc;
+    uint32_t scom_addr;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_hotplug_reg: Start");
+
+    // write west/center/east register copies
+    for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
+    {
+        // set target scom address based on input parameters
+        if (i_curr_not_next)
+        {
+            if (i_hp_not_hpx)
+            {
+                scom_addr = PB_HP_MODE_CURR_SHADOWS[r];
+            }
+            else
+            {
+                scom_addr = PB_HPX_MODE_CURR_SHADOWS[r];
+            }
+        }
+        else
+        {
+            if (i_hp_not_hpx)
+            {
+                scom_addr = PB_HP_MODE_NEXT_SHADOWS[r];
+            }
+            else
+            {
+                scom_addr = PB_HPX_MODE_NEXT_SHADOWS[r];
+            }
+        }
+
+        // write register
+        rc = fapiPutScom(i_smp_chip.chip->this_chip,
+                         scom_addr,
+                         i_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_hotplug_reg: fapiPutScom error (%08X)",
+                     scom_addr);
+            break;
+        }
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_hotplug_reg: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg(
+    const proc_build_smp_chip& i_smp_chip,
+    const bool i_hp_not_hpx,
+    ecmdDataBufferBase& o_data)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_get_hotplug_curr_reg: Start");
+
+    // check consistency of west/center/east register copies
+    for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
+    {
+        // get current (working) register
+        rc = fapiGetScom(i_smp_chip.chip->this_chip,
+                         ((i_hp_not_hpx)?
+                          (PB_HP_MODE_CURR_SHADOWS[r]):
+                          (PB_HPX_MODE_CURR_SHADOWS[r])),
+                         data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: fapiGetScom error (%08X)",
+                     ((i_hp_not_hpx)?
+                      (PB_HP_MODE_CURR_SHADOWS[r]):
+                      (PB_HPX_MODE_CURR_SHADOWS[r])));
+            break;
+        }
+
+        // raise error if shadow copies aren't equal
+        if ((r != 0) &&
+            (o_data != data))
+        {
+            FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: Shadow copies are not equivalent");
+            const uint32_t& ADDRESS0 = ((i_hp_not_hpx)?
+                                        (PB_HP_MODE_CURR_SHADOWS[r-1]):
+                                        (PB_HPX_MODE_CURR_SHADOWS[r-1]));
+            const uint32_t& ADDRESS1 = ((i_hp_not_hpx)?
+                                        (PB_HP_MODE_CURR_SHADOWS[r]):
+                                        (PB_HPX_MODE_CURR_SHADOWS[r]));
+            const uint64_t& DATA0 = o_data.getDoubleWord(0);
+            const uint64_t& DATA1 = data.getDoubleWord(0);
+            FAPI_SET_HWP_ERROR(
+                rc,
+                RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR);
+            break;
+        }
+
+        // set output (will be used to compare with next HW read)
+        data.copy(o_data);
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_get_hotplug_curr_reg: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: reset (copy CURR->NEXT) PB Hotplug Mode register
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_reset_pb_hp_mode(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_reset_pb_hp_mode: Start");
+
+    do
+    {
+        // read CURR state
+        rc = proc_build_smp_get_hotplug_curr_reg(i_smp_chip,
+                                                 true,
+                                                 data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_reset_pb_hp_mode: proc_build_smp_get_hotplug_curr_reg");
+            break;
+        }
+
+        // write NEXT state
+        rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                            false,
+                                            true,
+                                            data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_reset_pb_hp_mode: proc_build_smp_set_hotplug_reg");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_reset_pb_hp_mode: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB Hotplug Mode register
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP topology
+//             i_set_curr => set CURR register set?
+//             i_set_next => set NEXT register set?
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
+//              specifies invalid aggregate link setup,
+//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
+//              is invalid,
+//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
+//              is invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_pb_hp_mode(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_system& i_smp,
+    const bool i_set_curr,
+    const bool i_set_next)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+    // set of per-link destination chip targets
+    fapi::Target * a_target[PROC_FAB_SMP_NUM_A_LINKS];
+    // per-link enables
+    bool a_en[PROC_FAB_SMP_NUM_A_LINKS];
+    bool f_en[PROC_FAB_SMP_NUM_F_LINKS];
+    // per-link destination IDs
+    uint8_t a_id[PROC_FAB_SMP_NUM_A_LINKS];
+    uint8_t f_id[PROC_FAB_SMP_NUM_F_LINKS];
+    // per-link address disable values
+    bool a_addr_dis[PROC_FAB_SMP_NUM_A_LINKS];
+    bool f_addr_dis[PROC_FAB_SMP_NUM_F_LINKS];
+    // aggregate link settings
+    bool a_link_aggregate;
+    bool f_link_aggregate;
+    // link ow pack settings
+    bool a_link_owpack;
+    bool a_link_owpack_priority;
+    bool f_link_owpack;
+    bool f_link_owpack_priority;
+    // link command rates
+    uint8_t a_cmd_rate;
+    uint8_t f_cmd_rate;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_pb_hp_mode: Start");
+
+    do
+    {
+        // process all A links
+        a_target[0] = &(i_smp_chip.chip->a0_chip);
+        a_target[1] = &(i_smp_chip.chip->a1_chip);
+        a_target[2] = &(i_smp_chip.chip->a2_chip);
+        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_A_LINKS; l++)
+        {
+            // determine link enable
+            a_en[l] = (a_target[l]->getType() != fapi::TARGET_TYPE_NONE);
+            // determine link ID
+            proc_fab_smp_node_id dest_node_id = FBC_NODE_ID_0;
+            if (a_en[l])
+            {
+                rc = proc_fab_smp_get_node_id_attr(a_target[l], dest_node_id);
+                if (rc)
+                {
+                    FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_fab_smp_get_node_id_attr");
+                    break;
+                }
+            }
+            a_id[l] = (uint8_t) dest_node_id;
+        }
+        if (rc)
+        {
+            break;
+        }
+
+
+        // process all F links
+        f_en[0] = i_smp_chip.chip->enable_f0;
+        f_id[0] = i_smp_chip.chip->f0_node_id;
+        f_en[1] = i_smp_chip.chip->enable_f1;
+        f_id[1] = i_smp_chip.chip->f1_node_id;
+
+        // determine address/data assignents & aggregate mode programming
+        rc = proc_build_smp_calc_link_setup(i_smp_chip,
+                                            PROC_FAB_SMP_NUM_A_LINKS,
+                                            PROC_FAB_SMP_NUM_NODE_IDS,
+                                            PB_A_MODE_0x0801080A,
+                                            PB_A_MODE_LINK_DELAY_START_BIT,
+                                            PB_A_MODE_LINK_DELAY_END_BIT,
+                                            a_en,
+                                            a_id,
+                                            a_addr_dis,
+                                            a_link_aggregate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (A)");
+            break;
+        }
+
+        rc = proc_build_smp_calc_link_setup(i_smp_chip,
+                                            PROC_FAB_SMP_NUM_F_LINKS,
+                                            PROC_FAB_SMP_NUM_NODE_IDS,
+                                            PB_IOF_MODE_0x09011C0A,
+                                            PB_IOF_MODE_LINK_DELAY_START_BIT,
+                                            PB_IOF_MODE_LINK_DELAY_END_BIT,
+                                            f_en,
+                                            f_id,
+                                            f_addr_dis,
+                                            f_link_aggregate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (F)");
+            break;
+        }
+
+        // determine link command rates
+        rc = proc_build_smp_get_a_owpack_config(i_smp_chip,
+                                                a_link_owpack,
+                                                a_link_owpack_priority);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_a_owpack_config");
+            break;
+        }
+
+        rc = proc_build_smp_calc_a_cmd_rate(i_smp.freq_a,
+                                            i_smp.freq_pb,
+                                            a_link_owpack,
+                                            a_link_owpack_priority,
+                                            a_link_aggregate,
+                                            a_cmd_rate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate");
+            break;
+        }
+
+        rc = proc_build_smp_get_f_owpack_config(i_smp_chip,
+                                                f_link_owpack,
+                                                f_link_owpack_priority);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_f_owpack_config");
+            break;
+        }
+
+        rc = proc_build_smp_calc_f_cmd_rate(i_smp.freq_pcie,
+                                            i_smp.freq_pb,
+                                            f_link_owpack,
+                                            f_link_owpack_priority,
+                                            f_link_aggregate,
+                                            f_cmd_rate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate");
+            break;
+        }
+
+        // build data buffer with per-link values
+        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_A_LINKS; l++)
+        {
+            // pb_cfg_link_a#_en
+            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_A_EN_BIT[l],
+                                     a_en[l]?1:0);
+
+            // pb_cfg_link_na#_addr_dis
+            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_A_ADDR_DIS_BIT[l],
+                                     a_addr_dis[l]?1:0);
+            // pb_cfg_link_a#_chipid
+            rc_ecmd |= data.insertFromRight(
+                a_id[l],
+                PB_HP_MODE_LINK_A_ID_START_BIT[l],
+                (PB_HP_MODE_LINK_A_ID_END_BIT[l]-
+                 PB_HP_MODE_LINK_A_ID_START_BIT[l]+1));
+        }
+
+        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
+        {
+            // pb_cfg_link_f#_master
+            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_MASTER_BIT[l],
+                                     f_en[l]?1:0);
+
+            // pb_cfg_link_f#_en
+            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_EN_BIT[l],
+                                     f_en[l]?1:0);
+
+            // pb_cfg_link_nf#_addr_dis
+            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_ADDR_DIS_BIT[l],
+                                     f_addr_dis[l]?1:0);
+
+            // pb_cfg_link_f#_chipid
+            rc_ecmd |= data.insertFromRight(
+                f_id[l],
+                PB_HP_MODE_LINK_F_ID_START_BIT[l],
+                (PB_HP_MODE_LINK_F_ID_END_BIT[l]-
+                 PB_HP_MODE_LINK_F_ID_START_BIT[l]+1));
+
+            // pb_cfg_p#_x8tok
+            rc_ecmd |= data.writeBit(
+                PB_HP_MODE_PCIE_NOT_DSMP_BIT[l],
+                i_smp_chip.pcie_not_f_link[l]);
+        }
+
+        // pb_cfg_master_chip
+        rc_ecmd |= data.writeBit(PB_HP_MODE_MASTER_CHIP_BIT,
+                                 i_smp_chip.master_chip_sys_next?1:0);
+
+        // pb_cfg_a_aggregate
+        rc_ecmd |= data.writeBit(PB_HP_MODE_A_AGGREGATE_BIT,
+                                 a_link_aggregate?1:0);
+
+        // pb_cfg_tm_master
+        rc_ecmd |= data.writeBit(PB_HP_MODE_TM_MASTER_BIT,
+                                 i_smp_chip.master_chip_sys_next?1:0);
+
+        // pb_cfg_chg_rate_gp_master
+        rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT,
+                                 i_smp_chip.master_chip_node_next?1:0);
+
+        // pb_cfg_chg_rate_sp_master
+        rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_SP_MASTER_BIT,
+                                 i_smp_chip.master_chip_sys_next?1:0);
+
+        // pb_cfg_pump_mode
+        rc_ecmd |= data.writeBit(PB_HP_MODE_PUMP_MODE_BIT,
+            (i_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE2)?1:0);
+
+        // pb_cfg_single_mc
+        rc_ecmd |= data.writeBit(PB_HP_MODE_SINGLE_MC_BIT,
+            (i_smp.all_mcs_interleaved == false)?1:0);
+
+        // pb_cfg_dcache_capp_mode
+        rc_ecmd |= data.writeBit(PB_HP_MODE_DCACHE_CAPP_MODE_BIT,
+                                 PB_HP_MODE_DCACHE_CAPP_EN?1:0);
+
+        // pb_cfg_a_cmd_rate
+        rc_ecmd |= data.insertFromRight(
+            a_cmd_rate,
+            PB_HP_MODE_A_CMD_RATE_START_BIT,
+            (PB_HP_MODE_A_CMD_RATE_END_BIT-
+             PB_HP_MODE_A_CMD_RATE_START_BIT+1));
+
+        // pb_cfg_a_gather_enable
+        rc_ecmd |= data.writeBit(PB_HP_MODE_A_GATHER_ENABLE_BIT,
+                                 PB_HP_MODE_A_GATHER_ENABLE?1:0);
+
+        // pb_cfg_a_dly_cnt
+        rc_ecmd |= data.insertFromRight(
+            PB_HP_MODE_A_GATHER_DLY_CNT,
+            PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT,
+            (PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT-
+             PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT+1));
+
+        // pb_cfg_gather_enable
+        rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT,
+                                 PB_HP_MODE_GATHER_ENABLE?1:0);
+
+        // pb_cfg_f_aggregate
+        rc_ecmd |= data.writeBit(PB_HP_MODE_F_AGGREGATE_BIT,
+                                 f_link_aggregate?1:0);
+
+        // pb_cfg_f_cmd_rate
+        rc_ecmd |= data.insertFromRight(
+            f_cmd_rate,
+            PB_HP_MODE_F_CMD_RATE_START_BIT,
+            (PB_HP_MODE_F_CMD_RATE_END_BIT-
+             PB_HP_MODE_F_CMD_RATE_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error 0x%x setting up PB Hotplug Mode register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write current (working) registers
+        if (i_set_curr)
+        {
+            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                                true,
+                                                true,
+                                                data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_set_hotplug_reg (CURR)");
+                break;
+            }
+        }
+
+        // write next (switch) registers
+        if (i_set_next)
+        {
+            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                                false,
+                                                true,
+                                                data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_set_hotplug_reg (NEXT)");
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_pb_hp_mode: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: reset (copy CURR->NEXT) PB Hotplug Extension Mode register
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_reset_pb_hpx_mode(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_reset_pb_hpx_mode: Start");
+
+    do
+    {
+        // read CURR state
+        rc = proc_build_smp_get_hotplug_curr_reg(i_smp_chip,
+                                                 false,
+                                                 data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_reset_pb_hpx_mode: proc_build_smp_get_hotplug_curr_reg");
+            break;
+        }
+
+        // write NEXT state
+        rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                            false,
+                                            false,
+                                            data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_reset_pb_hpx_mode: proc_build_smp_set_hotplug_reg");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_reset_pb_hpx_mode: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB Hotplug Extension Mode register
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP topology
+//             i_set_curr => set CURR register set?
+//             i_set_next => set NEXT register set?
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
+//              specifies invalid aggregate link setup,
+//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
+//              is invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_pb_hpx_mode(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_system& i_smp,
+    const bool i_set_curr,
+    const bool i_set_next)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+    // set of per-link destination chip targets
+    fapi::Target * x_target[PROC_FAB_SMP_NUM_X_LINKS];
+    // per-link enables
+    bool x_en[PROC_FAB_SMP_NUM_X_LINKS];
+    // per-link destination IDs
+    uint8_t x_id[PROC_FAB_SMP_NUM_X_LINKS];
+    // per-link address disable values
+    bool x_addr_dis[PROC_FAB_SMP_NUM_X_LINKS];
+    // aggregate link setting
+    bool x_link_aggregate;
+    // link command rate
+    uint8_t x_cmd_rate;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_pb_hpx_mode: Start");
+
+    do
+    {
+        // process all links
+        x_target[0] = &(i_smp_chip.chip->x0_chip);
+        x_target[1] = &(i_smp_chip.chip->x1_chip);
+        x_target[2] = &(i_smp_chip.chip->x2_chip);
+        x_target[3] = &(i_smp_chip.chip->x3_chip);
+        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_X_LINKS; l++)
+        {
+            // determine link enable
+            x_en[l] = (x_target[l]->getType() != fapi::TARGET_TYPE_NONE);
+            // determine link ID
+            proc_fab_smp_chip_id dest_chip_id = FBC_CHIP_ID_0;
+            if (x_en[l])
+            {
+                rc = proc_fab_smp_get_chip_id_attr(x_target[l], dest_chip_id);
+                if (rc)
+                {
+                    FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_fab_smp_get_chip_id_attr");
+                    break;
+                }
+            }
+            x_id[l] = (uint8_t) dest_chip_id;
+        }
+        if (rc)
+        {
+            break;
+        }
+
+        // determine address/data assignents & aggregate mode programming
+        rc = proc_build_smp_calc_link_setup(i_smp_chip,
+                                            PROC_FAB_SMP_NUM_X_LINKS,
+                                            PROC_FAB_SMP_NUM_CHIP_IDS,
+                                            PB_X_MODE_0x04010C0A,
+                                            PB_X_MODE_LINK_DELAY_START_BIT,
+                                            PB_X_MODE_LINK_DELAY_END_BIT,
+                                            x_en,
+                                            x_id,
+                                            x_addr_dis,
+                                            x_link_aggregate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_link_setup (X)");
+            break;
+        }
+
+        // determine link command rate
+        rc = proc_build_smp_calc_x_cmd_rate(i_smp.freq_x,
+                                            i_smp.freq_pb,
+                                            i_smp.x_bus_8B,
+                                            x_link_aggregate,
+                                            x_cmd_rate);
+        if (rc)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_x_cmd_rate");
+            break;
+        }
+
+        // build data buffer with per-link values
+        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_X_LINKS; l++)
+        {
+            // pb_cfg_link_x#_en
+            rc_ecmd |= data.writeBit(PB_HPX_MODE_LINK_X_EN_BIT[l],
+                                     x_en[l]?1:0);
+
+            // pb_cfg_link_nx#_addr_dis
+            rc_ecmd |= data.writeBit(PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[l],
+                                     x_addr_dis[l]?1:0);
+
+            // pb_cfg_link_x#_chipid
+            rc_ecmd |= data.insertFromRight(
+                x_id[l],
+                PB_HPX_MODE_LINK_X_CHIPID_START_BIT[l],
+                (PB_HPX_MODE_LINK_X_CHIPID_END_BIT[l]-
+                 PB_HPX_MODE_LINK_X_CHIPID_START_BIT[l]+1));
+        }
+
+        // pb_cfg_x_aggregate
+        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_AGGREGATE_BIT,
+                                 x_link_aggregate);
+
+        // pb_cfg_x_indirect_en
+        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_INDIRECT_EN_BIT,
+                                 PB_HPX_MODE_X_INDIRECT_EN?1:0);
+
+        // pb_cfg_x_gather_enable
+        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_GATHER_ENABLE_BIT,
+                                 PB_HPX_MODE_X_GATHER_ENABLE?1:0);
+
+        // pb_cfg_x_dly_cnt
+        rc_ecmd |= data.insertFromRight(
+            PB_HPX_MODE_X_GATHER_DLY_CNT,
+            PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT,
+            (PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT-
+             PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT+1));
+
+        // pb_cfg_x_onnode_12queues
+        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_ONNODE_12QUEUES_BIT,
+                                 PB_HPX_MODE_X_ONNODE_12QUEUES?1:0);
+
+        // pb_cfg_x_cmd_rate
+        rc_ecmd |= data.insertFromRight(
+            x_cmd_rate,
+            PB_HPX_MODE_X_CMD_RATE_START_BIT,
+            (PB_HPX_MODE_X_CMD_RATE_END_BIT-
+             PB_HPX_MODE_X_CMD_RATE_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error 0x%x setting up PB Hotplug Extension Mode register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write current (working) registers
+        if (i_set_curr)
+        {
+            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                                true,
+                                                false,
+                                                data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_set_hotplug_reg (CURR)");
+                break;
+            }
+        }
+
+        // write next (switch) registers
+        if (i_set_next)
+        {
+            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
+                                                false,
+                                                false,
+                                                data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_set_hotplug_reg (NEXT)");
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_pb_hpx_mode: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_set_fbc_ab(
+    proc_build_smp_system& i_smp,
+    const proc_build_smp_operation i_op)
+{
+    fapi::ReturnCode rc;
+    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_fbc_ab: Start");
+
+    do
+    {
+        // loop through all chips
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                // in SMP activate phase1, quisece hostboot slave chips
+                if ((i_op == SMP_ACTIVATE_PHASE1) &&
+                    (!p_iter->second.master_chip_sys_next))
+                {
+                    rc = proc_build_smp_quiesce_pb(p_iter->second);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_quiesce_pb");
+                        break;
+                    }
+                }
+
+                // always program NEXT register set
+                // only program CURR register set for hostboot slave chips in
+                // SMP activate phase 1
+                rc = proc_build_smp_set_pb_hp_mode(
+                    p_iter->second,
+                    i_smp,
+                    ((i_op == SMP_ACTIVATE_PHASE1) &&
+                     (!p_iter->second.master_chip_sys_next)),
+                    true);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_set_pb_hp_mode");
+                    break;
+                }
+
+                rc = proc_build_smp_set_pb_hpx_mode(
+                    p_iter->second,
+                    i_smp,
+                    ((i_op == SMP_ACTIVATE_PHASE1) &&
+                     (!p_iter->second.master_chip_sys_next)),
+                    true);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_set_pb_hpx_mode");
+                    break;
+                }
+            }
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // issue switch AB from current SMP master chip
+        proc_fab_smp_node_id node_id = i_smp.master_chip_curr_node_id;
+        proc_fab_smp_chip_id chip_id = i_smp.master_chip_curr_chip_id;
+        rc = proc_build_smp_switch_ab(
+            i_smp.nodes[node_id].chips[chip_id],
+            i_smp);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_switch_ab");
+            break;
+        }
+
+        // reset NEXT register set (copy CURR->NEXT)
+        for (n_iter = i_smp.nodes.begin();
+             (n_iter != i_smp.nodes.end()) && (rc.ok());
+             n_iter++)
+        {
+            for (p_iter = n_iter->second.chips.begin();
+                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
+                 p_iter++)
+            {
+                rc = proc_build_smp_reset_pb_hp_mode(p_iter->second);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hp_mode");
+                    break;
+                }
+
+                rc = proc_build_smp_reset_pb_hpx_mode(p_iter->second);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hpx_mode");
+                    break;
+                }
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_fbc_ab: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H
new file mode 100644
index 000000000..0959343ef
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H
@@ -0,0 +1,217 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_ab.H,v 1.2 2012/09/05 03:12:18 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_ab.H
+// *! DESCRIPTION : Fabric configuration (hotplug, AB) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_FBC_AB_H_
+#define _PROC_BUILD_SMP_FBC_AB_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp.H"
+#include "p8_scom_addresses.H"
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// PB Hotplug Mode register field/bit definitions
+const uint32_t PB_HP_MODE_LINK_A_EN_BIT[PROC_FAB_SMP_NUM_A_LINKS]       = {  1,  2,  3 };
+const uint32_t PB_HP_MODE_LINK_A_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_A_LINKS] = {  4,  5,  6 };
+const uint32_t PB_HP_MODE_LINK_A_ID_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = {  7, 10, 13 };
+const uint32_t PB_HP_MODE_LINK_A_ID_END_BIT[PROC_FAB_SMP_NUM_A_LINKS]   = {  9, 12, 15 };
+
+const uint32_t PB_HP_MODE_PCIE_NOT_DSMP_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 38, 39 };
+const uint32_t PB_HP_MODE_LINK_F_MASTER_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 42, 43 };
+const uint32_t PB_HP_MODE_LINK_F_EN_BIT[PROC_FAB_SMP_NUM_F_LINKS]       = { 44, 45 };
+const uint32_t PB_HP_MODE_LINK_F_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 46, 47 };
+const uint32_t PB_HP_MODE_LINK_F_ID_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 48, 51 };
+const uint32_t PB_HP_MODE_LINK_F_ID_END_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 50, 53 };
+
+const uint32_t PB_HP_MODE_MASTER_CHIP_BIT = 0;
+const uint32_t PB_HP_MODE_A_AGGREGATE_BIT = 16;
+const uint32_t PB_HP_MODE_TM_MASTER_BIT = 17;
+const uint32_t PB_HP_MODE_CHG_RATE_GP_MASTER_BIT = 18;
+const uint32_t PB_HP_MODE_CHG_RATE_SP_MASTER_BIT = 19;
+const uint32_t PB_HP_MODE_PUMP_MODE_BIT = 20;
+const uint32_t PB_HP_MODE_SINGLE_MC_BIT = 21;
+const uint32_t PB_HP_MODE_DCACHE_CAPP_MODE_BIT = 22;
+const uint32_t PB_HP_MODE_A_CMD_RATE_START_BIT = 24;
+const uint32_t PB_HP_MODE_A_CMD_RATE_END_BIT = 31;
+const uint32_t PB_HP_MODE_A_CMD_RATE_MIN_VALUE = 1;
+const uint32_t PB_HP_MODE_A_CMD_RATE_MAX_VALUE = 0x7F;
+const uint32_t PB_HP_MODE_A_GATHER_ENABLE_BIT = 32;
+const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT = 33;
+const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT = 37;
+const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT = 40;
+const uint32_t PB_HP_MODE_F_AGGREGATE_BIT = 55;
+const uint32_t PB_HP_MODE_F_CMD_RATE_START_BIT = 56;
+const uint32_t PB_HP_MODE_F_CMD_RATE_END_BIT = 63;
+const uint32_t PB_HP_MODE_F_CMD_RATE_MIN_VALUE = 1;
+const uint32_t PB_HP_MODE_F_CMD_RATE_MAX_VALUE = 0x7F;
+
+const bool PB_HP_MODE_DCACHE_CAPP_EN = false;
+const bool PB_HP_MODE_A_GATHER_ENABLE = true;
+const uint8_t PB_HP_MODE_A_GATHER_DLY_CNT = 0x04;
+const bool PB_HP_MODE_GATHER_ENABLE = true;
+
+const uint32_t PB_HP_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_HP_MODE_NEXT_WEST_0x02010C0B,
+    PB_HP_MODE_NEXT_CENT_0x02010C4B,
+    PB_HP_MODE_NEXT_EAST_0x02010C8B
+};
+const uint32_t PB_HP_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_HP_MODE_CURR_WEST_0x02010C0C,
+    PB_HP_MODE_CURR_CENT_0x02010C4C,
+    PB_HP_MODE_CURR_EAST_0x02010C8C
+};
+
+// PB Hotplug Extension Mode register field/bit definitions
+const uint32_t PB_HPX_MODE_LINK_X_EN_BIT[PROC_FAB_SMP_NUM_X_LINKS]           = {  0,  1,  2,  3 };
+const uint32_t PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_X_LINKS]     = {  5,  6,  7,  8 };
+const uint32_t PB_HPX_MODE_LINK_X_CHIPID_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 10, 13, 16, 19 };
+const uint32_t PB_HPX_MODE_LINK_X_CHIPID_END_BIT[PROC_FAB_SMP_NUM_X_LINKS]   = { 12, 15, 18, 21 };
+
+const uint32_t PB_HPX_MODE_X_AGGREGATE_BIT = 25;
+const uint32_t PB_HPX_MODE_X_INDIRECT_EN_BIT = 26;
+const uint32_t PB_HPX_MODE_X_GATHER_ENABLE_BIT = 32;
+const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT = 33;
+const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT = 37;
+const uint32_t PB_HPX_MODE_X_ONNODE_12QUEUES_BIT = 38;
+const uint32_t PB_HPX_MODE_X_CMD_RATE_START_BIT = 56;
+const uint32_t PB_HPX_MODE_X_CMD_RATE_END_BIT = 63;
+const uint32_t PB_HPX_MODE_X_CMD_RATE_MIN_VALUE = 1;
+const uint32_t PB_HPX_MODE_X_CMD_RATE_MAX_VALUE = 0x7F;
+
+const bool PB_HPX_MODE_X_INDIRECT_EN = true;
+const bool PB_HPX_MODE_X_GATHER_ENABLE = true;
+const uint8_t PB_HPX_MODE_X_GATHER_DLY_CNT = 0x04;
+const bool PB_HPX_MODE_X_ONNODE_12QUEUES = true;
+
+const uint32_t PB_HPX_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_HPX_MODE_NEXT_WEST_0x02010C0D,
+    PB_HPX_MODE_NEXT_CENT_0x02010C4D,
+    PB_HPX_MODE_NEXT_EAST_0x02010C8D
+};
+const uint32_t PB_HPX_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_HPX_MODE_CURR_WEST_0x02010C0E,
+    PB_HPX_MODE_CURR_CENT_0x02010C4E,
+    PB_HPX_MODE_CURR_EAST_0x02010C8E
+};
+
+// PB X Link Mode register field/bit definitions
+const uint32_t PB_X_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 24, 32, 40, 48 };
+const uint32_t PB_X_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_X_LINKS]   = { 31, 39, 47, 55 };
+
+// PB A Link Mode register field/bit definitions
+const uint32_t PB_A_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 40, 48, 56 };
+const uint32_t PB_A_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_A_LINKS]   = { 47, 55, 63 };
+
+// PB A Link Framer Configuration register field/bit definitions
+const uint32_t PB_A_FMR_CFG_OW_PACK_BIT = 24;
+const uint32_t PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT = 25;
+
+// PB IOF Link Mode register field/bit definitions
+const uint32_t PB_IOF_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 32, 48 };
+const uint32_t PB_IOF_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 47, 63 };
+
+// PB F Link Framer Configuration register field/bit definitions
+const uint32_t PB_F_FMR_CFG_OW_PACK_BIT = 20;
+const uint32_t PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT = 21;
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: utility function to read set of PB CURR hotplug registers
+// parameters: i_smp_chip   => structure encapsulating SMP chip
+//             i_hp_not_hpx => choose HP/HPX register set (true=HP,
+//                             false=HPX)
+//             o_data       => data buffer containing read data
+// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
+//               registers are equivalent,
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg(
+    const proc_build_smp_chip& i_smp_chip,
+    const bool i_hp_not_hpx,
+    ecmdDataBufferBase& o_data);
+
+
+//------------------------------------------------------------------------------
+// function: program fabric configuration register (hotplug, A/B set)
+// parameters: i_smp => structure encapsulating SMP topology
+//             i_op  => enumerated type representing SMP build phase
+// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
+//               registers are equivalent,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
+//              equivalent,
+//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
+//              specifies invalid aggregate link setup,
+//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
+//              is invalid,
+//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
+//              is invalid,
+//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
+//              is invalid,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_fbc_ab(
+    proc_build_smp_system& i_smp,
+    const proc_build_smp_operation i_op);
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_FBC_AB_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
new file mode 100644
index 000000000..873aeef76
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
@@ -0,0 +1,1130 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_cd.C,v 1.4 2012/09/24 05:01:19 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_cd.C
+// *! DESCRIPTION : Fabric configuration (hotplug, CD) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp_fbc_cd.H"
+#include "proc_build_smp_adu.H"
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: utility function to program PB serial SCOM chain
+// parameters: i_smp_chip    => structure encapsulating SMP chip
+//             i_sconfig_def => structure defining properties of chain
+//                              to be written
+//             i_chain_data  => data buffer containing chain write data
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_sconfig_def & i_sconfig_def,
+    const ecmdDataBufferBase& i_chain_data)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig: Start");
+
+    do
+    {
+        // pb_cfg_sconfig_load
+        rc_ecmd |= data.setBit(PB_SCONFIG_LOAD_START_BIT);
+
+        // pb_cfg_sconfig_slow
+        if (i_sconfig_def.use_slow_clock)
+        {
+            rc_ecmd |= data.setBit(PB_SCONFIG_LOAD_SLOW_BIT);
+        }
+
+        // pb_cfg_sconfig_shift_count
+        rc_ecmd |= data.insertFromRight(
+            i_sconfig_def.length,
+            PB_SCONFIG_SHIFT_COUNT_START_BIT,
+            (PB_SCONFIG_SHIFT_COUNT_END_BIT-
+             PB_SCONFIG_SHIFT_COUNT_START_BIT+1));
+
+        // pb_cfg_sconfig_shift_select
+        rc_ecmd |= data.insertFromRight(
+            i_sconfig_def.select,
+            PB_SCONFIG_SELECT_START_BIT,
+            (PB_SCONFIG_SELECT_END_BIT-
+             PB_SCONFIG_SELECT_START_BIT+1));
+
+        // pb_cfg_sconfig_shift_data
+        rc_ecmd |= i_chain_data.extractPreserve(
+            data,
+            PB_SCONFIG_SHIFT_DATA_START_BIT,
+            (PB_SCONFIG_SHIFT_DATA_END_BIT-
+             PB_SCONFIG_SHIFT_DATA_START_BIT+1),
+            PB_SCONFIG_SHIFT_DATA_START_BIT);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write specified register copies
+        for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
+        {
+            if (i_sconfig_def.use_shadow[r])
+            {
+                // write register
+                rc = fapiPutScom(i_smp_chip.chip->this_chip,
+                                 PB_SCONFIG_LOAD[r],
+                                 data);
+                if (!rc.ok())
+                {
+                    FAPI_ERR("proc_build_smp_set_sconfig: fapiPutScom error (%08X)",
+                             PB_SCONFIG_LOAD[r]);
+                    break;
+                }
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (center #4)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_c4(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_c4: Start");
+
+    do
+    {
+        // build register content
+        // gp_lo_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD,
+            PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT+1));
+
+        // gp_hi_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD,
+            PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT+1));
+
+        // rgp_lo_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD,
+            PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT+1));
+
+        // rgp_hi_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD,
+            PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT+1));
+
+        // sp_lo_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD,
+            PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c4: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C4_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c4: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_c4: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (center #5)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_c5(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_c5: Start");
+
+    do
+    {
+        // build register content
+        // sp_hi_rty_threshold
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD,
+            PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT,
+            (PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT-
+             PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT+1));
+
+        // gp_cresp_sample_time
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME,
+            PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT,
+            (PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT-
+             PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT+1));
+
+        // rgp_cresp_sample_time
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME,
+            PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT,
+            (PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT-
+             PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT+1));
+
+        // sp_cresp_sample_time
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME,
+            PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT,
+            (PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT-
+             PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c5: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C5_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c5: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_c5: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (center #6)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_c6(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_c6: Start");
+
+    do
+    {
+        // build register content
+        // gp_req_sample_time
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME,
+            PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT,
+            (PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT-
+             PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT+1));
+
+        // sp_req_sample_time
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME,
+            PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT,
+            (PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT-
+             PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT+1));
+
+        // gp_lo_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_GP_LO_JUMP,
+            PB_SCONFIG_C6_GP_LO_JUMP_START_BIT,
+            (PB_SCONFIG_C6_GP_LO_JUMP_END_BIT-
+             PB_SCONFIG_C6_GP_LO_JUMP_START_BIT+1));
+
+        // gp_hi_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_GP_HI_JUMP,
+            PB_SCONFIG_C6_GP_HI_JUMP_START_BIT,
+            (PB_SCONFIG_C6_GP_HI_JUMP_END_BIT-
+             PB_SCONFIG_C6_GP_HI_JUMP_START_BIT+1));
+
+        // sp_lo_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_SP_LO_JUMP,
+            PB_SCONFIG_C6_SP_LO_JUMP_START_BIT,
+            (PB_SCONFIG_C6_SP_LO_JUMP_END_BIT-
+             PB_SCONFIG_C6_SP_LO_JUMP_START_BIT+1));
+
+        // sp_hi_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_SP_HI_JUMP,
+            PB_SCONFIG_C6_SP_HI_JUMP_START_BIT,
+            (PB_SCONFIG_C6_SP_HI_JUMP_END_BIT-
+             PB_SCONFIG_C6_SP_HI_JUMP_START_BIT+1));
+
+        // rgp_lo_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_RGP_LO_JUMP,
+            PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT,
+            (PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT-
+             PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT+1));
+
+        // rgp_hi_jump
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C6_RGP_HI_JUMP,
+            PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT,
+            (PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT-
+             PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c6: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C6_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c6: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_c6: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (center #7)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_c7(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_c7: Start");
+
+    do
+    {
+        // build register content
+        // program hang command rates
+        for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
+        {
+            rc_ecmd |= data.insertFromRight(
+                PB_SCONFIG_C7_HANG_CMD_RATE[l],
+                PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[l],
+                (PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[l]-
+                 PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[l]+1));
+        }
+
+        // slow_go_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_C7_SLOW_GO_RATE_BIT,
+            PB_SCONFIG_C7_SLOW_GO_RATE?1:0);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c7: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C7_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c7: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_c7: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (center #8)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_c8(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_c8: Start");
+
+    do
+    {
+        // build register content
+        // program hang command rates
+        for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
+        {
+            rc_ecmd |= data.insertFromRight(
+                PB_SCONFIG_C8_HANG_CMD_RATE[l],
+                PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l],
+                (PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l]-
+                 PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l]+1));
+        }
+
+        // cpo_jump_level
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C8_CPO_JUMP_LEVEL,
+            PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT,
+            (PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT-
+             PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT+1));
+
+        // cpo_rty_level
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_C8_CPO_RTY_LEVEL,
+            PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT,
+            (PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT-
+             PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c8: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C8_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_c8: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_c8: End");
+    return rc;
+}
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (west/east #0)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
+//              ratio is unsupported,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_we0(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_we0: Start");
+
+    // set "safe" mode defaults
+    uint8_t cmd_c2i_done_launch  = 0x0;              // rc_p1
+    uint8_t crsp_i2c_dval_launch = 0x0;              // wc_p1
+    uint8_t data_i2c_dval_launch = 0x0;              // wc_p1
+    uint8_t data_c2i_done_launch = 0x0;              // rc_p1
+    uint8_t data_c2i_dctr_launch = 0x0;              // rc_p1
+    uint8_t rcmd_i2c_dval_launch = 0x0;              // wc_p1
+
+    do
+    {
+        // build register content
+        if (!i_smp.async_safe_mode)
+        {
+            // "performance" mode settings
+            cmd_c2i_done_launch  = 0x6;              // rc_m1
+            crsp_i2c_dval_launch = 0x3;              // wc
+            data_i2c_dval_launch = 0x2;              // wc_m1
+            data_c2i_done_launch = 0x3;              // rc
+            data_c2i_dctr_launch = 0x3;              // rc
+            rcmd_i2c_dval_launch = 0x3;              // wc
+
+            switch (i_smp.core_floor_ratio)
+            {
+                // dial back if over 2x
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8:
+                    if (i_smp.freq_core_floor > (2 * i_smp.freq_pb))
+                    {
+                        crsp_i2c_dval_launch = 0x0;  // rc_p1
+                        rcmd_i2c_dval_launch = 0x0;  // rc_p1
+                        data_i2c_dval_launch = 0x3;  // wc
+                    }
+                    break;
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8:
+                    break;
+                default:
+                    FAPI_ERR("proc_build_smp_set_sconfig_we0: Unsupported core floor frequency ratio enum (%d)",
+                             i_smp.core_floor_ratio);
+                    const uint32_t& CORE_FLOOR_RATIO = i_smp.core_floor_ratio;
+                    FAPI_SET_HWP_ERROR(rc,
+                        RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR);
+                    break;
+            }
+        }
+        if (rc)
+        {
+            break;
+        }
+
+        // cmd_c2i_done_launch
+        rc_ecmd |= data.insertFromRight(
+            cmd_c2i_done_launch,
+            PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT+1));
+
+        // cmd_c2i_late_rd_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT,
+            PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE?1:0);
+
+        // cmd_c2i_delay_sp_rd
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD,
+            PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT,
+            (PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT-
+             PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT+1));
+
+        // cmd_c2i_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE?1:0);
+
+        // prsp_c2i_done_launch
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT,
+            PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH);
+
+        // prsp_c2i_hw070772_dis
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT,
+            PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS?1:0);
+
+        // prsp_c2i_nop_mode
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE,
+            PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT,
+            (PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT-
+             PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT+1));
+
+        // prsp_c2i_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE?1:0);
+
+        // crsp_i2c_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            crsp_i2c_dval_launch,
+            PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT+1));
+
+        // crsp_i2c_hshake
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT,
+            PB_SCONFIG_WE0_CRSP_I2C_HSHAKE?1:0);
+
+        // crsp_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE?1:0);
+
+        // data_i2c_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            data_i2c_dval_launch,
+            PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT+1));
+
+        // data_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE?1:0);
+
+        // data_i2c_force_fa_alloc
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT,
+            PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC?1:0);
+
+        // data_c2i_done_launch
+        rc_ecmd |= data.insertFromRight(
+            data_c2i_done_launch,
+            PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT+1));
+
+        // data_c2i_initial_req_dly_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY,
+            PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT,
+            (PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT-
+             PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT+1));
+
+        // data_c2i_dctr_launch
+        rc_ecmd |= data.insertFromRight(
+            data_c2i_dctr_launch,
+            PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT+1));
+
+        // data_c2i_outstanding_req_count
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT,
+            PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT?1:0);
+
+        // data_c2i_req_id_assignment_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT,
+            PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE?1:0);
+
+        // data_c2i_allow_fragmentation_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT,
+            PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION?1:0);
+
+        // data_c2i_serial_dreq_id_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT,
+            PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID?1:0);
+
+        // data_c2i_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE?1:0);
+
+        // rcmd_i2c_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            rcmd_i2c_dval_launch,
+            PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT+1));
+
+        // rcmd_i2c_hshake
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT,
+            PB_SCONFIG_WE0_RCMD_I2C_HSHAKE?1:0);
+
+        // rcmd_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE?1:0);
+
+        // fp_i2c_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH,
+            PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT+1));
+
+        // fp_i2c_hshake
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT,
+            PB_SCONFIG_WE0_FP_I2C_HSHAKE?1:0);
+
+        // fp_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_FP_I2C_SPARE_MODE?1:0);
+
+        // fp_c2i_done_launch
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT,
+            PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH);
+
+        // fp_c2i_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE0_FP_C2I_SPARE_MODE?1:0);
+
+        // cpu_ratio_table_full
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL,
+            PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT,
+            (PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_END_BIT-
+             PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT+1));
+
+        // cpu_ratio_table_half
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM,
+            PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT,
+            (PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_END_BIT-
+             PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT+1));
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we0: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE0_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we0: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_we0: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB serial SCOM chain (west/east #1)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
+//              ratio is unsupported,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_sconfig_we1(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_sconfig_we1: Start");
+
+    // set "safe" mode defaults
+    uint8_t cmd_c2i_dval_launch = 0x0;               // wc_p1
+    uint8_t crsp_i2c_done_launch = 0x0;              // rc_p1
+    uint8_t crsp_i2c_pty_rd_capture = 0x0;           // rc
+    uint8_t data_i2c_done_launch = 0x0;              // rc_p1
+    uint8_t data_i2c_dctr_launch = 0x0;              // rc_p1
+    uint8_t data_c2i_dval_launch = 0x0;              // wc_p1
+    uint8_t rcmd_i2c_done_launch = 0x0;              // rc_p1
+    uint8_t rcmd_i2c_pty_rd_capture = 0x0;           // rc
+
+    do
+    {
+        // build register content
+        if (!i_smp.async_safe_mode)
+        {
+            // "performance" mode settings
+            crsp_i2c_done_launch = 0x1;              // rc
+            crsp_i2c_pty_rd_capture = 0x1;           // rc_p1
+            data_i2c_done_launch = 0x2;              // rc_m1
+            rcmd_i2c_done_launch = 0x1;              // rc
+            rcmd_i2c_pty_rd_capture = 0x1;           // rc_p1
+
+            switch (i_smp.core_floor_ratio)
+            {
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_8_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_7_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_6_8:
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_5_8:
+                    cmd_c2i_dval_launch = 0x3;       // wc
+                    data_i2c_dctr_launch = 0x1;      // rc_m2
+                    data_c2i_dval_launch = 0x2;      // wc_m1
+                    break;
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_4_8:
+                    cmd_c2i_dval_launch = 0x3;       // wc
+                    data_i2c_dctr_launch = 0x2;      // rc_m1
+                    data_c2i_dval_launch = 0x3;      // wc
+                    break;
+                case PROC_BUILD_SMP_CORE_FLOOR_RATIO_2_8:
+                    cmd_c2i_dval_launch = 0x0;       // wc_p1
+                    data_i2c_dctr_launch = 0x3;      // rc
+                    data_c2i_dval_launch = 0x0;      // wc_p1
+                    break;
+                default:
+                    FAPI_ERR("proc_build_smp_set_sconfig_we1: Unsupported core floor frequency ratio enum (%d)",
+                             i_smp.core_floor_ratio);
+                    const uint32_t& CORE_FLOOR_RATIO = i_smp.core_floor_ratio;
+                    FAPI_SET_HWP_ERROR(rc,
+                        RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR);
+                    break;
+            }
+        }
+        if (rc)
+        {
+            break;
+        }
+
+        // cmd_c2i_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            cmd_c2i_dval_launch,
+            PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT+1));
+
+        // cmd_c2i_early_req_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT,
+            PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE?1:0);
+
+        // cmd_c2i_spare_bit
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT,
+            PB_SCONFIG_WE1_CMD_C2I_SPARE?1:0);
+
+        // cmd_c2i_spare_mode_bit
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE?1:0);
+
+        // prsp_c2i_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH,
+            PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT+1));
+
+        // prsp_c2i_hshake
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT,
+            PB_SCONFIG_WE1_PRSP_C2I_HSHAKE?1:0);
+
+        // prsp_c2i_spare mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE?1:0);
+
+        // crsp_i2c_done_launch
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT,
+            crsp_i2c_done_launch);
+
+        // crsp_i2c_pty_rd_capture
+        rc_ecmd |= data.insertFromRight(
+            crsp_i2c_pty_rd_capture,
+            PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT,
+            (PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT-
+             PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT+1));
+
+        // crsp_i2c_spare mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE?1:0);
+
+        // data_i2c_done_launch
+        rc_ecmd |= data.insertFromRight(
+            data_i2c_done_launch,
+            PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT+1));
+
+        // data_i2c_dctr_launch
+        rc_ecmd |= data.insertFromRight(
+            data_i2c_dctr_launch,
+            PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT+1));
+
+        // data_i2c_spare mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE?1:0);
+
+        // data_c2i_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            data_c2i_dval_launch,
+            PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT+1));
+
+        // data_c2i_dreq_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH,
+            PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT+1));
+
+        // data_c2i_spare mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE?1:0);
+
+        // rcmd_i2c_done_launch
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT,
+            rcmd_i2c_done_launch);
+
+        // rcmd_i2c_l3_not_use_dcbfl
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT,
+            PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL?1:0);
+
+        // rcmd_i2c_pty_rd_capture_launch
+        rc_ecmd |= data.insertFromRight(
+            rcmd_i2c_pty_rd_capture,
+            PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT,
+            (PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT-
+             PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT+1));
+
+        // rcmd_i2c_pty_inject
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT,
+            PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT?1:0);
+
+        // rcmd_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE?1:0);
+
+        // fp_i2c_done_launch
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT,
+            PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH?1:0);
+
+        // fp_i2c_spare
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_FP_I2C_SPARE_BIT,
+            PB_SCONFIG_WE1_FP_I2C_SPARE?1:0);
+
+        // fp_i2c_pty_rd_capture_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE,
+            PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT,
+            (PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT-
+             PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT+1));
+
+        // fp_i2c_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_FP_I2C_SPARE_MODE?1:0);
+
+        // fp_c2i_dval_launch
+        rc_ecmd |= data.insertFromRight(
+            PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH,
+            PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT,
+            (PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT-
+             PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT+1));
+
+        // fp_c2i_hshake
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT,
+            PB_SCONFIG_WE1_FP_C2I_HSHAKE?1:0);
+
+        // fp_c2i_spare_mode
+        rc_ecmd |= data.writeBit(
+            PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT,
+            PB_SCONFIG_WE1_FP_C2I_SPARE_MODE?1:0);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we1: Error 0x%x setting up PB Serial Configuration load register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // call common routine to program chain
+        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE1_DEF, data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_sconfig_we1: Error from proc_build_smp_set_sconfig");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_sconfig_we1: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_set_fbc_cd(
+    proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_fbc_cd: Start");
+
+    for (n_iter = i_smp.nodes.begin();
+         (n_iter != i_smp.nodes.end()) && (rc.ok());
+         n_iter++)
+    {
+        for (p_iter = n_iter->second.chips.begin();
+             (p_iter != n_iter->second.chips.end()) && (rc.ok());
+             p_iter++)
+        {
+            // program center chains
+            rc = proc_build_smp_set_sconfig_c4(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c4");
+                break;
+            }
+
+            rc = proc_build_smp_set_sconfig_c5(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c5");
+                break;
+            }
+
+            rc = proc_build_smp_set_sconfig_c6(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c6");
+                break;
+            }
+
+            rc = proc_build_smp_set_sconfig_c7(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c7");
+                break;
+            }
+
+            rc = proc_build_smp_set_sconfig_c8(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c8");
+                break;
+            }
+
+            // program east/west chains
+            rc = proc_build_smp_set_sconfig_we0(p_iter->second, i_smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we0");
+                break;
+            }
+
+            rc = proc_build_smp_set_sconfig_we1(p_iter->second, i_smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we1");
+                break;
+            }
+
+            // issue single switch CD to force all updates to occur
+            rc = proc_build_smp_switch_cd(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_switch_cd");
+                break;
+            }
+        }
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_fbc_cd: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
new file mode 100644
index 000000000..4555064c7
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
@@ -0,0 +1,375 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_cd.H,v 1.3 2012/09/05 03:12:50 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_cd.H
+// *! DESCRIPTION : Fabric configuration (hotplug, CD) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_FBC_CD_H_
+#define _PROC_BUILD_SMP_FBC_CD_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp.H"
+#include "p8_scom_addresses.H"
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// structure encapsulating serial configuration load programming
+struct proc_build_smp_sconfig_def
+{
+    uint8_t select;                               // ID/select for chain
+    uint8_t length;                               // number of bits to load
+    bool use_slow_clock;                          // use 16:1 slow clock? (EX)
+    bool use_shadow[PROC_BUILD_SMP_NUM_SHADOWS];  // define which shadows to set
+};
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+//
+// PB Serial Configuration Load register field/bit definitions
+//
+
+// hang level constants
+const uint8_t PB_SCONFIG_NUM_HANG_LEVELS = 7;
+
+const uint32_t PB_SCONFIG_LOAD[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_SCONFIG_LOAD_WEST_0x02010C16,
+    PB_SCONFIG_LOAD_CENT_0x02010C6D,
+    PB_SCONFIG_LOAD_EAST_0x02010C96
+};
+
+const uint32_t PB_SCONFIG_LOAD_START_BIT = 0;
+const uint32_t PB_SCONFIG_LOAD_SLOW_BIT = 1;
+const uint32_t PB_SCONFIG_SHIFT_COUNT_START_BIT = 2;
+const uint32_t PB_SCONFIG_SHIFT_COUNT_END_BIT = 7;
+const uint32_t PB_SCONFIG_SELECT_START_BIT = 8;
+const uint32_t PB_SCONFIG_SELECT_END_BIT = 11;
+const uint32_t PB_SCONFIG_SHIFT_DATA_START_BIT = 12;
+const uint32_t PB_SCONFIG_SHIFT_DATA_END_BIT = 63;
+
+
+//
+// PBH_CMD_SNOOPER (center, chain #4) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_C4_DEF = { 0x4, 50, false, { false, true, false} };
+
+const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT = 14;
+const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT = 23;
+const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT = 24;
+const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT = 33;
+const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT = 34;
+const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT = 43;
+const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT = 44;
+const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT = 53;
+const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT = 54;
+const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT = 63;
+
+const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD = 0x8;
+const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD = 0x6;
+const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD = 0x8;
+const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD = 0x6;
+const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD = 0x8;
+
+
+//
+// PBH_CMD_SNOOPER (center, chain #5) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_C5_DEF = { 0x5, 46, false, { false, true, false} };
+
+const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT = 18;
+const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT = 27;
+const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT = 28;
+const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT = 39;
+const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT = 40;
+const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT = 51;
+const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT = 52;
+const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT = 63;
+
+const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD = 0x6;
+const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME = 256;
+const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME = 256;
+const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME = 256;
+
+
+//
+// PBH_CMD_SNOOPER (center, chain #6) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_C6_DEF = { 0x6, 42, false, { false, true, false} };
+
+const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT = 22;
+const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT = 33;
+const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT = 34;
+const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT = 45;
+const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_START_BIT = 46;
+const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_END_BIT = 48;
+const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_START_BIT = 49;
+const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_END_BIT = 51;
+const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_START_BIT = 52;
+const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_END_BIT = 54;
+const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_START_BIT = 55;
+const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_END_BIT = 57;
+const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT = 58;
+const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT = 60;
+const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT = 61;
+const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT = 63;
+
+const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME = 512;
+const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME = 512;
+const uint32_t PB_SCONFIG_C6_GP_LO_JUMP = 0x3;
+const uint32_t PB_SCONFIG_C6_GP_HI_JUMP = 0x3;
+const uint32_t PB_SCONFIG_C6_SP_LO_JUMP = 0x3;
+const uint32_t PB_SCONFIG_C6_SP_HI_JUMP = 0x3;
+const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP = 0x3;
+const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP = 0x3;
+
+
+//
+// PBH_CMD_SNOOPER (center, chain #7) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_C7_DEF = { 0x7, 36, false, { false, true, false } };
+
+const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 33, 38, 43, 48, 53, 58 };
+const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS]   = { 32, 37, 42, 47, 52, 57, 62 };
+const uint32_t PB_SCONFIG_C7_SLOW_GO_RATE_BIT = 63;
+
+// PB_CFG_HANG0_CMD_RATE = 0x00 = 127/128
+// PB_CFG_HANG1_CMD_RATE = 0x06 = 1/2
+// PB_CFG_HANG2_CMD_RATE = 0x0D = 1/512
+// PB_CFG_HANG3_CMD_RATE = 0x00 = 127/128
+// PB_CFG_HANG4_CMD_RATE = 0x1E = 1/4096 (toad mode)
+// PB_CFG_HANG5_CMD_RATE = 0x19 = 1/8 (toad mode)
+// PB_CFG_HANG6_CMD_RATE = 0x00 = 127/128
+const uint8_t PB_SCONFIG_C7_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x06, 0x0D, 0x00, 0x1E, 0x19, 0x00 };
+const bool    PB_SCONFIG_C7_SLOW_GO_RATE = true;
+
+
+//
+// PBH_CMD_SNOOPER (center, chain #8) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF = { 0x8, 37, false, { false, true, false } };
+
+const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 };
+const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS]   = { 30, 34, 38, 42, 46, 50, 54 };
+const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT = 55;
+const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT = 57;
+const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT = 58;
+const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT = 63;
+
+const uint8_t  PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x3;
+const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0xF;
+
+
+//
+// PBH_PBIEX_EH (east/west, chain #0) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_WE0_DEF = { 0x0, 52, false, { true, false, true } };
+
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT = 12;
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT = 14;
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT = 15;
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT = 16;
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT = 17;
+const uint32_t PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT = 18;
+const uint32_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT = 19;
+const uint32_t PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT = 20;
+const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT = 21;
+const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT = 22;
+const uint32_t PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT = 23;
+const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT = 24;
+const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT = 25;
+const uint32_t PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT = 26;
+const uint32_t PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT = 27;
+const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT = 28;
+const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT = 29;
+const uint32_t PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT = 30;
+const uint32_t PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT = 31;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT = 32;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT = 33;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT = 34;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT = 36;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT = 37;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT = 38;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT = 39;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT = 40;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT = 41;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT = 42;
+const uint32_t PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT = 43;
+const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT = 44;
+const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT = 45;
+const uint32_t PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT = 46;
+const uint32_t PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT = 47;
+const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT = 48;
+const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT = 49;
+const uint32_t PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT = 50;
+const uint32_t PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT  = 51;
+const uint32_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT = 52;
+const uint32_t PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT = 53;
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_START_BIT = 54;
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL_END_BIT = 58;
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_START_BIT  = 59;
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM_END_BIT = 63;
+
+const uint8_t  PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true;             // on
+const uint8_t  PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD = 0x0;               // rc_p1
+const bool     PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE = false;              // spare
+const uint8_t  PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH = 0x0;              // rc_p1
+const bool     PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS = true;            // on
+const uint8_t  PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE = 0x0;                 // 16c
+const bool     PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE = false;             // spare
+const bool     PB_SCONFIG_WE0_CRSP_I2C_HSHAKE = false;                 // off
+const bool     PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE = false;             // spare
+const bool     PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE = false;             // spare
+const bool     PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC = false;         // off
+const uint8_t  PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY = 0x7;          // 7c
+const bool     PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT = false;  // 8
+const bool     PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE = false; // FA
+const bool     PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION = true;     // on
+const bool     PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID = true;          // on
+const bool     PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE = false;             // spare
+const bool     PB_SCONFIG_WE0_RCMD_I2C_HSHAKE = false;                 // off
+const bool     PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE = false;             // spare
+const uint8_t  PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH = 0x0;                // wc_p1
+const uint8_t  PB_SCONFIG_WE0_FP_I2C_HSHAKE = false;                   // off
+const bool     PB_SCONFIG_WE0_FP_I2C_SPARE_MODE = false;               // spare
+const uint8_t  PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH = 0x0;                // rc_p1
+const bool     PB_SCONFIG_WE0_FP_C2I_SPARE_MODE = false;               // spare
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_FULL = 0x0D;             // 13
+const uint32_t PB_SCONFIG_WE0_CPU_RATIO_TABLE_NOM = 0x12;              // 18
+
+
+//
+// PBH_PBIEX_EX (east/west, chain #1) field/bit definitions
+//
+
+const proc_build_smp_sconfig_def PB_SCONFIG_WE1_DEF = { 0x1, 38, true, { true, false, true } };
+
+const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT = 26;
+const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT = 27;
+const uint32_t PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT = 28;
+const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT = 29;
+const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT = 30;
+const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT = 31;
+const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT = 32;
+const uint32_t PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT = 33;
+const uint32_t PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT = 34;
+const uint32_t PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT = 35;
+const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT = 36;
+const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT = 37;
+const uint32_t PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT = 38;
+const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT = 39;
+const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT = 40;
+const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT = 41;
+const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT = 42;
+const uint32_t PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT = 43;
+const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT = 44;
+const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT = 45;
+const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT = 46;
+const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT = 47;
+const uint32_t PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT = 48;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT = 49;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT = 50;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT = 51;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT = 52;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT = 53;
+const uint32_t PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT = 54;
+const uint32_t PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT = 55;
+const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_BIT = 56;
+const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT = 57;
+const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT = 58;
+const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT = 59;
+const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT = 60;
+const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT = 61;
+const uint32_t PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT = 62;
+const uint32_t PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT = 63;
+
+const bool    PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE = false;           // off
+const bool    PB_SCONFIG_WE1_CMD_C2I_SPARE = false;                    // spare
+const bool    PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE = false;               // spare
+const uint8_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH = 0x0;               // rc_p1
+const bool    PB_SCONFIG_WE1_PRSP_C2I_HSHAKE = false;                  // off
+const bool    PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE = false;              // spare
+const bool    PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE = false;              // spare
+const bool    PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE = false;              // spare
+const uint8_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH = 0x0;               // rc_d3
+const bool    PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE = false;              // off
+const bool    PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL = false;        // off
+const bool    PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT = false;              // off
+const bool    PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE = false;              // off
+const bool    PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH = false;               // rc_p1
+const bool    PB_SCONFIG_WE1_FP_I2C_SPARE = false;                     // spare
+const uint8_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE = 0x0;              // rc
+const bool    PB_SCONFIG_WE1_FP_I2C_SPARE_MODE = false;                // off
+const uint8_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH = 0x0;                 // wc_p1
+const bool    PB_SCONFIG_WE1_FP_C2I_HSHAKE = false;                    // off
+const bool    PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false;                // spare
+
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: program fabric configuration register (hotplug, C/D set)
+// parameters: i_smp => structure encapsulating SMP topology
+//             i_op  => enumerated type representing SMP build phase
+// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
+//               registers are equivalent,
+//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
+//              ratio is unsupported,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_fbc_cd(
+    proc_build_smp_system& i_smp);
+
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_FBC_CD_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C
new file mode 100644
index 000000000..798bd19b2
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C
@@ -0,0 +1,732 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_nohp.C,v 1.3 2012/09/05 03:13:17 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_nohp.C
+// *! DESCRIPTION : Fabric configuration (non-hotplug) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp_fbc_nohp.H"
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_gp_low_pacing_table::xlate_map =
+    proc_build_smp_gp_low_pacing_table::create_map();
+
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_gp_high_pacing_table::xlate_map =
+    proc_build_smp_gp_high_pacing_table::create_map();
+
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_sp_low_pacing_table::xlate_map =
+    proc_build_smp_sp_low_pacing_table::create_map();
+
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_sp_high_pacing_table::xlate_map =
+    proc_build_smp_sp_high_pacing_table::create_map();
+
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_rgp_low_pacing_table::xlate_map =
+    proc_build_smp_rgp_low_pacing_table::create_map();
+
+const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_rgp_high_pacing_table::xlate_map =
+    proc_build_smp_rgp_high_pacing_table::create_map();
+
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: utility function to determine number of chips present
+//           in enclosing group
+// parameters: i_smp_chip        => structure encapsulating SMP chip
+//             i_smp             => structure encapsulating SMP topology
+//             o_chips_per_group => enum representing number of chips in
+//                                  group enclosing i_smp_chip
+// returns: FAPI_RC_SUCCESS if output group size is valid,
+//          else RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
+//              small/large
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_calc_chips_per_group(
+    const proc_build_smp_chip& i_smp_chip,
+    proc_build_smp_system& i_smp,
+    proc_build_smp_chips_per_group& o_chips_per_group)
+{
+    fapi::ReturnCode rc;
+    uint8_t chips_per_group_exact;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_calc_chips_per_group: Start");
+
+    chips_per_group_exact = i_smp.nodes[i_smp_chip.node_id].chips.size();
+    switch(chips_per_group_exact)
+    {
+        case 1:
+            o_chips_per_group = PROC_BUILD_SMP_1CPG;
+            break;
+        case 2:
+            o_chips_per_group = PROC_BUILD_SMP_2CPG;
+            break;
+        case 3:
+        case 4:
+            o_chips_per_group = PROC_BUILD_SMP_4CPG;
+            break;
+        default:
+            FAPI_ERR("proc_build_smp_calc_chips_per_group: Unsupported group size (=%d)",
+                     chips_per_group_exact);
+            const uint8_t& SIZE = chips_per_group_exact;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR);
+            break;
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_calc_chips_per_group: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to program one command scope drop priority
+//           register
+// parameters: i_smp_chip        => structure encapsulating SMP chip
+//             i_chips_per_group => enum representing chips in group enclosing
+//                                  i_smp_chip
+//             i_map_table       => map defining drop priority programming rates
+//             i_scom_addr       => target SCOM register
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
+//              is unsuccessful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_pacing_rate(
+    const proc_build_smp_chip& i_smp_chip,
+    const proc_build_smp_chips_per_group& i_chips_per_group,
+    const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]>& i_map_table,
+    const uint32_t i_scom_addr)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_pacing_rate: Start");
+
+    do
+    {
+        // access map table
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]>::const_iterator m =
+            i_map_table.find(i_chips_per_group);
+
+        if (m == i_map_table.end())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rate: Pacing rate map table lookup failed");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR);
+            break;
+        }
+
+        // set all drop priority level fields
+        for (uint8_t l = 0; l < PROC_BUILD_SMP_DP_LEVELS; l++)
+        {
+            // pb_cfg_##_cmd_rate_dp#_lvl#
+            rc_ecmd |= data.insertFromRight(
+                (*(m->second))[l],
+                PB_SCOPE_COMMAND_PACING_LVL_START_BIT[l],
+                (PB_SCOPE_COMMAND_PACING_LVL_END_BIT[l]-
+                 PB_SCOPE_COMMAND_PACING_LVL_START_BIT[l]+1));
+        }
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rate: Error 0x%x setting up data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register
+        rc = fapiPutScom(i_smp_chip.chip->this_chip, i_scom_addr, data);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rate: fapiPutScom error (%08X)",
+                     i_scom_addr);
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_pacing_rate: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program all command scope drop priority registers
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP topology
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
+//              small/large,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_pacing_rates(
+    const proc_build_smp_chip& i_smp_chip,
+    proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    proc_build_smp_chips_per_group chips_per_group;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_pacing_rates: Start");
+
+    do
+    {
+        // determine number of chips in enclosing group (use to index proper
+        // drop priority table)
+        rc = proc_build_smp_calc_chips_per_group(i_smp_chip,
+                                                 i_smp,
+                                                 chips_per_group);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_calc_chips_per_group");
+            break;
+        }
+
+        // group (low)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_gp_low_pacing_table::xlate_map,
+                                            PB_GP_CMD_RATE_DP_LO_0x02010C62);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (GP low)");
+            break;
+        }
+
+        // group (high)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_gp_high_pacing_table::xlate_map,
+                                            PB_GP_CMD_RATE_DP_HI_0x02010C63);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (GP high)");
+            break;
+        }
+
+        // remote group (low)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_rgp_low_pacing_table::xlate_map,
+                                            PB_RGP_CMD_RATE_DP_LO_0x02010C64);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (RGP low)");
+            break;
+        }
+
+        // remote group (high)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_rgp_high_pacing_table::xlate_map,
+                                            PB_RGP_CMD_RATE_DP_HI_0x02010C65);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (RGP high)");
+            break;
+        }
+
+        // system (low)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_sp_low_pacing_table::xlate_map,
+                                            PB_SP_CMD_RATE_DP_LO_0x02010C66);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (SP low)");
+            break;
+        }
+
+        // system (high)
+        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
+                                            chips_per_group,
+                                            proc_build_smp_sp_high_pacing_table::xlate_map,
+                                            PB_SP_CMD_RATE_DP_HI_0x02010C67);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (SP high)");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_pacing_rates: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB mode register
+// parameters: i_smp_chip => structure encapsulating SMP chip
+//             i_smp      => structure encapsulating SMP topology
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_pb_mode(
+    const proc_build_smp_chip& i_smp_chip,
+    proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64), mask(64);
+    bool chip_is_system = false;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_pb_mode: Start");
+
+    do
+    {
+        // compute derived register fields
+        // pb_cfg_chip_is_system
+        // set for single chip SMP, only if AVP mode is off
+        chip_is_system = ((i_smp.nodes.size() == 1) &&
+                          (i_smp.nodes[i_smp_chip.node_id].chips.size() == 1) &&
+                          (!i_smp.avp_mode));
+
+        // pb_cfg_chip_is_system
+        rc_ecmd |= data.writeBit(PB_MODE_CHIP_IS_SYSTEM_BIT,
+                                 chip_is_system?1:0);
+        rc_ecmd |= mask.setBit(PB_MODE_CHIP_IS_SYSTEM_BIT);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_pb_mode: Error 0x%x setting up PB Mode register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write west/center/east register copies (use mask to avoid overriding
+        // other configuration settings in register)
+        for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
+        {
+            rc = fapiPutScomUnderMask(i_smp_chip.chip->this_chip,
+                                      PB_MODE_SHADOWS[r],
+                                      data,
+                                      mask);
+
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_pb_mode: fapiPutScomUnderMask error (%08X)",
+                         PB_MODE_SHADOWS[r]);
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_pb_mode: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB X Link Mode register (configure trace selection based
+//           on first active link)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_x_trace(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64), mask(64);
+    bool trace_enable = false;
+    uint8_t trace_sel = 0x0;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_x_trace: Start");
+
+    do
+    {
+        // find first configured link, set to trace outbound traffic
+        if (i_smp_chip.chip->x0_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            trace_enable = true;
+            trace_sel = 0x4;
+        }
+        else if (i_smp_chip.chip->x1_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            trace_enable = true;
+            trace_sel = 0x5;
+        }
+        else if (i_smp_chip.chip->x2_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            trace_enable = true;
+            trace_sel = 0x6;
+        }
+        else if (i_smp_chip.chip->x3_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            trace_enable = true;
+            trace_sel = 0x7;
+        }
+
+        // build data buffer
+        // trace enable
+        rc_ecmd |= data.writeBit(
+            PB_X_MODE_TRACE_ENABLE_BIT,
+            trace_enable?1:0);
+        rc_ecmd |= mask.setBit(
+            PB_X_MODE_TRACE_ENABLE_BIT);
+
+        // trace select
+        rc_ecmd |= data.insertFromRight(
+            trace_sel,
+            PB_X_MODE_TRACE_SELECT_START_BIT,
+            (PB_X_MODE_TRACE_SELECT_END_BIT-
+             PB_X_MODE_TRACE_SELECT_START_BIT)+1);
+        rc_ecmd |= mask.setBit(
+            PB_X_MODE_TRACE_SELECT_START_BIT,
+            (PB_X_MODE_TRACE_SELECT_END_BIT-
+             PB_X_MODE_TRACE_SELECT_START_BIT)+1);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_x_trace: Error 0x%x setting up X Link Mode register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register
+        rc = fapiPutScomUnderMask(i_smp_chip.chip->this_chip,
+                                  PB_X_MODE_0x04010C0A,
+                                  data,
+                                  mask);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_x_trace: fapiPutScomUnderMask error (PB_X_MODE_0x04010C0A)");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_x_trace: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB A Link Trace register (configure trace selection based
+//           on first active link)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_a_trace(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64);
+    uint8_t a0_out_sel = 0x0;
+    uint8_t a1_out_sel = 0x0;
+    uint8_t a2_out_sel = 0x0;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_a_trace: Start");
+
+    do
+    {
+        // find first configured link, set to trace outbound traffic
+        if (i_smp_chip.chip->a0_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            a0_out_sel = 0x1;
+            a1_out_sel = 0x0;
+            a2_out_sel = 0x0;
+        }
+        else if (i_smp_chip.chip->a1_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            a0_out_sel = 0x0;
+            a1_out_sel = 0x1;
+            a2_out_sel = 0x0;
+        }
+        else if (i_smp_chip.chip->a2_chip.getType() != fapi::TARGET_TYPE_NONE)
+        {
+            a0_out_sel = 0x0;
+            a1_out_sel = 0x0;
+            a2_out_sel = 0x1;
+        }
+
+        // build data buffer (clear previous configuration)
+        // A0 outbound trace select
+        rc_ecmd |= data.insertFromRight(
+            a0_out_sel,
+            PB_A_TRACE_A0_OUT_SEL0_START_BIT,
+            (PB_A_TRACE_A0_OUT_SEL0_END_BIT-
+             PB_A_TRACE_A0_OUT_SEL0_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a0_out_sel,
+            PB_A_TRACE_A0_OUT_SEL1_START_BIT,
+            (PB_A_TRACE_A0_OUT_SEL1_END_BIT-
+             PB_A_TRACE_A0_OUT_SEL1_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a0_out_sel,
+            PB_A_TRACE_A0_OUT_SEL2_START_BIT,
+            (PB_A_TRACE_A0_OUT_SEL2_END_BIT-
+             PB_A_TRACE_A0_OUT_SEL2_START_BIT)+1);
+
+        // A1 outbound trace select
+        rc_ecmd |= data.insertFromRight(
+            a1_out_sel,
+            PB_A_TRACE_A1_OUT_SEL0_START_BIT,
+            (PB_A_TRACE_A1_OUT_SEL0_END_BIT-
+             PB_A_TRACE_A1_OUT_SEL0_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a1_out_sel,
+            PB_A_TRACE_A1_OUT_SEL1_START_BIT,
+            (PB_A_TRACE_A1_OUT_SEL1_END_BIT-
+             PB_A_TRACE_A1_OUT_SEL1_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a1_out_sel,
+            PB_A_TRACE_A1_OUT_SEL2_START_BIT,
+            (PB_A_TRACE_A1_OUT_SEL2_END_BIT-
+             PB_A_TRACE_A1_OUT_SEL2_START_BIT)+1);
+
+        // A2 outbound trace select
+        rc_ecmd |= data.insertFromRight(
+            a2_out_sel,
+            PB_A_TRACE_A2_OUT_SEL0_START_BIT,
+            (PB_A_TRACE_A2_OUT_SEL0_END_BIT-
+             PB_A_TRACE_A2_OUT_SEL0_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a2_out_sel,
+            PB_A_TRACE_A2_OUT_SEL1_START_BIT,
+            (PB_A_TRACE_A2_OUT_SEL1_END_BIT-
+             PB_A_TRACE_A2_OUT_SEL1_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            a2_out_sel,
+            PB_A_TRACE_A2_OUT_SEL2_START_BIT,
+            (PB_A_TRACE_A2_OUT_SEL2_END_BIT-
+             PB_A_TRACE_A2_OUT_SEL2_START_BIT)+1);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_a_trace: Error 0x%x setting up A Link Trace register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register
+        rc = fapiPutScom(i_smp_chip.chip->this_chip,
+                         PB_A_TRACE_0x08010812,
+                         data);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_a_trace: fapiPutScom error (PB_A_TRACE_0x08010812)");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_a_trace: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: program PB F Link Trace register (configure trace selection based
+//           on first active link)
+// parameters: i_smp_chip => structure encapsulating SMP chip
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_f_trace(
+    const proc_build_smp_chip& i_smp_chip)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0x0;
+    ecmdDataBufferBase data(64), mask(64);
+    uint8_t f0_out_sel = 0x0;
+    uint8_t f1_out_sel = 0x0;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_f_trace: Start");
+
+    do
+    {
+        // find first configured link, set to trace outbound traffic
+        if (i_smp_chip.chip->enable_f0)
+        {
+            f0_out_sel = 0x1;
+            f1_out_sel = 0x0;
+        }
+        else if (i_smp_chip.chip->enable_f1)
+        {
+            f0_out_sel = 0x0;
+            f1_out_sel = 0x1;
+        }
+
+        // build data buffer (clear previous configuration)
+        // F0 outbound trace select
+        rc_ecmd |= data.insertFromRight(
+            f0_out_sel,
+            PB_F_TRACE_F0_OUT_SEL0_START_BIT,
+            (PB_F_TRACE_F0_OUT_SEL0_END_BIT-
+             PB_F_TRACE_F0_OUT_SEL0_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            f0_out_sel,
+            PB_F_TRACE_F0_OUT_SEL1_START_BIT,
+            (PB_F_TRACE_F0_OUT_SEL1_END_BIT-
+             PB_F_TRACE_F0_OUT_SEL1_START_BIT)+1);
+
+        // F1 outbound trace select
+        rc_ecmd |= data.insertFromRight(
+            f1_out_sel,
+            PB_F_TRACE_F1_OUT_SEL0_START_BIT,
+            (PB_F_TRACE_F1_OUT_SEL0_END_BIT-
+             PB_F_TRACE_F1_OUT_SEL0_START_BIT)+1);
+        rc_ecmd |= data.insertFromRight(
+            f1_out_sel,
+            PB_F_TRACE_F1_OUT_SEL1_START_BIT,
+            (PB_F_TRACE_F1_OUT_SEL1_END_BIT-
+             PB_F_TRACE_F1_OUT_SEL1_START_BIT)+1);
+
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_build_smp_set_f_trace: Error 0x%x setting up F Link Trace register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write register
+        rc = fapiPutScom(i_smp_chip.chip->this_chip,
+                         PB_F_TRACE_0x09010812,
+                         data);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_a_trace: fapiPutScom error (PB_F_TRACE_0x09010812)");
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_f_traec: End");
+    return rc;
+}
+
+
+// NOTE: see comments above function prototype in header
+fapi::ReturnCode proc_build_smp_set_fbc_nohp(
+    proc_build_smp_system& i_smp)
+{
+    fapi::ReturnCode rc;
+    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
+    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
+
+    // mark function entry
+    FAPI_DBG("proc_build_smp_set_fbc_nohp: Start");
+
+    // process each chip in SMP, program unit non-hotplug registers
+    for (n_iter = i_smp.nodes.begin();
+         (n_iter != i_smp.nodes.end()) && (rc.ok());
+         n_iter++)
+    {
+        for (p_iter = n_iter->second.chips.begin();
+             (p_iter != n_iter->second.chips.end()) && (rc.ok());
+             p_iter++)
+        {
+            // PB Mode register
+            rc = proc_build_smp_set_pb_mode(p_iter->second,
+                                            i_smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_pb_mode");
+                break;
+            }
+
+            // command scope drop priority registers
+            rc = proc_build_smp_set_pacing_rates(p_iter->second,
+                                                 i_smp);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_pacing_rates");
+                break;
+            }
+
+            // X link trace setup
+            rc = proc_build_smp_set_x_trace(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_x_trace");
+                break;
+            }
+
+            // A link trace setup
+            rc = proc_build_smp_set_a_trace(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_a_trace");
+                break;
+            }
+
+            // F link trace setup
+            rc = proc_build_smp_set_f_trace(p_iter->second);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_f_trace");
+                break;
+            }
+        }
+    }
+
+    // mark function exit
+    FAPI_DBG("proc_build_smp_set_fbc_nohp: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H
new file mode 100644
index 000000000..29545ae2e
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H
@@ -0,0 +1,257 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_build_smp_fbc_nohp.H,v 1.2 2012/09/05 03:13:18 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_build_smp_fbc_nohp.H
+// *! DESCRIPTION : Fabric configuration (non-hotplug) functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_BUILD_SMP_FBC_NOHP_H_
+#define _PROC_BUILD_SMP_FBC_NOHP_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_build_smp.H"
+#include "p8_scom_addresses.H"
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// enumerate chips per group configurations
+enum proc_build_smp_chips_per_group {
+    PROC_BUILD_SMP_1CPG = 0x0,
+    PROC_BUILD_SMP_2CPG = 0x1,
+    PROC_BUILD_SMP_4CPG = 0x2
+};
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+//
+// PB Mode register field/bit definitions
+//
+
+const uint32_t PB_MODE_CHIP_IS_SYSTEM_BIT = 4;
+
+const uint32_t PB_MODE_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
+{
+    PB_MODE_WEST_0x02010C0A,
+    PB_MODE_CENT_0x02010C4A,
+    PB_MODE_EAST_0x02010C8A
+};
+
+
+//
+// Group/Remote Group/System Command Pacing Rate register field/bit definitions
+//
+
+const uint8_t PROC_BUILD_SMP_DP_LEVELS = 8;
+
+const uint8_t PB_GP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   1,   2,   3,   4,   5,   6,   7,   8 };
+const uint8_t PB_GP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   2,   4,   6,   8,   8,   8,   8,   8 };
+const uint8_t PB_RGP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,   9,   9,   9,  10,  10,  11,  12 };
+const uint8_t PB_RGP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  13,  14,  15,  16 };
+const uint8_t PB_SP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   9,  10,  11,  12,  13,  14,  15,  16 };
+const uint8_t PB_SP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  13,  14,  16,  18,  20,  22,  24 };
+
+const uint8_t PB_GP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   3,   4,   5,   6,   7,   8,  10,  16 };
+const uint8_t PB_GP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   4,   5,   6,   7,   8,  10,  12,  16 };
+const uint8_t PB_RGP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  13,  14,  16,  32 };
+const uint8_t PB_RGP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = {  12,  13,  14,  15,  16,  20,  32,  32 };
+const uint8_t PB_SP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  13,  14,  15,  16,  20,  32,  64 };
+const uint8_t PB_SP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  20,  22,  24,  26,  32,  40,  64,  64 };
+
+const uint8_t PB_GP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   3,   4,   5,   6,   8,  10,  16,  32 };
+const uint8_t PB_GP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   4,   6,   8,  12,  16,  20,  32,  32 };
+const uint8_t PB_RGP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  16,  20,  32,  64 };
+const uint8_t PB_RGP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = {  12,  14,  16,  24,  32,  40,  64,  64 };
+const uint8_t PB_SP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  14,  16,  24,  32,  40,  64, 128 };
+const uint8_t PB_SP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  20,  24,  32,  48,  64,  80, 128, 128 };
+
+const uint32_t PB_SCOPE_COMMAND_PACING_LVL_START_BIT[PROC_BUILD_SMP_DP_LEVELS] = {  0,  8, 16, 24, 32, 40, 48, 56 };
+const uint32_t PB_SCOPE_COMMAND_PACING_LVL_END_BIT[PROC_BUILD_SMP_DP_LEVELS]   = {  7, 15, 23, 31, 39, 47, 55, 63 };
+
+
+// define set of group scope command pacing rate settings
+struct proc_build_smp_gp_low_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_LO_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_LO_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_LO_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+struct proc_build_smp_gp_high_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_HI_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_HI_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_HI_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+struct proc_build_smp_sp_low_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_LO_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_LO_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_LO_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+struct proc_build_smp_sp_high_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_HI_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_HI_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_HI_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+struct proc_build_smp_rgp_low_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_LO_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_LO_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_LO_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+struct proc_build_smp_rgp_high_pacing_table
+{
+    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
+    {
+        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
+        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_HI_1CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_HI_2CPG));
+        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_HI_4CPG));
+        return m;
+    }
+    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
+};
+
+
+//
+// X Link Mode register field/bit definitions
+//
+
+const uint32_t PB_X_MODE_TRACE_ENABLE_BIT = 4;
+const uint32_t PB_X_MODE_TRACE_SELECT_START_BIT = 5;
+const uint32_t PB_X_MODE_TRACE_SELECT_END_BIT = 7;
+
+
+//
+// A Link Trace register field/bit definitions
+//
+
+const uint32_t PB_A_TRACE_A0_OUT_SEL0_START_BIT = 0;
+const uint32_t PB_A_TRACE_A0_OUT_SEL0_END_BIT = 1;
+const uint32_t PB_A_TRACE_A0_OUT_SEL1_START_BIT = 2;
+const uint32_t PB_A_TRACE_A0_OUT_SEL1_END_BIT = 3;
+const uint32_t PB_A_TRACE_A0_OUT_SEL2_START_BIT = 4;
+const uint32_t PB_A_TRACE_A0_OUT_SEL2_END_BIT = 5;
+const uint32_t PB_A_TRACE_A1_OUT_SEL0_START_BIT = 6;
+const uint32_t PB_A_TRACE_A1_OUT_SEL0_END_BIT = 7;
+const uint32_t PB_A_TRACE_A1_OUT_SEL1_START_BIT = 8;
+const uint32_t PB_A_TRACE_A1_OUT_SEL1_END_BIT = 9;
+const uint32_t PB_A_TRACE_A1_OUT_SEL2_START_BIT = 10;
+const uint32_t PB_A_TRACE_A1_OUT_SEL2_END_BIT = 11;
+const uint32_t PB_A_TRACE_A2_OUT_SEL0_START_BIT = 12;
+const uint32_t PB_A_TRACE_A2_OUT_SEL0_END_BIT = 13;
+const uint32_t PB_A_TRACE_A2_OUT_SEL1_START_BIT = 14;
+const uint32_t PB_A_TRACE_A2_OUT_SEL1_END_BIT = 15;
+const uint32_t PB_A_TRACE_A2_OUT_SEL2_START_BIT = 16;
+const uint32_t PB_A_TRACE_A2_OUT_SEL2_END_BIT = 17;
+
+//
+// F Link Trace register field/bit definitions
+//
+
+const uint32_t PB_F_TRACE_F0_OUT_SEL0_START_BIT = 0;
+const uint32_t PB_F_TRACE_F0_OUT_SEL0_END_BIT = 3;
+const uint32_t PB_F_TRACE_F0_OUT_SEL1_START_BIT = 8;
+const uint32_t PB_F_TRACE_F0_OUT_SEL1_END_BIT = 11;
+const uint32_t PB_F_TRACE_F1_OUT_SEL0_START_BIT = 16;
+const uint32_t PB_F_TRACE_F1_OUT_SEL0_END_BIT = 19;
+const uint32_t PB_F_TRACE_F1_OUT_SEL1_START_BIT = 24;
+const uint32_t PB_F_TRACE_F1_OUT_SEL1_END_BIT = 27;
+const uint32_t PB_F_TRACE_F0_OBS_SEL = 32;
+const uint32_t PB_F_TRACE_F1_OBS_SEL = 33;
+
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: program fabric configuration registers (non-hotplug)
+// parameters: i_smp => structure encapsulating SMP topology
+// returns: FAPI_RC_SUCCESS if register programming is successful,
+//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
+//              small/large,
+//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
+//              is unsuccessful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_build_smp_set_fbc_nohp(
+    proc_build_smp_system& i_smp);
+
+} // extern "C"
+
+#endif // _PROC_BUILD_SMP_FBC_NOHP_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml
new file mode 100644
index 000000000..635d4e920
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml
@@ -0,0 +1,92 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- proc_fab_smp_fabric_attributes.xml -->
+<attributes>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_CORE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      firmware notes:
+        Nominal processor's core DPLL frequency (MHz).
+        Default value provided by Machine Readable Workbook.
+        This attribute is the current value.
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_EPS_GB_PERCENTAGE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      firmware notes:
+        Guardband percentage to apply to baseline epsilon values
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_EPS_GB_DIRECTION</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      firmware notes:
+        Direction to apply guardband margin (positive/negative)
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <enum>POSITIVE = 0x0, NEGATIVE = 0x1</enum>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      firmware notes:
+        Set to force all asynchronous boundary crossings into safe mode.
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <enum>PERFORMANCE_MODE = 0x0, SAFE_MODE = 0x1</enum>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_NOT_F_LINK</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      firmware notes:
+        Set IPL time mux/switch between PCIE PHB/F link function
+        (one per foreign link)
+    </description>
+    <valueType>uint8</valueType>
+    <array>2</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H
new file mode 100644
index 000000000..a4ec1264c
--- /dev/null
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H
@@ -0,0 +1,96 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_fbc_utils.H,v 1.2 2012/04/27 06:49:15 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_fbc_utils.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_fbc_utils.H
+// *! DESCRIPTION : PBA library functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_FBC_UTILS_H_
+#define _PROC_FBC_UTILS_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "p8_scom_addresses.H"
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// address range definitions
+const uint64_t PROC_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 50)-1ULL);
+const uint64_t PROC_FBC_UTILS_CACHELINE_MASK = 0x7FULL;
+const uint64_t PROC_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
+
+// PB Mode register field bit/definitions
+const uint32_t PB_MODE_FBC_INIT_BIT = 0;
+
+// ADU pMISC Mode register field/bit definitions
+const uint32_t ADU_PMISC_MODE_DISABLE_CHECKSTOP_BIT = 19;
+const uint32_t ADU_PMISC_MODE_MANUAL_CLEAR_FBC_STOP_BIT = 21;
+const uint32_t ADU_PMISC_MODE_FBC_STOP_BIT = 22;
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+// function: read PB Mode & ADU pMisc Mode registers to check state of fabric
+//           init and stop control signals
+// parameters: i_target         => P8 chip target
+//             o_is_initialized => return state of fabric init signal
+//             o_is_running     => return state of fabric pervasive stop control
+// returns: FAPI_RC_SUCCESS if SCOM reads are successful,
+//          else error
+fapi::ReturnCode proc_fbc_utils_get_fbc_state(
+    const fapi::Target& i_target,
+    bool& o_is_initialized,
+    bool& o_is_running);
+
+
+// function: read-modify-write ADU pMisc Mode register to clear fabric stop
+//           signal (override stop caused by checkstop)
+// parameters: i_target         => P8 chip target
+// returns: FAPI_RC_SUCCESS if SCOM sequence is successful,
+//          else error
+fapi::ReturnCode proc_fbc_utils_override_fbc_stop(
+    const fapi::Target& i_target);
+
+
+} // extern "C"
+
+#endif // _PROC_FBC_UTILS_H_
diff --git a/src/usr/hwpf/hwp/bus_training/makefile b/src/usr/hwpf/hwp/bus_training/makefile
index dd17dd43f..3fa717649 100644
--- a/src/usr/hwpf/hwp/bus_training/makefile
+++ b/src/usr/hwpf/hwp/bus_training/makefile
@@ -34,7 +34,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 ## pointer to common HWP files
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
 
-OBJS =  gcr_funcs.o io_funcs.o io_run_training.o
+OBJS =  gcr_funcs.o io_funcs.o io_run_training.o pbusLinkSvc.o proc_fab_smp.o
 
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ## vpath   %.C proc_cen_framelock:io_run_training
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/pbusLinkSvc.C b/src/usr/hwpf/hwp/bus_training/pbusLinkSvc.C
index 22cf3bfa6..22cf3bfa6 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/pbusLinkSvc.C
+++ b/src/usr/hwpf/hwp/bus_training/pbusLinkSvc.C
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/pbusLinkSvc.H b/src/usr/hwpf/hwp/bus_training/pbusLinkSvc.H
index ee2caffd5..ee2caffd5 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/pbusLinkSvc.H
+++ b/src/usr/hwpf/hwp/bus_training/pbusLinkSvc.H
diff --git a/src/usr/hwpf/hwp/bus_training/proc_fab_smp.C b/src/usr/hwpf/hwp/bus_training/proc_fab_smp.C
new file mode 100644
index 000000000..8f97676d8
--- /dev/null
+++ b/src/usr/hwpf/hwp/bus_training/proc_fab_smp.C
@@ -0,0 +1,288 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/proc_fab_smp.C $                */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_fab_smp.C,v 1.7 2012/09/24 05:00:12 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_fab_smp.C
+// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "proc_fab_smp.H"
+
+extern "C" {
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return fabric node ID attribute
+// parameters: i_target  => pointer to chip target
+//             o_node_id => structure encapsulating node ID value
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_node_id_attr(
+    const fapi::Target* i_target,
+    proc_fab_smp_node_id& o_node_id)
+{
+    // return code
+    fapi::ReturnCode rc;
+    // temporary attribute storage used to build procedure data structures
+    uint8_t node_id_attr;
+
+    // mark function entry
+    FAPI_DBG("proc_fab_smp_get_node_id_attr: Start");
+
+    do
+    {
+        // retrieve node ID attribute
+        rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID,
+                           i_target,
+                           node_id_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_fab_smp_get_node_id_attr: Error querying ATTR_FABRIC_NODE_ID");
+            break;
+        }
+
+        // print attribute value
+        FAPI_DBG("proc_fab_smp_get_node_id_attr: ATTR_FABRIC_NODE_ID = 0x%X",
+                 node_id_attr);
+
+        // translate to output value
+        switch (node_id_attr)
+        {
+            case 0:
+                o_node_id = FBC_NODE_ID_0;
+                break;
+            case 1:
+                o_node_id = FBC_NODE_ID_1;
+                break;
+            case 2:
+                o_node_id = FBC_NODE_ID_2;
+                break;
+            case 3:
+                o_node_id = FBC_NODE_ID_3;
+                break;
+            case 4:
+                o_node_id = FBC_NODE_ID_4;
+                break;
+            case 5:
+                o_node_id = FBC_NODE_ID_5;
+                break;
+            case 6:
+                o_node_id = FBC_NODE_ID_6;
+                break;
+            case 7:
+                o_node_id = FBC_NODE_ID_7;
+                break;
+            default:
+                FAPI_ERR("proc_fab_smp_get_node_id_attr: Invalid fabric node ID attribute value 0x%02X",
+                         node_id_attr);
+                const uint8_t& ATTR_DATA = node_id_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR);
+                break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_fab_smp_get_node_id_attr: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return fabric chip ID attribute
+// parameters: i_target  => pointer to chip target
+//             o_chip_id => structure encapsulating chip ID value
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_chip_id_attr(
+    const fapi::Target* i_target,
+    proc_fab_smp_chip_id& o_chip_id)
+{
+    // return code
+    fapi::ReturnCode rc;
+    // temporary attribute storage used to build procedure data structures
+    uint8_t chip_id_attr;
+
+    // mark function entry
+    FAPI_DBG("proc_fab_smp_get_chip_id_attr: Start");
+
+    do
+    {
+        // retrieve chip ID attribute
+        rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID,
+                           i_target,
+                           chip_id_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error querying ATTR_FABRIC_CHIP_ID");
+            break;
+        }
+
+        // print attribute value
+        FAPI_DBG("proc_fab_smp_get_chip_id_attr: ATTR_FABRIC_CHIP_ID = 0x%X",
+                 chip_id_attr);
+
+        // translate to output value
+        switch (chip_id_attr)
+        {
+            case 0:
+                o_chip_id = FBC_CHIP_ID_0;
+                break;
+            case 1:
+                o_chip_id = FBC_CHIP_ID_1;
+                break;
+            case 2:
+                o_chip_id = FBC_CHIP_ID_2;
+                break;
+            case 3:
+                o_chip_id = FBC_CHIP_ID_3;
+                break;
+            case 4:
+                o_chip_id = FBC_CHIP_ID_4;
+                break;
+            case 5:
+                o_chip_id = FBC_CHIP_ID_5;
+                break;
+            case 6:
+                o_chip_id = FBC_CHIP_ID_6;
+                break;
+            case 7:
+                o_chip_id = FBC_CHIP_ID_7;
+                break;
+            default:
+                FAPI_ERR("proc_fab_smp_get_chip_id_attr: Invalid fabric chip ID attribute value 0x%02X",
+                         chip_id_attr);
+                const uint8_t& ATTR_DATA = chip_id_attr;
+                FAPI_SET_HWP_ERROR(rc,
+                    RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR);
+                break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_fab_smp_get_chip_id_attr: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return PCIe/DSMP mux attribute values
+// parameters: i_target          => pointer to chip target
+//             o_pcie_not_f_link => vector of boolean values representing state
+//                                  of PCIe/DSMP mux settings (one value per
+//                                  foreign link, true=PCIe function, false=
+//                                  DSMP function)
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs(
+    const fapi::Target* i_target,
+    bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS])
+{
+    // return code
+    fapi::ReturnCode rc;
+    // temporary attribute storage used to build procedure data structures
+    uint8_t pcie_not_f_link_attr[PROC_FAB_SMP_NUM_F_LINKS];
+
+    // mark function entry
+    FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: Start");
+
+    do
+    {
+        // retrieve PCIe/DSMP mux attributes
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NOT_F_LINK,
+                           i_target,
+                           pcie_not_f_link_attr);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Error querying ATTR_PROC_PCIE_NOT_F_LINK");
+            break;
+        }
+
+        // loop over all links
+        for (uint8_t l = 0;
+             l < PROC_FAB_SMP_NUM_F_LINKS;
+             l++)
+        {
+            // print attribute value
+            FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: ATTR_PROC_PCIE_NOT_F_LINK[%d] = 0x%X",
+                     l, pcie_not_f_link_attr[l]);
+
+            // validate attribute value
+            switch (pcie_not_f_link_attr[l])
+            {
+                case 0:
+                    o_pcie_not_f_link[l] = false;
+                    break;
+                case 1:
+                    o_pcie_not_f_link[l] = true;
+                    break;
+                default:
+                    FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Invalid PCIe/DSMP mux attribute value 0x%02X",
+                             pcie_not_f_link_attr[l]);
+                    const uint8_t& ATTR_DATA = pcie_not_f_link_attr[l];
+                    FAPI_SET_HWP_ERROR(rc,
+                        RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR);
+                    break;
+            }
+            if (!rc.ok())
+            {
+                break;
+            }
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: End");
+    return rc;
+}
+
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/proc_fab_smp.H b/src/usr/hwpf/hwp/bus_training/proc_fab_smp.H
new file mode 100644
index 000000000..3b235161f
--- /dev/null
+++ b/src/usr/hwpf/hwp/bus_training/proc_fab_smp.H
@@ -0,0 +1,160 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/proc_fab_smp.H $                */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_fab_smp.H,v 1.6 2012/09/24 05:00:15 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_fab_smp.H
+// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_FAB_SMP_H_
+#define _PROC_FAB_SMP_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// define set of supported fabric node ID values
+enum proc_fab_smp_node_id
+{
+    FBC_NODE_ID_0 = 0,
+    FBC_NODE_ID_1 = 1,
+    FBC_NODE_ID_2 = 2,
+    FBC_NODE_ID_3 = 3,
+    FBC_NODE_ID_4 = 4,
+    FBC_NODE_ID_5 = 5,
+    FBC_NODE_ID_6 = 6,
+    FBC_NODE_ID_7 = 7
+};
+
+// define set of supported fabric chip ID values
+enum proc_fab_smp_chip_id
+{
+    FBC_CHIP_ID_0 = 0,
+    FBC_CHIP_ID_1 = 1,
+    FBC_CHIP_ID_2 = 2,
+    FBC_CHIP_ID_3 = 3,
+    FBC_CHIP_ID_4 = 4,
+    FBC_CHIP_ID_5 = 5,
+    FBC_CHIP_ID_6 = 6,
+    FBC_CHIP_ID_7 = 7
+};
+
+// define set of supported epsilon table types
+enum proc_fab_smp_eps_table_type
+{
+    PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE = 0,
+    PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE = 1
+};
+
+// define set of supported broadcast/pump modes
+enum proc_fab_smp_pump_mode
+{
+    PROC_FAB_SMP_PUMP_MODE1 = 1,
+    PROC_FAB_SMP_PUMP_MODE2 = 2
+};
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// largest representable fabric real address given HW implementation
+const uint64_t PROC_FAB_SMP_MAX_ADDRESS = ((1ULL << 50)-1ULL);
+
+// number of links supported per chip
+const uint8_t PROC_FAB_SMP_NUM_A_LINKS = 3;
+const uint8_t PROC_FAB_SMP_NUM_X_LINKS = 4;
+const uint8_t PROC_FAB_SMP_NUM_F_LINKS = 2;
+
+// range of fabric node/chip ID fields
+const uint8_t PROC_FAB_SMP_NUM_CHIP_IDS = 8;
+const uint8_t PROC_FAB_SMP_NUM_NODE_IDS = 8;
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return fabric node ID attribute
+// parameters: i_target  => pointer to P8 chip target
+//             o_node_id => structure encapsulating node ID value
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_node_id_attr(
+    const fapi::Target* i_target,
+    proc_fab_smp_node_id& o_node_id);
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return fabric chip ID attribute
+// parameters: i_target  => pointer to P8 chip target
+//             o_chip_id => structure encapsulating chip ID value
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_chip_id_attr(
+    const fapi::Target* i_target,
+    proc_fab_smp_chip_id& o_chip_id);
+
+//------------------------------------------------------------------------------
+// function: utility function to read & return PCIe/DSMP mux attribute values
+// parameters: i_target          => pointer to P8 chip target
+//             o_pcie_not_f_link => vector of boolean values representing state
+//                                  of PCIe/DSMP mux settings (one value per
+//                                  foreign link, true=PCIe function, false=
+//                                  DSMP function)
+// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
+//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
+//              invalid,
+//          else FAPI_ATTR_GET return code
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs(
+    const fapi::Target* i_target,
+    bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]);
+
+
+} // extern "C"
+
+#endif // _PROC_FAB_SMP_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml
deleted file mode 100644
index 5d590c998..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml
+++ /dev/null
@@ -1,41 +0,0 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END_TAG -->
-<!-- Error definitions for proc_fab_smp -->
-<hwpErrors>
-  <!-- *********************************************************************** -->
-  <hwpError>
-    <rc>RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR</rc>
-    <description>Invalid definition for PCIe/DSMP mux attribute value.</description>
-    <ffdc>ATTR_DATA</ffdc>
-  </hwpError>
-  <hwpError>
-    <rc>RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR</rc>
-    <description>Invalid definition for fabric node ID attribute value.</description>
-    <ffdc>ATTR_DATA</ffdc>
-  </hwpError>
-  <hwpError>
-    <rc>RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR</rc>
-    <description>Invalid definition for fabric chip ID attribute value.</description>
-    <ffdc>ATTR_DATA</ffdc>
-  </hwpError>
-</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml
deleted file mode 100644
index ac9ab578c..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml
+++ /dev/null
@@ -1,54 +0,0 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-
-     $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml $
-
-     IBM CONFIDENTIAL
-
-     COPYRIGHT International Business Machines Corp. 2012
-
-     p1
-
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-
-     Origin: 30
-
-     IBM_PROLOG_END_TAG -->
-<!-- proc_fab_smp_fabric_attributes.xml -->
-<attributes>
-  <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_FREQ_CORE</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>
-      firmware notes:
-        Nominal processor's core DPLL frequency (MHz).
-        Default value provided by Machine Readable Workbook.
-        This attribute is the current value.
-    </description>
-    <valueType>uint32</valueType>
-    <writeable/>
-    <persistRuntime/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_PROC_PCIE_NOT_F_LINK</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      firmware notes:
-        Set IPL time mux/switch between PCIE PHB/F link function
-        (one per foreign link)
-    </description>
-    <valueType>uint8</valueType>
-    <array>2</array>
-    <platInit/>
-    <persistRuntime/>
-   </attribute>
-   <!-- ********************************************************************* -->
-</attributes>
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C
index c98a216fc..bc51f6dee 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C
+++ b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C
@@ -59,7 +59,7 @@
 #include    <fapiPlatHwpInvoker.H>
 
 #include    "edi_ei_initialization.H"
-#include    "pbusLinkSvc.H"
+#include    <pbusLinkSvc.H>
 
 //  Uncomment these files as they become available:
 // #include    "fabric_erepair/fabric_erepair.H"
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/makefile b/src/usr/hwpf/hwp/edi_ei_initialization/makefile
index 44318856e..41a30accb 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/makefile
+++ b/src/usr/hwpf/hwp/edi_ei_initialization/makefile
@@ -47,8 +47,8 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_
 
 
 ##  NOTE: add new object files when you add a new HWP
-OBJS =  edi_ei_initialization.o pbusLinkSvc.o \
-        proc_fab_iovalid.o proc_fab_smp.o fabric_io_run_training.o
+OBJS =  edi_ei_initialization.o \
+        proc_fab_iovalid.o fabric_io_run_training.o
 
         
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.C b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.C
deleted file mode 100644
index d046d869e..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.C
+++ /dev/null
@@ -1,186 +0,0 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
-// $Id: proc_fab_smp.C,v 1.3 2012/04/27 18:20:00 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-// *|
-// *! TITLE       : proc_fab_smp.C
-// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_fab_smp.H"
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode proc_fab_smp_validate_smp(
-    std::vector<proc_fab_smp_proc_chip *>& i_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    // iterator defintions
-    std::vector<proc_fab_smp_proc_chip *>::iterator smp_chip;
-    std::vector<proc_fab_smp_x_bus *>::iterator x_bus;
-    std::vector<proc_fab_smp_a_bus *>::iterator a_bus;
-
-    do
-    {
-        // mark function entry
-        FAPI_DBG("proc_fab_smp_validate_smp: Start");
-
-        FAPI_DBG("proc_fab_smp_validate_smp: *************************************");
-        for (smp_chip = i_smp.begin(); smp_chip != i_smp.end(); smp_chip++)
-        {
-            // ensure that proc_fab_smp_proc_chip pointer is non NULL
-            if ((*smp_chip) == NULL)
-            {
-                FAPI_ERR("proc_fab_smp_validate_smp: Invalid NULL proc_fab_smp_proc_chip pointer");
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_PROC_CHIP_ARG);
-                break;
-            }
-
-            // display target information for this chip
-            FAPI_DBG("proc_fab_smp_validate_smp: Target: %s", (*smp_chip)->this_chip.toEcmdString());
-
-            // display information about X bus connections
-            for (x_bus = (*smp_chip)->x_busses.begin();
-                 x_bus != (*smp_chip)->x_busses.end();
-                 x_bus++)
-            {
-                // ensure that proc_fab_smp_x_bus pointer & enclosed destination
-                // chip pointers are non NULL
-                if ((*x_bus == NULL) ||
-                    ((*x_bus)->dest_chip == NULL))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Invalid/NULL proc_fab_smp_x_bus pointer");
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_X_BUS_ARG);
-                    break;
-                }
-                // validate source/destination bus ID values
-                if (((*x_bus)->src_chip_bus_id != FBC_BUS_X0) &&
-                    ((*x_bus)->src_chip_bus_id != FBC_BUS_X1) &&
-                    ((*x_bus)->src_chip_bus_id != FBC_BUS_X2) &&
-                    ((*x_bus)->src_chip_bus_id != FBC_BUS_X3))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Unsupported source X bus ID value 0x%x presented",
-                             (*x_bus)->src_chip_bus_id);
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_X_BUS_ARG);
-                    break;
-                }
-                if (((*x_bus)->dest_chip_bus_id != FBC_BUS_X0) &&
-                    ((*x_bus)->dest_chip_bus_id != FBC_BUS_X1) &&
-                    ((*x_bus)->dest_chip_bus_id != FBC_BUS_X2) &&
-                    ((*x_bus)->dest_chip_bus_id != FBC_BUS_X3))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Unsupported destination X bus ID value 0x%x presented",
-                             (*x_bus)->dest_chip_bus_id);
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_X_BUS_ARG);
-                    break;
-                }
-                FAPI_DBG("proc_fab_smp_validate_smp: X%d [ Target: %s X%d]",
-                         (*x_bus)->src_chip_bus_id,
-                         (*x_bus)->dest_chip->toEcmdString(),
-                         (*x_bus)->dest_chip_bus_id);
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-
-            // display information about A bus connections
-            for (a_bus = (*smp_chip)->a_busses.begin();
-                 a_bus != (*smp_chip)->a_busses.end();
-                 a_bus++)
-            {
-                // ensure that proc_fab_smp_a_bus pointer & enclosed destination
-                // chip pointers are non NULL
-                if ((*a_bus == NULL) ||
-                    ((*a_bus)->dest_chip == NULL))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Invalid/NULL proc_fab_smp_a_bus pointer");
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_A_BUS_ARG);
-                    break;
-                }
-                // validate source/destination bus ID values
-                if (((*a_bus)->src_chip_bus_id != FBC_BUS_A0) &&
-                    ((*a_bus)->src_chip_bus_id != FBC_BUS_A1) &&
-                    ((*a_bus)->src_chip_bus_id != FBC_BUS_A2))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Unsupported source A bus ID value 0x%x presented",
-                             (*a_bus)->src_chip_bus_id);
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_A_BUS_ARG);
-                    break;
-                }
-                if (((*a_bus)->dest_chip_bus_id != FBC_BUS_A0) &&
-                    ((*a_bus)->dest_chip_bus_id != FBC_BUS_A1) &&
-                    ((*a_bus)->dest_chip_bus_id != FBC_BUS_A2))
-                {
-                    FAPI_ERR("proc_fab_smp_validate_smp: Unsupported destination A bus ID value 0x%x presented",
-                             (*a_bus)->dest_chip_bus_id);
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_A_BUS_ARG);
-                    break;
-                }
-                FAPI_DBG("proc_fab_smp_validate_smp: A%d [ Target: %s A%d]",
-                         (*a_bus)->src_chip_bus_id,
-                         (*a_bus)->dest_chip->toEcmdString(),
-                         (*a_bus)->dest_chip_bus_id);
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-
-            FAPI_DBG("proc_fab_smp_validate_smp:");
-        }
-        FAPI_DBG("proc_fab_smp_validate_smp: *************************************");
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_smp_validate_smp: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.H b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.H
deleted file mode 100644
index ae904b1c5..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.H
+++ /dev/null
@@ -1,131 +0,0 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
-// $Id: proc_fab_smp.H,v 1.2 2012/03/19 03:18:39 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-// *|
-// *! TITLE       : proc_fab_smp.H
-// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *! Define interface structures which pass SMP connectivity information
-// *! between platform and FAPI HWP code.
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_FAB_SMP_H_
-#define _PROC_FAB_SMP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// define set of supported X busses
-enum proc_fab_smp_x_bus_id
-{
-    FBC_BUS_X0 = 0,
-    FBC_BUS_X1 = 1,
-    FBC_BUS_X2 = 2,
-    FBC_BUS_X3 = 3
-};
-
-// define set of supported A busses
-enum proc_fab_smp_a_bus_id
-{
-    FBC_BUS_A0 = 0,
-    FBC_BUS_A1 = 1,
-    FBC_BUS_A2 = 2
-};
-
-// encapsulate X bus connectivity information (relative to source chip):
-//   source bus ID
-//   destination bus ID, pointer to destination target
-struct proc_fab_smp_x_bus
-{
-    proc_fab_smp_x_bus_id src_chip_bus_id;
-    fapi::Target*         dest_chip;
-    proc_fab_smp_x_bus_id dest_chip_bus_id;
-};
-
-// encapsulate A bus connectivity information (relative to source chip):
-//   source bus ID
-//   destination bus ID, and pointer to destination target
-struct proc_fab_smp_a_bus
-{
-    proc_fab_smp_a_bus_id src_chip_bus_id;
-    fapi::Target*         dest_chip;
-    proc_fab_smp_a_bus_id dest_chip_bus_id;
-};
-
-// structure to document target/fabric connectivity for a single chip
-// in the SMP topology
-struct proc_fab_smp_proc_chip
-{
-    // target associated with this chip
-    fapi::Target this_chip;
-    // X bus connections
-    std::vector<proc_fab_smp_x_bus*> x_busses;
-    // A bus connections
-    std::vector<proc_fab_smp_a_bus*> a_busses;
-};
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-// function: validate & display SMP topology
-// parameters: i_smp => vector of proc_fab_smp_chip structures which
-//                      defines scope of SMP fabric & bus connectivity
-// returns: FAPI_RC_SUCCESS if topology is valid,
-//          RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_PROC_CHIP_ARG
-//              if invalid/NULL proc_fab_smp_proc_chip argument is passed
-//              in HWP argument vector
-//          RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_A_BUS_ARG
-//              if invalid/NULL proc_fab_smp_a_bus argument is passed
-//              in HWP argument vector
-//          RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_X_BUS_ARG
-//              if invalid/NULL proc_fab_smp_x_bus argument is passed
-//              in HWP argument vector
-//          else FAPI getscom/putscom return code for failing operation
-fapi::ReturnCode proc_fab_smp_validate_smp(
-    std::vector<proc_fab_smp_proc_chip *>& i_smp);
-
-} // extern "C"
-
-#endif // _PROC_FAB_SMP_H_
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml
index 9caa67fe8..4893352c2 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml
+++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml
@@ -1,38 +1,71 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
-<!-- Error definitions for proc_fab_smp library -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_fab_smp -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_PROC_CHIP_ARG</rc>
-    <description>Invalid/NULL proc_fab_smp_proc_chip_argument passed in HWP argument vector.</description>
+    <rc>RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR</rc>
+    <description>Invalid definition for PCIe/DSMP mux attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
   </hwpError>
   <hwpError>
-    <rc>RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_A_BUS_ARG</rc>
-    <description>Invalid/NULL proc_fab_smp_a_bus argument passed in HWP argument vector.</description>
+    <rc>RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR</rc>
+    <description>Invalid definition for fabric node ID attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
   </hwpError>
   <hwpError>
-    <rc>RC_PROC_FAB_SMP_INVALID_PROC_FAB_SMP_X_BUS_ARG</rc>
-    <description>Invalid/NULL proc_fab_smp_x_bus argument passed in HWP argument vector.</description>
+    <rc>RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR</rc>
+    <description>Invalid definition for fabric chip ID attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR</rc>
+    <description>Invalid definition for epsilon table type attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR</rc>
+    <description>Invalid definition for epsilon guardband direction attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR</rc>
+    <description>Invalid definition for fabric async safe mode attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_PUMP_MODE_ATTR_ERR</rc>
+    <description>Invalid definition for fabric pump mode attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR</rc>
+    <description>Invalid definition for X bus width attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR</rc>
+    <description>Invalid definition for MCS interleaving attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
   </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/fapiTestHwpAttr.C b/src/usr/hwpf/hwp/fapiTestHwpAttr.C
index 83371db6d..bb7701595 100755
--- a/src/usr/hwpf/hwp/fapiTestHwpAttr.C
+++ b/src/usr/hwpf/hwp/fapiTestHwpAttr.C
@@ -128,31 +128,6 @@ fapi::ReturnCode hwpTestAttributes()
         }
 
         //----------------------------------------------------------------------
-        // Test ATTR_L2_R_T0_EPS
-        //----------------------------------------------------------------------
-        {
-            TARGETING::PredicateCTM l_pred(TARGETING::CLASS_UNIT,
-                                                      TARGETING::TYPE_EX);
-            TARGETING::TargetRangeFilter l_filter(
-                                    TARGETING::targetService().begin(),
-                                    TARGETING::targetService().end(), &l_pred);
-            // Use the first EX chiplet
-            if (l_filter)
-            {
-                uint32_t l_tmp;
-                fapi::Target l_target(fapi::TARGET_TYPE_EX_CHIPLET, *l_filter);
-                fapi::Target * l_pTarget = &l_target;
-
-                l_rc = FAPI_ATTR_GET(ATTR_L2_R_T0_EPS, l_pTarget, l_tmp);
-                if (l_rc)
-                {
-                    FAPI_ERR("hwpTestAttributes: L2/L3 ATTR. Error from GET");
-                    break;
-                }
-            }
-        }
-
-        //----------------------------------------------------------------------
         // Test ATTR_SCRATCH_UINT8_1
         //----------------------------------------------------------------------
         {
diff --git a/src/usr/hwpf/hwp/freq_attributes.xml b/src/usr/hwpf/hwp/freq_attributes.xml
index fde70fd10..3b68ff85e 100644
--- a/src/usr/hwpf/hwp/freq_attributes.xml
+++ b/src/usr/hwpf/hwp/freq_attributes.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/freq_attributes.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/freq_attributes.xml $                        -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!--
     XML file specifying HWPF attributes.
     These are frequency attributes.
@@ -77,6 +77,8 @@
         reads ATTR_FREQ_PROC_REFCLOCK and the PB PLL settings.
     </description>
     <valueType>uint32</valueType>
+    <writeable/>
+    <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
@@ -88,6 +90,8 @@
       This is set by the HWP that sets up the A-bus PLL.
     </description>
     <valueType>uint32</valueType>
+    <writeable/>
+    <platInit/>
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
@@ -96,8 +100,23 @@
     <description>
       The frequency of a processor's X-bus chiplet in MHz.
       This is the same for all X-bus chiplets in the system.
-      This is set by the HWP that sets up the X-bus PLL. 
+      This is set by the HWP that sets up the X-bus PLL.
     </description>
     <valueType>uint32</valueType>
+    <writeable/>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_PCIE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      The frequency of a processor's PCI-e bus in MHz.
+      This is the same for all PCI-e busses in the system.
+      This is set by the HWP that sets up the PCI-e PLL.
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <platInit/>
   </attribute>
 </attributes>
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index d97bc37cf..0cab1a5a9 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -41,13 +41,14 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/mvpd_errors.xml \
     ../pore/fapiporeve/fapiPoreVe_errors.xml \
     hwp/dram_initialization/proc_setup_bars/proc_setup_bars_errors.xml  \
-    hwp/dram_initialization/proc_setup_bars/proc_fab_smp_errors.xml     \
     hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml  \
     hwp/build_winkle_images/p8_pba_bar_config/p8_pba_bar_config_errors.xml \
     hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml \
     hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml \
     hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml \
     hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml \
+    hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml \
+    hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml \
     hwp/thread_activate/proc_thread_control/proc_thread_control.xml
 
 
@@ -68,7 +69,7 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \
-                     hwp/dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml
+                     hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml
 
 #------------------------------------------------------------------------------
 # Initfiles
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 5f61d3ce4..a52b34232 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -2948,7 +2948,6 @@
         <uint8_t></uint8_t>
     </simpleType>
     <persistency>non-volatile</persistency>
-    <hasStringConversion/>
     <readable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_EPS_TABLE_TYPE</id>
@@ -2982,7 +2981,6 @@
         <uint8_t></uint8_t>
     </simpleType>
     <persistency>non-volatile</persistency>
-    <hasStringConversion/>
     <readable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_FABRIC_PUMP_MODE</id>
@@ -3014,7 +3012,6 @@
         <uint8_t></uint8_t>
     </simpleType>
     <persistency>non-volatile</persistency>
-    <hasStringConversion/>
     <readable/>
     <hwpfToHbAttrMap>
         <id>ATTR_PROC_X_BUS_WIDTH</id>
@@ -3158,8 +3155,9 @@
           reads ATTR_FREQ_PROC_REFCLOCK and the PB PLL settings.
     </description>
     <simpleType><uint32_t></uint32_t></simpleType>
-    <persistency>volatile-zeroed</persistency>
+    <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_FREQ_PB</id>
         <macro>DIRECT</macro>
@@ -3176,8 +3174,9 @@
         - Is set by the HWP that sets up the A-bus PLL.
     </description>
     <simpleType><uint32_t></uint32_t></simpleType>
-    <persistency>volatile-zeroed</persistency>
+    <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_FREQ_A</id>
         <macro>DIRECT</macro>
@@ -3194,8 +3193,9 @@
         - Is set by the HWP that sets up the X-bus PLL.
     </description>
     <simpleType><uint32_t></uint32_t></simpleType>
-    <persistency>volatile-zeroed</persistency>
+    <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/>
     <hwpfToHbAttrMap>
         <id>ATTR_FREQ_X</id>
         <macro>DIRECT</macro>
@@ -3990,7 +3990,7 @@
   </description>
   <simpleType>
       <uint8_t>
-          <default>0,0</default>
+          <default>1,1</default>
       </uint8_t>
       <array>2</array>
   </simpleType>
@@ -4566,6 +4566,77 @@ bits6:7  will be consumed together to form COARSE_LVL. </description>
 </attribute>
 
 <attribute>
+  <id>PROC_EPS_GB_PERCENTAGE</id>
+  <description>
+     firmware notes:
+        Guardband percentage to apply to baseline epsilon values
+  </description>
+  <simpleType>
+      <uint8_t></uint8_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_EPS_GB_PERCENTAGE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_EPS_GB_DIRECTION</id>
+  <description>
+    firmware notes:
+      Direction to apply guardband margin (positive/negative)
+  </description>
+  <simpleType>
+      <uint8_t></uint8_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_EPS_GB_DIRECTION</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_FABRIC_ASYNC_SAFE_MODE</id>
+  <description>
+    firmware notes:
+      Set to force all asynchronous boundary crossings into safe mode.
+  </description>
+  <simpleType>
+      <uint8_t></uint8_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>FREQ_PCIE</id>
+  <description>
+    The frequency of a processor's PCI-e bus in MHz.
+    This is the same for all PCI-e busses in the system.
+    This is set by the HWP that sets up the PCI-e PLL.
+  </description>
+  <simpleType><uint32_t></uint32_t></simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_FREQ_PCIE</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>NOMINAL_FREQ_MHZ</id>
     <description>Nominal frequency in mhz for all processors in the system based on module VPD processing.</description>
     <simpleType>
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index 2b4eb56ff..6a6cb8395 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -1,25 +1,25 @@
-#   IBM_PROLOG_BEGIN_TAG
-#  This is an automatically generated prolog.
-#
-#  $Source: src/usr/targeting/common/xmltohb/common.mk $
-#
-#  IBM CONFIDENTIAL
-#
-#  COPYRIGHT International Business Machines Corp. 2011-2012
-#
-#  p1
-#
-#  Object Code Only (OCO) source materials
-#  Licensed Internal Code Source Materials
-#  IBM HostBoot Licensed Internal Code
-#
-#  The source code for this program is not published or other-
-#  wise divested of its trade secrets, irrespective of what has
-#  been deposited with the U.S. Copyright Office.
-#
-#  Origin: 30
-#
-#  IBM_PROLOG_END_TAG
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+# 
+# $Source: src/usr/targeting/common/xmltohb/common.mk $
+# 
+# IBM CONFIDENTIAL
+# 
+# COPYRIGHT International Business Machines Corp. 2011,2012
+# 
+# p1
+# 
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+# 
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+# 
+# Origin: 30
+# 
+# IBM_PROLOG_END_TAG 
 ################################################################################
 #
 #  @file targeting/common/xmltohb/common.mk
@@ -69,7 +69,7 @@ FAPI_ATTR_SOURCES =          \
     dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml \
     dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml \
     dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \
-    dram_initialization/proc_setup_bars/proc_fab_smp_fabric_attributes.xml
+    activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml
 
 
 XMLTOHB_GENERIC_XML     = generic.xml
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index e9153e9d9..8263850bb 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -54,7 +54,7 @@
         <id>AFFINITY_PATH</id>
         <default>affinity:sys-0</default>
     </attribute>
-        <attribute>
+    <attribute>
         <id>PROC_EPS_TABLE_TYPE</id>
         <default>2</default>
     </attribute>
@@ -80,7 +80,35 @@
     </attribute>
     <attribute>
         <id>FREQ_CORE_FLOOR</id>
-        <default>2500</default>
+        <default>0x2580</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_PB</id>
+        <default>0x960</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_X</id>
+        <default>0x12C0</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_A</id>
+        <default>0x1900</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_PCIE</id>
+        <default>0x3E8</default>
+    </attribute>
+    <attribute>
+        <id>PROC_EPS_GB_DIRECTION</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_EPS_GB_PERCENTAGE</id>
+        <default>0x14</default>
+    </attribute>
+    <attribute>
+        <id>PROC_FABRIC_ASYNC_SAFE_MODE</id>
+        <default>0</default>
     </attribute>
     <attribute>
         <id>SP_FUNCTIONS</id>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 8e1d253d3..3ce48084a 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -108,6 +108,20 @@
     <attribute><id>MSS_PREFETCH_ENABLE</id></attribute>
     <attribute><id>MSS_CLEANER_ENABLE</id></attribute>
     <attribute><id>MIRROR_BASE_ADDRESS</id></attribute>
+    <attribute><id>PROC_EPS_GB_PERCENTAGE</id></attribute>
+    <attribute><id>PROC_EPS_GB_DIRECTION</id></attribute>
+    <attribute><id>PROC_FABRIC_ASYNC_SAFE_MODE</id></attribute>
+    <attribute><id>FREQ_PCIE</id></attribute>
+    <attribute><id>L2_R_T0_EPS</id></attribute>
+    <attribute><id>L2_R_T1_EPS</id></attribute>
+    <attribute><id>L2_R_T2_EPS</id></attribute>
+    <attribute><id>L2_FORCE_R_T2_EPS</id></attribute>
+    <attribute><id>L2_W_EPS</id></attribute>
+    <attribute><id>L3_R_T0_EPS</id></attribute>
+    <attribute><id>L3_R_T1_EPS</id></attribute>
+    <attribute><id>L3_R_T2_EPS</id></attribute>
+    <attribute><id>L3_FORCE_R_T2_EPS</id></attribute>
+    <attribute><id>L3_W_EPS</id></attribute>
     <attribute><id>NOMINAL_FREQ_MHZ</id></attribute>
     <attribute><id>MNFG_FLAGS</id></attribute>
 </targetType>
@@ -309,36 +323,6 @@
         <id>TYPE</id>
         <default>EX</default>
     </attribute>
-    <attribute>
-        <id>L2_R_T0_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L2_R_T1_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L2_R_T2_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L2_FORCE_R_T2_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L2_W_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L3_R_T0_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L3_R_T1_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L3_R_T2_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L3_FORCE_R_T2_EPS</id>
-    </attribute>
-    <attribute>
-        <id>L3_W_EPS</id>
-    </attribute>
 </targetType>
 
 <targetType>
diff --git a/src/usr/targeting/common/xmltohb/vbu.system.xml b/src/usr/targeting/common/xmltohb/vbu.system.xml
index 1fa43d528..fe926f66b 100644
--- a/src/usr/targeting/common/xmltohb/vbu.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu.system.xml
@@ -63,7 +63,7 @@
     </attribute>
     <attribute>
         <id>ALL_MCS_IN_INTERLEAVING_GROUP</id>
-        <default>0</default>
+        <default>1</default>
     </attribute>
     <attribute>
         <id>FREQ_PROC_REFCLOCK</id>
@@ -75,7 +75,35 @@
     </attribute>
     <attribute>
         <id>FREQ_CORE_FLOOR</id>
-        <default>2500</default>
+        <default>0x2580</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_PB</id>
+        <default>0x960</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_X</id>
+        <default>0x12C0</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_A</id>
+        <default>0x1900</default>
+    </attribute>
+    <attribute>
+        <id>FREQ_PCIE</id>
+        <default>0x3E8</default>
+    </attribute>
+    <attribute>
+        <id>PROC_EPS_GB_DIRECTION</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_EPS_GB_PERCENTAGE</id>
+        <default>0x14</default>
+    </attribute>
+    <attribute>
+        <id>PROC_FABRIC_ASYNC_SAFE_MODE</id>
+        <default>0</default>
     </attribute>
     <attribute>
         <id>SP_FUNCTIONS</id>