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| author | Stephen Glancy <sglancy@us.ibm.com> | 2019-05-07 15:57:33 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-13 10:54:30 -0500 |
| commit | b952df368d4204b91f6374036051cfd99f1834d6 (patch) | |
| tree | f3e15084a0cd5299de4d891115ee2f744d8d35b8 /src | |
| parent | 2b3c06d520853a436ac78050482168752dcd6efd (diff) | |
| download | talos-hostboot-b952df368d4204b91f6374036051cfd99f1834d6.tar.gz talos-hostboot-b952df368d4204b91f6374036051cfd99f1834d6.zip | |
Moves CCS lab code to generic
Change-Id: I7cc293bcca34612db4761b50d701d52a56d2cfd3
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77139
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77214
Reviewed-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
3 files changed, 12 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H index e469fee45..382fa63fd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H @@ -119,7 +119,7 @@ class ccsTraits<mss::mc_type::NIMBUS> NTTM_RW_DATA_DLY = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY, NTTM_RW_DATA_DLY_LEN = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN, IDLE_PAT_BANK_2 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2, - DR_PARITY_ENABLE = MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, + DDR_PARITY_ENABLE = MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, IDLE_PAT_PARITY = MCBIST_CCS_MODEQ_IDLE_PAT_PARITY, // MCB_CNTRL @@ -265,6 +265,9 @@ class ccsTraits<mss::mc_type::NIMBUS> { return fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target); } + + // Lab values + static constexpr uint64_t LAB_MRS_CMD = 0x000008F000000000; }; #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index d89bf89b0..aeddf0277 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -251,9 +251,9 @@ class portTraits<mss::mc_type::NIMBUS> RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, + RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION, RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN, - RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, DSM0Q_WRDONE_DLY = MCA_MBA_DSM0Q_CFG_WRDONE_DLY, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H index e1cf84dfd..f9046be7a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H @@ -127,6 +127,13 @@ class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST> // All of the pattern registers are calculated off of this base static constexpr uint64_t PATTERN0_REG = MCBIST_MCBFD0Q; + static constexpr uint64_t PATTERN1_REG = MCBIST_MCBFD1Q; + static constexpr uint64_t PATTERN2_REG = MCBIST_MCBFD2Q; + static constexpr uint64_t PATTERN3_REG = MCBIST_MCBFD3Q; + static constexpr uint64_t PATTERN4_REG = MCBIST_MCBFD4Q; + static constexpr uint64_t PATTERN5_REG = MCBIST_MCBFD5Q; + static constexpr uint64_t PATTERN6_REG = MCBIST_MCBFD6Q; + static constexpr uint64_t PATTERN7_REG = MCBIST_MCBFD7Q; static constexpr uint64_t DATA_ROTATE_CNFG_REG = MCBIST_MCBDRCRQ; static constexpr uint64_t DATA_ROTATE_SEED_REG = MCBIST_MCBDRSRQ; |
