diff options
| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-12-23 02:02:51 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-24 09:32:46 -0400 |
| commit | b4f215e8febd8026d801335e08ff1b353f8eb447 (patch) | |
| tree | d10630cfb91d201f9c3f45f4bfeafcee48f6edfa /src | |
| parent | a95e5d02b73a4bbfced8bed7751a6800f5e962ad (diff) | |
| download | talos-hostboot-b4f215e8febd8026d801335e08ff1b353f8eb447.tar.gz talos-hostboot-b4f215e8febd8026d801335e08ff1b353f8eb447.zip | |
PM: Updated QPMR and SGPE Header with 24x7 offset and length.
Change-Id: Idfcca3888ad1446a9e5130538e8270adc44e2631
RTC:164313
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34192
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34599
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
9 files changed, 2974 insertions, 2828 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 7a550a6d0..f03d380fc 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -157,8 +157,8 @@ HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_OFFSET_BYTE, 0x40) HCD_CONST(QPMR_QUAD_SPECIFIC_RINGS_LENGTH_BYTE, 0x44) HCD_CONST(QPMR_QUAD_SCOM_RESTORE_OFFSET_BYTE, 0x48) HCD_CONST(QPMR_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x4C) -HCD_CONST(QPMR_24x7_DATA_OFFSET_BYTE, 0x50) -HCD_CONST(QPMR_24x7_DATA_LENGTH_BYTE, 0x54) +HCD_CONST(QPMR_AUX_DATA_OFFSET_BYTE, 0x50) +HCD_CONST(QPMR_AUX_DATA_LENGTH_BYTE, 0x54) HCD_CONST(QPMR_STOP_FFDC_OFFSET_BYTE, 0x58) HCD_CONST(QPMR_STOP_FFDC_LENGTH_BYTE, 0x5C) @@ -202,9 +202,9 @@ HCD_CONST(SGPE_QUAD_SPECIFIC_RING_SRAM_OFF_BYTE, 0x30) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_SRAM_OFF_BYTE, 0x34) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_MEM_OFF_BYTE, 0x38) HCD_CONST(SGPE_QUAD_SCOM_RESTORE_LENGTH_BYTE, 0x3C) -HCD_CONST(SGPE_24x7_DATA_OFFSET_BYTE, 0x40) -HCD_CONST(SGPE_24x7_DATA_LENGTH_BYTE, 0x44) -HCD_CONST(PGPE_24x7_CTRL_BYTE, 0x48) +HCD_CONST(SGPE_AUX_DATA_OFFSET_BYTE, 0x40) +HCD_CONST(SGPE_AUX_DATA_LENGTH_BYTE, 0x44) +HCD_CONST(PGPE_AUX_CTRL_BYTE, 0x48) HCD_CONST(SGPE_RESET_ADDR_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_SYSTEM_RESET_ADDR_BYTE)) HCD_CONST(SGPE_BUILD_DATE_IMAGE_OFFSET, (SGPE_HEADER_IMAGE_OFFSET + SGPE_BUILD_DATE_BYTE)) @@ -217,6 +217,9 @@ HCD_CONST(SGPE_STOP_11_TO_8_BIT_POS, 0x10000000) HCD_CONST(SGPE_CME_INSTRUCTION_TRACE_BIT_POS, 0x08000000) HCD_CONST(SGPE_PROC_FAB_ADDR_BAR_MODE_POS, 0x00008000) +///24x7 +HCD_CONST(QPMR_AUX_OFFSET, (512 * ONE_KB)) +HCD_CONST(QPMR_AUX_LENGTH, (64 * ONE_KB)) /// SGPE Hcode HCD_CONST(SGPE_HCODE_IMAGE_OFFSET, (SGPE_INT_VECTOR_SIZE + SGPE_HEADER_SIZE)) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H index 2e59b3620..adf1b73ed 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_homer.H @@ -59,6 +59,7 @@ HCD_CONST(HOMER_SGPE_BOOT_LOADER_LENGTH_ADDR, (HOMER_QPMR_HEADER_ADDR + QPMR_BOOT_LOADER_LENGTH_BYTE)) HCD_CONST(HOMER_SGPE_BOOT_COPIER_ADDR, (HOMER_QPMR_HEADER_ADDR + QPMR_HEADER_SIZE)) +HCD_CONST(HOMER_AUX_BASE_ADDR, (HOMER_QPMR_BASE_ADDR + QPMR_AUX_OFFSET)) /// CPMR diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index fc6980d51..6df1dbf5e 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -90,8 +90,8 @@ HCD_HDR_UINT32( quadSpecRingOffset, 0); HCD_HDR_UINT32( quadSpecRingLength, 0); HCD_HDR_UINT32( quadScomOffset, 0); HCD_HDR_UINT32( quadScomLength, 0); -HCD_HDR_UINT32( quad24x7Offset, 0); -HCD_HDR_UINT32( quad24x7Length, 0); +HCD_HDR_UINT32( quadAuxOffset, 0); +HCD_HDR_UINT32( quadAuxLength, 0); HCD_HDR_UINT32( stopFfdcOffset, 0); HCD_HDR_UINT32( stopFfdcLength, 0); HCD_HDR_PAD(512); @@ -229,8 +229,10 @@ HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_mem_offset, 0); HCD_HDR_UINT32(g_sgpe_scom_mem_length, 0); -HCD_HDR_UINT32(g_sgpe_24x7_offset, 0); -HCD_HDR_UINT32(g_sgpe_24x7_length, 0); +HCD_HDR_UINT32(g_sgpe_aux_offset, 0); +HCD_HDR_UINT32(g_sgpe_aux_length, 0); +HCD_HDR_UINT32(g_sgpe_aux_control, 0); +HCD_HDR_UINT32(g_sgpe_reserve4, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index fe5848944..16f40325c 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -66,8 +66,8 @@ typedef union occ_flags uint32_t sgpe_StopExitsIgnored : 1; uint32_t sgpe_StopEntryIgnored : 1; uint32_t reserved2 : 1; - uint32_t sgpe_24x7_Activate : 1; - uint32_t sgpe_24x7_Active : 1; + uint32_t sgpe_Aux_Activate : 1; + uint32_t sgpe_Aux_Active : 1; uint32_t pib_I2CMasterEngine1Lock : 2; uint32_t pib_I2CMasterEngine2Lock : 2; uint32_t pib_I2CMasterEngine3Lock : 2; @@ -81,8 +81,8 @@ typedef union occ_flags uint32_t pib_I2CMasterEngine3Lock : 2; uint32_t pib_I2CMasterEngine2Lock : 2; uint32_t pib_I2CMasterEngine1Lock : 2; - uint32_t sgpe_24x7_Active : 1; - uint32_t sgpe_24x7_Activate : 1; + uint32_t sgpe_Aux_Active : 1; + uint32_t sgpe_Aux_Activate : 1; uint32_t reserved2 : 1; uint32_t sgpe_StopEntryIgnored : 1; uint32_t sgpe_StopExitsIgnored : 1; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 315070d65..6c0898631 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -60,11 +60,11 @@ using namespace stopImageSection; extern "C" { - /** - * @brief aligns DATA_SIZE to 8B. - * @param TEMP_LEN temp storage - * @param DATA_SIZE size to be aligned. Aligned size is saved in same variable. - */ +/** + * @brief aligns DATA_SIZE to 8B. + * @param TEMP_LEN temp storage + * @param DATA_SIZE size to be aligned. Aligned size is saved in same variable. + */ #define ALIGN_DWORD(TEMP_LEN, DATA_SIZE) \ {TEMP_LEN = (DATA_SIZE % RING_ALIGN_BOUNDARY); \ if( TEMP_LEN ) \ @@ -73,11 +73,11 @@ extern "C" } \ } - /** - * @brief aligns start of scan ring to 8B boundary. - * @param RING_REGION_BASE start location of scan ring region in HOMER. - * @param RING_LOC start of scan ring. - */ +/** + * @brief aligns start of scan ring to 8B boundary. + * @param RING_REGION_BASE start location of scan ring region in HOMER. + * @param RING_LOC start of scan ring. + */ #define ALIGN_RING_LOC(RING_REGION_BASE, RING_LOC) \ { \ uint8_t tempDiff = \ @@ -88,9 +88,9 @@ extern "C" } \ } - /** - * @brief round of ring size to multiple of 32B - */ +/** + * @brief round of ring size to multiple of 32B + */ #define ROUND_OFF_32B( ROUND_SIZE) \ { \ uint32_t tempSize = ROUND_SIZE; \ @@ -99,290 +99,291 @@ extern "C" ROUND_SIZE = (( ( tempSize + 31 )/32 ) * 32 ); \ } \ } - namespace p9_hcodeImageBuild - { +namespace p9_hcodeImageBuild +{ - /** - * @brief some misc local constants - */ - enum +/** + * @brief some misc local constants + */ +enum +{ + ENABLE_ALL_CORE = 0x000FFFF, + RISK_LEVEL = 0x01, + QUAD_COMMON_RING_INDEX_SIZE = sizeof(QuadCmnRingsList_t), + QUAD_SPEC_RING_INDEX_SIZE = ((sizeof(QuadSpecRingsList_t)) / sizeof(uint16_t)), + QUAD_SPEC_RING_INDEX_LEN = (QUAD_SPEC_RING_INDEX_SIZE * 2 * MAX_QUADS_PER_CHIP), + CORE_COMMON_RING_INDEX_SIZE = sizeof(CoreCmnRingsList_t), + CORE_SPEC_RING_INDEX_SIZE = sizeof(CoreSpecRingList_t), + RING_START_TO_RS4_OFFSET = 8, + TOR_VER_ONE = 1, + TOR_VER_TWO = 2, + QUAD_BIT_POS = 24, + ODD_EVEN_EX_POS = 0x00000400, + SECTN_NAME_MAX_LEN = 20, + SGPE_AUX_FUNC_INERVAL_SHIFT = 24, + CME_SRAM_IMAGE = P9_XIP_SECTIONS + 1, + SGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 2, + PGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 3, +}; + +/** + * @brief struct used to manipulate scan ring in HOMER. + */ +struct RingBufData +{ + void* iv_pRingBuffer; + uint32_t iv_ringBufSize; + void* iv_pWorkBuf1; + uint32_t iv_sizeWorkBuf1; + void* iv_pWorkBuf2; + uint32_t iv_sizeWorkBuf2; + + RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize, + void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1, + void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) : + iv_pRingBuffer( i_pRingBuf1), + iv_ringBufSize(i_ringSize), + iv_pWorkBuf1( i_pWorkBuf1 ), + iv_sizeWorkBuf1( i_sizeWorkBuf1 ), + iv_pWorkBuf2( i_pWorkBuf2 ), + iv_sizeWorkBuf2( i_sizeWorkBuf2 ) + + {} + + RingBufData(): + iv_pRingBuffer( NULL ), + iv_ringBufSize( 0 ), + iv_pWorkBuf1( NULL ), + iv_sizeWorkBuf1( 0 ), + iv_pWorkBuf2( NULL ), + iv_sizeWorkBuf2( 0 ) + { } +}; + +/** + * @brief models a section in HOMER. + */ +struct ImgSec +{ + PlatId iv_plat; + uint8_t iv_secId; + char iv_secName[SECTN_NAME_MAX_LEN]; + ImgSec( PlatId i_plat, uint8_t i_secId, char* i_secName ): + iv_plat( i_plat ), + iv_secId( i_secId ) { - ENABLE_ALL_CORE = 0x000FFFF, - RISK_LEVEL = 0x01, - QUAD_COMMON_RING_INDEX_SIZE = sizeof(QuadCmnRingsList_t), - QUAD_SPEC_RING_INDEX_SIZE = ((sizeof(QuadSpecRingsList_t)) / sizeof(uint16_t)), - QUAD_SPEC_RING_INDEX_LEN = (QUAD_SPEC_RING_INDEX_SIZE * 2 * MAX_QUADS_PER_CHIP), - CORE_COMMON_RING_INDEX_SIZE = sizeof(CoreCmnRingsList_t), - CORE_SPEC_RING_INDEX_SIZE = sizeof(CoreSpecRingList_t), - RING_START_TO_RS4_OFFSET = 8, - TOR_VER_ONE = 1, - TOR_VER_TWO = 2, - QUAD_BIT_POS = 24, - ODD_EVEN_EX_POS = 0x00000400, - SECTN_NAME_MAX_LEN = 20, - CME_SRAM_IMAGE = P9_XIP_SECTIONS + 1, - SGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 2, - PGPE_SRAM_IMAGE = P9_XIP_SECTIONS + 3, - }; + memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN ); + uint8_t secLength = strlen(i_secName); + secLength = ( secLength > SECTN_NAME_MAX_LEN ) ? SECTN_NAME_MAX_LEN : secLength; + memcpy( iv_secName, i_secName, secLength ); + } - /** - * @brief struct used to manipulate scan ring in HOMER. - */ - struct RingBufData + ImgSec( PlatId i_plat, uint8_t i_secId ): + iv_plat( i_plat ), + iv_secId( i_secId ) { - void* iv_pRingBuffer; - uint32_t iv_ringBufSize; - void* iv_pWorkBuf1; - uint32_t iv_sizeWorkBuf1; - void* iv_pWorkBuf2; - uint32_t iv_sizeWorkBuf2; - - RingBufData( void* i_pRingBuf1, const uint32_t i_ringSize, - void* i_pWorkBuf1, const uint32_t i_sizeWorkBuf1, - void* i_pWorkBuf2, const uint32_t i_sizeWorkBuf2 ) : - iv_pRingBuffer( i_pRingBuf1), - iv_ringBufSize(i_ringSize), - iv_pWorkBuf1( i_pWorkBuf1 ), - iv_sizeWorkBuf1( i_sizeWorkBuf1 ), - iv_pWorkBuf2( i_pWorkBuf2 ), - iv_sizeWorkBuf2( i_sizeWorkBuf2 ) - - {} - - RingBufData(): - iv_pRingBuffer( NULL ), - iv_ringBufSize( 0 ), - iv_pWorkBuf1( NULL ), - iv_sizeWorkBuf1( 0 ), - iv_pWorkBuf2( NULL ), - iv_sizeWorkBuf2( 0 ) - { } - }; + memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN ); + } - /** - * @brief models a section in HOMER. - */ - struct ImgSec + ImgSec(): iv_plat (PLAT_SELF), iv_secId (0 ) { - PlatId iv_plat; - uint8_t iv_secId; - char iv_secName[SECTN_NAME_MAX_LEN]; - ImgSec( PlatId i_plat, uint8_t i_secId, char* i_secName ): - iv_plat( i_plat ), - iv_secId( i_secId ) - { - memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN ); - uint8_t secLength = strlen(i_secName); - secLength = ( secLength > SECTN_NAME_MAX_LEN ) ? SECTN_NAME_MAX_LEN : secLength; - memcpy( iv_secName, i_secName, secLength ); - } - - ImgSec( PlatId i_plat, uint8_t i_secId ): - iv_plat( i_plat ), - iv_secId( i_secId ) - { - memset( iv_secName, 0x00, SECTN_NAME_MAX_LEN ); - } - - ImgSec(): iv_plat (PLAT_SELF), iv_secId (0 ) - { - memcpy( iv_secName, "Self Restore", 12 ); - } - }; + memcpy( iv_secName, "Self Restore", 12 ); + } +}; - /** - * @brief operator < overloading for ImgSec. - */ - bool operator < ( const ImgSec& i_lhs, const ImgSec& i_rhs ) +/** + * @brief operator < overloading for ImgSec. + */ +bool operator < ( const ImgSec& i_lhs, const ImgSec& i_rhs ) +{ + if( i_lhs.iv_plat == i_rhs.iv_plat ) { - if( i_lhs.iv_plat == i_rhs.iv_plat ) - { - return i_lhs.iv_secId < i_rhs.iv_secId; - } - else - { - return i_lhs.iv_plat < i_rhs.iv_plat; - } + return i_lhs.iv_secId < i_rhs.iv_secId; } - - /** - * @brief operator == overloading for ImgSec. - */ - bool operator == ( const ImgSec& i_lhs, const ImgSec& i_rhs ) + else { - bool equal = false; + return i_lhs.iv_plat < i_rhs.iv_plat; + } +} - if( i_lhs.iv_plat == i_rhs.iv_plat ) +/** + * @brief operator == overloading for ImgSec. + */ +bool operator == ( const ImgSec& i_lhs, const ImgSec& i_rhs ) +{ + bool equal = false; + + if( i_lhs.iv_plat == i_rhs.iv_plat ) + { + if( i_lhs.iv_secId == i_rhs.iv_secId ) { - if( i_lhs.iv_secId == i_rhs.iv_secId ) - { - equal = true; - } + equal = true; } - - return equal; } - /** - * @brief compares size of a given image's section with maximum allowed size. - */ - class ImgSizeBank - { - public: - ImgSizeBank(); - ~ImgSizeBank() {}; - uint32_t isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size, - char* i_secName, uint8_t i_bufLength ); - uint32_t getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize, - char* i_secName, uint8_t i_bufLength ); - - private: - std::map< ImgSec, uint32_t> iv_secSize; + return equal; +} - }; - - /** - * @brief constructor - */ - ImgSizeBank::ImgSizeBank() - { - //A given section can be uniquely identified by platform to which it belongs, section id - //within the platform image. Name too has been added to assist debug in case of a failure. - //To identify a given image section say a bootloader, we are using it's id as defined in - //p9_xip_images.h. Inorder to identify a full SRAM Image, we introduced a new ID - //xxx_SRAM_IMAGE. - - iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF, (char*)"Self Restore")] = SELF_RESTORE_CODE_SIZE; - iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR, (char*)"CPMR Header")] = CPMR_HEADER_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR, (char*)"QPMR Header")] = HALF_KB; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL, (char*)"SGPE Boot Copier")] = SGPE_BOOT_COPIER_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL, (char*)"SGPE Boot Loader")] = SGPE_BOOT_LOADER_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, (char*)"SGPE Hcode")] = SGPE_IMAGE_SIZE; - iv_secSize[ImgSec(PLAT_SGPE, SGPE_SRAM_IMAGE, (char*)"SGPE SRAM Image")] = SGPE_IMAGE_SIZE; - - iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE, (char*)"CME Hcode")] = CME_SRAM_SIZE; - iv_secSize[ImgSec(PLAT_CME, CME_SRAM_IMAGE, (char*)"CME SRAM Image")] = CME_SRAM_SIZE; - - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR, (char*)"PPMR Header")] = HALF_KB; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL, (char*)"PGPE Boot Copier")] = PGPE_BOOT_COPIER_SIZE; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL, (char*)"PGPE Boot Loader")] = PGPE_BOOT_LOADER_SIZE;; - iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_IMAGE_SIZE; - iv_secSize[ImgSec(PLAT_PGPE, PGPE_SRAM_IMAGE, (char*)"PGPE SRAM Image")] = PGPE_IMAGE_SIZE; - } +/** + * @brief compares size of a given image's section with maximum allowed size. + */ +class ImgSizeBank +{ + public: + ImgSizeBank(); + ~ImgSizeBank() {}; + uint32_t isSizeGood( PlatId i_plat, uint8_t i_sec, uint32_t i_size, + char* i_secName, uint8_t i_bufLength ); + uint32_t getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize, + char* i_secName, uint8_t i_bufLength ); + + private: + std::map< ImgSec, uint32_t> iv_secSize; + +}; + +/** + * @brief constructor + */ +ImgSizeBank::ImgSizeBank() +{ + //A given section can be uniquely identified by platform to which it belongs, section id + //within the platform image. Name too has been added to assist debug in case of a failure. + //To identify a given image section say a bootloader, we are using it's id as defined in + //p9_xip_images.h. Inorder to identify a full SRAM Image, we introduced a new ID + //xxx_SRAM_IMAGE. + + iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_SELF, (char*)"Self Restore")] = SELF_RESTORE_CODE_SIZE; + iv_secSize[ImgSec(PLAT_SELF, P9_XIP_SECTION_RESTORE_CPMR, (char*)"CPMR Header")] = CPMR_HEADER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_QPMR, (char*)"QPMR Header")] = HALF_KB; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL1_BL, (char*)"SGPE Boot Copier")] = SGPE_BOOT_COPIER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_LVL2_BL, (char*)"SGPE Boot Loader")] = SGPE_BOOT_LOADER_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, P9_XIP_SECTION_SGPE_HCODE, (char*)"SGPE Hcode")] = SGPE_IMAGE_SIZE; + iv_secSize[ImgSec(PLAT_SGPE, SGPE_SRAM_IMAGE, (char*)"SGPE SRAM Image")] = SGPE_IMAGE_SIZE; + + iv_secSize[ImgSec(PLAT_CME, P9_XIP_SECTION_CME_HCODE, (char*)"CME Hcode")] = CME_SRAM_SIZE; + iv_secSize[ImgSec(PLAT_CME, CME_SRAM_IMAGE, (char*)"CME SRAM Image")] = CME_SRAM_SIZE; + + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_PPMR, (char*)"PPMR Header")] = HALF_KB; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL1_BL, (char*)"PGPE Boot Copier")] = PGPE_BOOT_COPIER_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_LVL2_BL, (char*)"PGPE Boot Loader")] = PGPE_BOOT_LOADER_SIZE;; + iv_secSize[ImgSec(PLAT_PGPE, P9_XIP_SECTION_PGPE_HCODE, (char*)"PGPE Hcode")] = PGPE_IMAGE_SIZE; + iv_secSize[ImgSec(PLAT_PGPE, PGPE_SRAM_IMAGE, (char*)"PGPE SRAM Image")] = PGPE_IMAGE_SIZE; +} + +/** + * @brief verifies actual section size against max size allowed. + * @param i_plat platform associated with image section. + * @param i_sec image section. + * @param i_size actual image section size. + * @param i_pSecName points to a buffer with section name. + * @param i_bufLength length of the buffer. + * @return zero if size within limit else max size allowed. + */ +uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec, + uint32_t i_size, char* i_pSecName, + uint8_t i_bufLength ) +{ + uint32_t rc = 0; + uint32_t tempSize = 0; + ImgSec key( i_plat, i_sec ); + std::map< ImgSec, uint32_t>::iterator it; - /** - * @brief verifies actual section size against max size allowed. - * @param i_plat platform associated with image section. - * @param i_sec image section. - * @param i_size actual image section size. - * @param i_pSecName points to a buffer with section name. - * @param i_bufLength length of the buffer. - * @return zero if size within limit else max size allowed. - */ - uint32_t ImgSizeBank::isSizeGood( PlatId i_plat, uint8_t i_sec, - uint32_t i_size, char* i_pSecName, - uint8_t i_bufLength ) + do { - uint32_t rc = 0; - uint32_t tempSize = 0; - ImgSec key( i_plat, i_sec ); - std::map< ImgSec, uint32_t>::iterator it; + rc = getImgSectn( i_plat, i_sec, tempSize, i_pSecName, i_bufLength ); + FAPI_DBG(" Sec: %s Max Size 0x%08X", i_pSecName ? i_pSecName : "--", tempSize ); - do + if( rc ) { - rc = getImgSectn( i_plat, i_sec, tempSize, i_pSecName, i_bufLength ); - FAPI_DBG(" Sec: %s Max Size 0x%08X", i_pSecName ? i_pSecName : "--", tempSize ); - - if( rc ) - { - FAPI_ERR( "Image Sectn not found i_plat 0x%08x i_sec 0x%08x", - (uint32_t) i_plat, i_sec ); - break; - } - - if( i_size > tempSize ) - { - rc = tempSize; // returning Max Allowed size as return code - break; - } + FAPI_ERR( "Image Sectn not found i_plat 0x%08x i_sec 0x%08x", + (uint32_t) i_plat, i_sec ); + break; + } + if( i_size > tempSize ) + { + rc = tempSize; // returning Max Allowed size as return code + break; } - while(0); - return rc; } - /** - * @brief returns max size for a given image section - * @param i_plat platform associated with image section. - * @param i_sec image section. - * @param i_size actual image section size. - * @param i_pSecName points to a buffer with section name. - * @param i_bufLength length of the buffer. - * @return zero if section found, error code otherwise. - */ - uint32_t ImgSizeBank::getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize, - char* i_pSecName, uint8_t i_bufLength ) - { - uint32_t rc = -1; - ImgSec key( i_plat, i_sec ); - std::map< ImgSec, uint32_t>::iterator it; - o_secSize = 0; + while(0); + + return rc; +} +/** + * @brief returns max size for a given image section + * @param i_plat platform associated with image section. + * @param i_sec image section. + * @param i_size actual image section size. + * @param i_pSecName points to a buffer with section name. + * @param i_bufLength length of the buffer. + * @return zero if section found, error code otherwise. + */ +uint32_t ImgSizeBank::getImgSectn( PlatId i_plat, uint8_t i_sec, uint32_t& o_secSize, + char* i_pSecName, uint8_t i_bufLength ) +{ + uint32_t rc = -1; + ImgSec key( i_plat, i_sec ); + std::map< ImgSec, uint32_t>::iterator it; + o_secSize = 0; - for( it = iv_secSize.begin(); it != iv_secSize.end(); it++ ) + for( it = iv_secSize.begin(); it != iv_secSize.end(); it++ ) + { + if( key == it->first ) { - if( key == it->first ) - { - rc = 0; - o_secSize = it->second; //Max Size allowed for section - - //Image section found and maximum size info obtained. - if( i_pSecName ) - { - //Copying Sectn name to assist debug - memcpy( i_pSecName, it->first.iv_secName, i_bufLength ); - } + rc = 0; + o_secSize = it->second; //Max Size allowed for section - break; + //Image section found and maximum size info obtained. + if( i_pSecName ) + { + //Copying Sectn name to assist debug + memcpy( i_pSecName, it->first.iv_secName, i_bufLength ); } + break; } - return rc; } + return rc; +} + +/** + * @brief models an Ex pair. + */ +struct ExpairId +{ + uint16_t iv_evenExId; + uint16_t iv_oddExId; /** - * @brief models an Ex pair. + * @brief constructor */ - struct ExpairId - { - uint16_t iv_evenExId; - uint16_t iv_oddExId; - /** - * @brief constructor - */ - ExpairId( uint32_t i_evenExId, uint32_t i_oddExId ): - iv_evenExId( i_evenExId ), - iv_oddExId( i_oddExId ) - { } - - /** - * @brief constructor - */ - ExpairId() { }; - }; + ExpairId( uint32_t i_evenExId, uint32_t i_oddExId ): + iv_evenExId( i_evenExId ), + iv_oddExId( i_oddExId ) + { } /** - * @brief a map to resolve Ex chiplet Id associated with all six quads in P9. + * @brief constructor */ - class ExIdMap - { - public: - ExIdMap(); - ~ExIdMap() {}; - uint32_t getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ); - private: - std::map<uint32_t, ExpairId> iv_idMap; - }; + ExpairId() { }; +}; + +/** + * @brief a map to resolve Ex chiplet Id associated with all six quads in P9. + */ +class ExIdMap +{ + public: + ExIdMap(); + ~ExIdMap() {}; + uint32_t getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ); + private: + std::map<uint32_t, ExpairId> iv_idMap; +}; #define ALIGN_DBWORD( OUTSIZE, INSIZE ) \ { \ @@ -393,2098 +394,2203 @@ extern "C" } \ } - /** - * @brief constructor - */ - ExIdMap::ExIdMap() - { - ExpairId exPairIdMap[6] = { { 0x10, 0x11}, - { 0x12, 0x13 }, - { 0x14, 0x15 }, - { 0x16, 0x17 }, - { 0x18, 0x19 }, - { 0x1A, 0x1B } - }; +/** + * @brief constructor + */ +ExIdMap::ExIdMap() +{ + ExpairId exPairIdMap[6] = { { 0x10, 0x11}, + { 0x12, 0x13 }, + { 0x14, 0x15 }, + { 0x16, 0x17 }, + { 0x18, 0x19 }, + { 0x1A, 0x1B } + }; - for( uint32_t eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) - { - iv_idMap[CACHE0_CHIPLET_ID + eqCnt] = exPairIdMap[eqCnt]; - } + for( uint32_t eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + iv_idMap[CACHE0_CHIPLET_ID + eqCnt] = exPairIdMap[eqCnt]; } +} //------------------------------------------------------------------------- - /** - * @brief returns ex chiplet ID associated with a scan ring and EQ id. - * @param i_eqId chiplet id for a given quad. - * @param i_ringOrder serial number associated with a scan ring in HOMER. - * @return chiplet Id associated with a scan ring. - */ - uint32_t ExIdMap::getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ) - { - uint32_t exChipletId = 0xFFFFFFFF; - std::map<uint32_t, ExpairId>::iterator itChipId = iv_idMap.find( i_eqId ); +/** + * @brief returns ex chiplet ID associated with a scan ring and EQ id. + * @param i_eqId chiplet id for a given quad. + * @param i_ringOrder serial number associated with a scan ring in HOMER. + * @return chiplet Id associated with a scan ring. + */ +uint32_t ExIdMap::getInstanceId( uint32_t i_eqId, uint32_t i_ringOrder ) +{ + uint32_t exChipletId = 0xFFFFFFFF; + std::map<uint32_t, ExpairId>::iterator itChipId = iv_idMap.find( i_eqId ); - do + do + { + if ( itChipId == iv_idMap.end() ) { - if ( itChipId == iv_idMap.end() ) - { - break; - } - else + break; + } + else + { + switch( i_ringOrder ) { - switch( i_ringOrder ) - { - case 0: - exChipletId = i_eqId; - break; - - case 1: - case 3: - case 5: - case 7: - exChipletId = itChipId->second.iv_evenExId; - break; - - case 2: - case 4: - case 6: - case 8: - exChipletId = itChipId->second.iv_oddExId; - break; - - default: - break; - } - } + case 0: + exChipletId = i_eqId; + break; + + case 1: + case 3: + case 5: + case 7: + exChipletId = itChipId->second.iv_evenExId; + break; + case 2: + case 4: + case 6: + case 8: + exChipletId = itChipId->second.iv_oddExId; + break; + + default: + break; + } } - while(0); - FAPI_DBG("Resolved Ex Id 0x%02x", exChipletId ); - return exChipletId; } + while(0); + + FAPI_DBG("Resolved Ex Id 0x%02x", exChipletId ); + return exChipletId; +} //------------------------------------------------------------------------- - fapi2::ReturnCode validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize ) - { - FAPI_DBG(">validateSramImageSize" ); - uint32_t rc = IMG_BUILD_SUCCESS; +fapi2::ReturnCode validateSramImageSize( Homerlayout_t* i_pChipHomer, uint32_t& o_sramImgSize ) +{ + FAPI_DBG(">validateSramImageSize" ); + uint32_t rc = IMG_BUILD_SUCCESS; - ImgSizeBank sizebank; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; + ImgSizeBank sizebank; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; - //FIXME size will change once SCOM and 24x7 are handled - o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset); + o_sramImgSize = SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset); - rc = sizebank.isSizeGood( PLAT_SGPE, SGPE_SRAM_IMAGE, o_sramImgSize, NULL , 0 ); - FAPI_IMP("SGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + rc = sizebank.isSizeGood( PLAT_SGPE, SGPE_SRAM_IMAGE, o_sramImgSize, NULL , 0 ); + FAPI_IMP("SGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::SGPE_IMG_EXCEED_SRAM_SIZE( ) - .set_BAD_IMG_SIZE( o_sramImgSize ) - .set_MAX_SGPE_IMG_SIZE_ALLOWED( rc ), - "SGPE Image Size Exceeded Max Allowed Size" ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::SGPE_IMG_EXCEED_SRAM_SIZE( ) + .set_BAD_IMG_SIZE( o_sramImgSize ) + .set_MAX_SGPE_IMG_SIZE_ALLOWED( rc ), + "SGPE Image Size Exceeded Max Allowed Size" ); - o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length); + o_sramImgSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset) << CME_BLK_SIZE_SHIFT) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length); - FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize ); + FAPI_DBG("CME Offset 0x%08X size 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset), o_sramImgSize ); - rc = sizebank.isSizeGood( PLAT_CME, CME_SRAM_IMAGE, o_sramImgSize, NULL, 0 ); - FAPI_IMP("CME SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + rc = sizebank.isSizeGood( PLAT_CME, CME_SRAM_IMAGE, o_sramImgSize, NULL, 0 ); + FAPI_IMP("CME SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::CME_IMG_EXCEED_SRAM_SIZE( ) - .set_BAD_IMG_SIZE( o_sramImgSize ) - .set_MAX_CME_IMG_SIZE_ALLOWED( rc ), - "CME Image Size Exceeded Max Allowed Size" ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::CME_IMG_EXCEED_SRAM_SIZE( ) + .set_BAD_IMG_SIZE( o_sramImgSize ) + .set_MAX_CME_IMG_SIZE_ALLOWED( rc ), + "CME Image Size Exceeded Max Allowed Size" ); - o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size); + o_sramImgSize = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size); - rc = sizebank.isSizeGood( PLAT_PGPE, PGPE_SRAM_IMAGE, o_sramImgSize, NULL, 0 ); - FAPI_IMP("PGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); + rc = sizebank.isSizeGood( PLAT_PGPE, PGPE_SRAM_IMAGE, o_sramImgSize, NULL, 0 ); + FAPI_IMP("PGPE SRAM Image Size : 0x%08X Size Check : %s", o_sramImgSize, rc ? "FAILURE" : "SUCCESS" ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::PGPE_IMG_EXCEED_SRAM_SIZE( ) - .set_BAD_IMG_SIZE( o_sramImgSize ) - .set_MAX_PGPE_IMG_SIZE_ALLOWED( rc ), - "PGPE Image Size Exceeded Max Allowed Size" ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::PGPE_IMG_EXCEED_SRAM_SIZE( ) + .set_BAD_IMG_SIZE( o_sramImgSize ) + .set_MAX_PGPE_IMG_SIZE_ALLOWED( rc ), + "PGPE Image Size Exceeded Max Allowed Size" ); - FAPI_DBG("<validateSramImageSize" ); + FAPI_DBG("<validateSramImageSize" ); - fapi_try_exit: - return fapi2::current_err; - } +fapi_try_exit: + return fapi2::current_err; +} //------------------------------------------------------------------------- - /** - * @brief validates arguments passed for hcode image build - * @param refer to p9_hcode_image_build arguments - * @return fapi2 return code - */ - fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut, - SysPhase_t i_phase, ImageType_t i_imgType, - void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2, - uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 ) - { - uint32_t l_rc = IMG_BUILD_SUCCESS; - uint32_t hwImagSize = 0; - - FAPI_DBG("Entering validateInputArguments ..."); - - FAPI_ASSERT( (( i_pImageIn != NULL ) && ( i_pImageOut != NULL ) && - ( i_pImageIn != i_pImageOut )), - fapi2::IMG_PTR_ERROR() - .set_HW_IMG_BUF_PTR( i_pImageIn ) - .set_HOMER_IMG_BUF_PTR( i_pImageOut ), - "Bad pointer to HW Image or HOMER Image" ); - l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize ); - - FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X", - hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize ); - - FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) && - ( HARDWARE_IMG_SIZE >= hwImagSize )), - fapi2::HW_IMAGE_INVALID_SIZE() - .set_HW_IMG_SIZE( hwImagSize ) - .set_MAX_HW_IMG_SIZE( HARDWARE_IMG_SIZE ), - "Hardware image size found out of range" ); - FAPI_ASSERT( (( i_phase > PHASE_NA ) && ( i_phase < PHASE_END )), - fapi2::HCODE_INVALID_PHASE() - .set_SYS_PHASE( i_phase ), - "Invalid value passed as build phase" ); - - FAPI_ASSERT( ( i_pBuf1 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf1 ), - "Invalid temp buffer1 passed for hcode image build" ); - - FAPI_ASSERT( (( i_bufSize1 != 0 ) && ( i_bufSize2 != 0 ) && ( i_bufSize3 != 0 )), - fapi2::HCODE_TEMP_BUF_SIZE() - .set_TEMP_BUF1_SIZE( i_bufSize1 ) - .set_TEMP_BUF2_SIZE( i_bufSize2 ) - .set_TEMP_BUF3_SIZE( i_bufSize3 ), - "Invalid work buffer size " ); - - FAPI_ASSERT( ( i_pBuf2 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf2 ), - "Invalid temp buffer2 passed for hcode image build" ); - - FAPI_ASSERT( ( i_pBuf3 != NULL ), - fapi2::HCODE_INVALID_TEMP_BUF() - .set_TEMP_BUF_PTR( i_pBuf3 ), - "Invalid temp buffer3 passed for hcode image build" ); - - FAPI_ASSERT( ( i_imgType.isBuildValid() ), - fapi2::HCODE_INVALID_IMG_TYPE(), - "Invalid temp buffer passed for hcode image build" ); - FAPI_DBG("Exiting validateInputArguments ..."); - - fapi_try_exit: - return fapi2::current_err; - } +/** + * @brief validates arguments passed for hcode image build + * @param refer to p9_hcode_image_build arguments + * @return fapi2 return code +*/ +fapi2::ReturnCode validateInputArguments( void* const i_pImageIn, void* i_pImageOut, + SysPhase_t i_phase, ImageType_t i_imgType, + void* i_pBuf1, uint32_t i_bufSize1, void* i_pBuf2, + uint32_t i_bufSize2, void* i_pBuf3, uint32_t i_bufSize3 ) +{ + uint32_t l_rc = IMG_BUILD_SUCCESS; + uint32_t hwImagSize = 0; + + FAPI_DBG("Entering validateInputArguments ..."); + + FAPI_ASSERT( (( i_pImageIn != NULL ) && ( i_pImageOut != NULL ) && + ( i_pImageIn != i_pImageOut )), + fapi2::IMG_PTR_ERROR() + .set_HW_IMG_BUF_PTR( i_pImageIn ) + .set_HOMER_IMG_BUF_PTR( i_pImageOut ), + "Bad pointer to HW Image or HOMER Image" ); + l_rc = p9_xip_image_size( i_pImageIn, &hwImagSize ); + + FAPI_DBG("size is 0x%08X; xip_image_size RC is 0x%02x HARDWARE_IMG_SIZE 0x%08X Sz 0x%08X", + hwImagSize, l_rc, HARDWARE_IMG_SIZE, hwImagSize ); + + FAPI_ASSERT( (( IMG_BUILD_SUCCESS == l_rc ) && ( hwImagSize > 0 ) && + ( HARDWARE_IMG_SIZE >= hwImagSize )), + fapi2::HW_IMAGE_INVALID_SIZE() + .set_HW_IMG_SIZE( hwImagSize ) + .set_MAX_HW_IMG_SIZE( HARDWARE_IMG_SIZE ), + "Hardware image size found out of range" ); + FAPI_ASSERT( (( i_phase > PHASE_NA ) && ( i_phase < PHASE_END )), + fapi2::HCODE_INVALID_PHASE() + .set_SYS_PHASE( i_phase ), + "Invalid value passed as build phase" ); + + FAPI_ASSERT( ( i_pBuf1 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf1 ), + "Invalid temp buffer1 passed for hcode image build" ); + + FAPI_ASSERT( (( i_bufSize1 != 0 ) && ( i_bufSize2 != 0 ) && ( i_bufSize3 != 0 )), + fapi2::HCODE_TEMP_BUF_SIZE() + .set_TEMP_BUF1_SIZE( i_bufSize1 ) + .set_TEMP_BUF2_SIZE( i_bufSize2 ) + .set_TEMP_BUF3_SIZE( i_bufSize3 ), + "Invalid work buffer size " ); + + FAPI_ASSERT( ( i_pBuf2 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf2 ), + "Invalid temp buffer2 passed for hcode image build" ); + + FAPI_ASSERT( ( i_pBuf3 != NULL ), + fapi2::HCODE_INVALID_TEMP_BUF() + .set_TEMP_BUF_PTR( i_pBuf3 ), + "Invalid temp buffer3 passed for hcode image build" ); + + FAPI_ASSERT( ( i_imgType.isBuildValid() ), + fapi2::HCODE_INVALID_IMG_TYPE(), + "Invalid temp buffer passed for hcode image build" ); + FAPI_DBG("Exiting validateInputArguments ..."); + +fapi_try_exit: + return fapi2::current_err; +} //------------------------------------------------------------------------------ - /** - * @brief Copies section of hardware image to HOMER - * @param i_destPtr a location in HOMER - * @param i_srcPtr a location in HW Image. - * @param i_secId XIP Section id to be copied. - * @param i_platId platform associated with the given section. - * @param o_ppeSection contains section details. - * @return IMG_BUILD_SUCCESS if successful, error code otherwise. - */ - uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_secId, PlatId i_platId , - P9XipSection& o_ppeSection ) +/** + * @brief Copies section of hardware image to HOMER + * @param i_destPtr a location in HOMER + * @param i_srcPtr a location in HW Image. + * @param i_secId XIP Section id to be copied. + * @param i_platId platform associated with the given section. + * @param o_ppeSection contains section details. + * @return IMG_BUILD_SUCCESS if successful, error code otherwise. + */ +uint32_t copySectionToHomer( uint8_t* i_destPtr, uint8_t* i_srcPtr, uint8_t i_secId, PlatId i_platId , + P9XipSection& o_ppeSection ) +{ + FAPI_INF("> copySectionToHomer"); + uint32_t retCode = IMG_BUILD_SUCCESS; + ImgSizeBank sizebank; + + do { - FAPI_INF("> copySectionToHomer"); - uint32_t retCode = IMG_BUILD_SUCCESS; - ImgSizeBank sizebank; + char secName[SECTN_NAME_MAX_LEN] = {0}; + o_ppeSection.iv_offset = 0; + o_ppeSection.iv_size = 0; + uint32_t rcTemp = p9_xip_get_section( i_srcPtr, i_secId, &o_ppeSection ); - do + if( rcTemp ) { - char secName[SECTN_NAME_MAX_LEN] = {0}; - o_ppeSection.iv_offset = 0; - o_ppeSection.iv_size = 0; - uint32_t rcTemp = p9_xip_get_section( i_srcPtr, i_secId, &o_ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId ); - retCode = BUILD_FAIL_INVALID_SECTN; - break; - } - - FAPI_DBG("o_ppeSection.iv_offset = %X, " - "o_ppeSection.iv_size = %X, " - "i_secId %d", - o_ppeSection.iv_offset, - o_ppeSection.iv_size, - i_secId); + FAPI_ERR("Failed to get section 0x%08X of Plat 0x%08X", i_secId, i_platId ); + retCode = BUILD_FAIL_INVALID_SECTN; + break; + } - rcTemp = sizebank.isSizeGood( i_platId, i_secId, o_ppeSection.iv_size, secName, SECTN_NAME_MAX_LEN ); + FAPI_DBG("o_ppeSection.iv_offset = %X, " + "o_ppeSection.iv_size = %X, " + "i_secId %d", + o_ppeSection.iv_offset, + o_ppeSection.iv_size, + i_secId); - if ( rcTemp ) - { - FAPI_ERR("??????????Size Exceeds the permissible limit???????" ); - FAPI_ERR("Sec Name: %s Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)", - secName, rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size); - retCode = BUILD_SEC_SIZE_OVERFLOW; - break; - } + rcTemp = sizebank.isSizeGood( i_platId, i_secId, o_ppeSection.iv_size, secName, SECTN_NAME_MAX_LEN ); - memcpy( i_destPtr, i_srcPtr + o_ppeSection.iv_offset, o_ppeSection.iv_size ); + if ( rcTemp ) + { + FAPI_ERR("??????????Size Exceeds the permissible limit???????" ); + FAPI_ERR("Sec Name: %s Max Allowed 0x%08X (%08d) Actual Size 0x%08X (%08d)", + secName, rcTemp, rcTemp, o_ppeSection.iv_size, o_ppeSection.iv_size); + retCode = BUILD_SEC_SIZE_OVERFLOW; + break; } - while(0); - FAPI_INF("< copySectionToHomer"); - return retCode; + memcpy( i_destPtr, i_srcPtr + o_ppeSection.iv_offset, o_ppeSection.iv_size ); } + while(0); + + FAPI_INF("< copySectionToHomer"); + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief Update the CME/SGPE Image Header Flag field. - * @param i_pChipHomer points to HOMER image. - * @return fapi2 return code. - */ - fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +/** + * @brief Update the CME/SGPE Image Header Flag field. + * @param i_pChipHomer points to HOMER image. + * @return fapi2 return code. + */ +fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ + uint8_t attrVal = 0; + uint32_t cmeFlag = 0; + uint32_t sgpeFlag = 0; + pgpe_flags_t pgpeFlags; + + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; + //Handling flags common to CME and SGPE + + FAPI_DBG(" ==================== CME/SGPE Flags ================="); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP4_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP4_DISABLE"); + + if( attrVal ) { - uint8_t attrVal = 0; - uint32_t cmeFlag = 0; - uint32_t sgpeFlag = 0; - pgpe_flags_t pgpeFlags; - - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; - //Handling flags common to CME and SGPE - - FAPI_DBG(" ==================== CME/SGPE Flags ================="); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP4_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP4_DISABLE"); - - if( attrVal ) - { - cmeFlag |= CME_STOP_4_TO_2_BIT_POS; - sgpeFlag |= SGPE_STOP_4_TO_2_BIT_POS; - } + cmeFlag |= CME_STOP_4_TO_2_BIT_POS; + sgpeFlag |= SGPE_STOP_4_TO_2_BIT_POS; + } - FAPI_DBG("STOP_4_to_2 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_4_to_2 : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP5_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP5_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP5_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP5_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_5_TO_4_BIT_POS; - sgpeFlag |= SGPE_STOP_5_TO_4_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_5_TO_4_BIT_POS; + sgpeFlag |= SGPE_STOP_5_TO_4_BIT_POS; + } - FAPI_DBG("STOP_5_to_4 : %s", attrVal ? "TRUE" : "FALSE"); + FAPI_DBG("STOP_5_to_4 : %s", attrVal ? "TRUE" : "FALSE"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP8_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP8_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP8_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP8_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_8_TO_5_BIT_POS; - sgpeFlag |= SGPE_STOP_8_TO_5_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_8_TO_5_BIT_POS; + sgpeFlag |= SGPE_STOP_8_TO_5_BIT_POS; + } - FAPI_DBG("STOP_8_to_5 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_8_to_5 : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP11_DISABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_STOP11_DISABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_STOP11_DISABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_STOP11_DISABLE"); - if( attrVal ) - { - cmeFlag |= CME_STOP_11_TO_8_BIT_POS; - sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS; - } + if( attrVal ) + { + cmeFlag |= CME_STOP_11_TO_8_BIT_POS; + sgpeFlag |= SGPE_STOP_11_TO_8_BIT_POS; + } - FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("STOP_11_to_8 : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE, - i_procTgt, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CME_INSTRUCTION_TRACE_ENABLE, + i_procTgt, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_CME_INSTRUCTION_TRACE_ENABLE"); - if( attrVal ) - { - sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS; - } + if( attrVal ) + { + sgpeFlag |= SGPE_CME_INSTRUCTION_TRACE_BIT_POS; + } - FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("CME Instruction Trace Enabled : %s", attrVal ? "TRUE" : "FALSE" ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_DISABLE_QUEUED_SCAN, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_DISABLE_QUEUED_SCAN" ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_DISABLE_QUEUED_SCAN, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_DISABLE_QUEUED_SCAN" ); - if( attrVal ) - { - cmeFlag |= CME_QUEUED_SCAN_DISABLE; - } + if( attrVal ) + { + cmeFlag |= CME_QUEUED_SCAN_DISABLE; + } - FAPI_DBG("QUEUED_SCAN_DISABLE : %s", attrVal ? "TRUE" : "FALSE" ); + FAPI_DBG("QUEUED_SCAN_DISABLE : %s", attrVal ? "TRUE" : "FALSE" ); - // Set PGPE Header Flags from Attributes - FAPI_DBG(" -------------------- PGPE Flags -----------------"); - pgpeFlags.value = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, - FAPI_SYSTEM, - attrVal), - "Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE"); + // Set PGPE Header Flags from Attributes + FAPI_DBG(" -------------------- PGPE Flags -----------------"); + pgpeFlags.value = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PGPE_HCODE_FUNCTION_ENABLE, + FAPI_SYSTEM, + attrVal), + "Error from FAPI_ATTR_GET for attribute ATTR_PGPE_HCODE_FUNCTION_ENABLE"); - // If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit - if( !attrVal ) - { - pgpeFlags.fields.occ_ipc_immed_response = 1; - } + // If 0 (Hcode disabled), then set the occ_opc_immed_response flag bit + if( !attrVal ) + { + pgpeFlags.fields.occ_ipc_immed_response = 1; + } - FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" ); + FAPI_DBG("PGPE Hcode Mode : %s", attrVal ? "PSTATES Enabled" : "OCC IPC Immediate Response Mode" ); - // Updating flag fields in the headers - pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); - pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag); - pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value); + // Updating flag fields in the headers + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); + pSgpeHdr->g_sgpe_reserve_flags = SWIZZLE_4_BYTE(sgpeFlag); + pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlags.value); - FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); - FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); - FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------=="); + FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); + FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); + FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); + FAPI_DBG(" -------------------- CME/SGPE Flags Ends ---------------=="); - fapi_try_exit: - return fapi2::current_err; - } +fapi_try_exit: + return fapi2::current_err; +} //------------------------------------------------------------------------------ - /** - * @brief updates various CPMR fields which are associated with scan rings. - * @param i_pChipHomer points to start of P9 HOMER. - */ - void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) +/** + * @brief updates various CPMR fields which are associated with scan rings. + * @param i_pChipHomer points to start of P9 HOMER. + */ +void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) +{ + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + + //Updating CPMR Header using info from CME Header + pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CME_IMAGE_CPMR_OFFSET >> CME_BLK_SIZE_SHIFT)); + pCpmrHdr->cmePstateOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); + pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset); + pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length; + pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled + pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_CPMR_OFFSET); + pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL); + + if( pCmeHdr->g_cme_common_ring_length ) { - cpmrHeader_t* pCpmrHdr = - (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - - //Updating CPMR Header using info from CME Header - pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CME_IMAGE_CPMR_OFFSET >> CME_BLK_SIZE_SHIFT)); - pCpmrHdr->cmePstateOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); - pCpmrHdr->cmePstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset); - pCpmrHdr->cmePstateLength = pCmeHdr->g_cme_pstate_region_length; - pCpmrHdr->cmeImgLength = pCmeHdr->g_cme_hcode_length;// already swizzled - pCpmrHdr->coreScomOffset = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_CPMR_OFFSET); - pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL); - - if( pCmeHdr->g_cme_common_ring_length ) - { - pCpmrHdr->cmeCommonRingOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); - pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); - pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length; - } - - if( pCmeHdr->g_cme_max_spec_ring_length ) - { - pCpmrHdr->coreSpecRingOffset = ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) + - SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) + - SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) + - SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength); - pCpmrHdr->coreSpecRingOffset = (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT; - pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset); - pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled - } - - //Updating CME Image header - pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER); - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); - pCmeHdr->g_cme_scom_offset = - ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); - //Adding to it instance ring length which is already a multiple of 32B - pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); - pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME); - - FAPI_INF("========================= CME Header Start =================================="); - char magicWord[16] = {0}; - uint64_t temp = pCmeHdr->g_cme_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); - FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length)); - FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); - FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length)); - FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); - FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); - FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); - FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); - FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); - FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); - FAPI_INF("========================= CME Header End =================================="); - - FAPI_INF("==========================CPMR Header==========================================="); - temp = pCpmrHdr->magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); - FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); - FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); - FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); - FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); - FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); - FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); - FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); - FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); - FAPI_INF("==================================CPMR Ends====================================="); - + pCpmrHdr->cmeCommonRingOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + pCpmrHdr->cmeCommonRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset); + pCpmrHdr->cmeCommonRingLength = pCmeHdr->g_cme_common_ring_length; } -//------------------------------------------------------------------------------ - /** - * @brief updates various CPMR fields which are associated with self restore code. - * @param i_pChipHomer points to start of P9 HOMER. - * @param i_fuseState core fuse status - */ - void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) + if( pCmeHdr->g_cme_max_spec_ring_length ) { - FAPI_INF("> updateCpmrHeaderSR"); - cpmrHeader_t* pCpmrHdr = - (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - //populate CPMR header - pCpmrHdr->fusedModeStatus = i_fusedState ? uint32_t(FUSED_CORE_MODE) : - uint32_t(NONFUSED_CORE_MODE); - pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); - - FAPI_INF("CPMR SR"); - FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, - SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", - SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, - SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); - - FAPI_INF("< updateCpmrHeaderSR"); + pCpmrHdr->coreSpecRingOffset = ( SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) << CME_BLK_SIZE_SHIFT ) + + SWIZZLE_4_BYTE( pCpmrHdr->cmeImgLength) + + SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength) + + SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength); + pCpmrHdr->coreSpecRingOffset = (pCpmrHdr->coreSpecRingOffset + CME_BLOCK_READ_LEN - 1) >> CME_BLK_SIZE_SHIFT; + pCpmrHdr->coreSpecRingOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset); + pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled } + //Updating CME Image header + pCmeHdr->g_cme_magic_number = SWIZZLE_8_BYTE(CME_MAGIC_NUMBER); + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); + pCmeHdr->g_cme_scom_offset = + ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); + //Adding to it instance ring length which is already a multiple of 32B + pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); + pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME); + + FAPI_INF("========================= CME Header Start =================================="); + char magicWord[16] = {0}; + uint64_t temp = pCmeHdr->g_cme_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); + FAPI_INF(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length)); + FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); + FAPI_INF(" PS Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length)); + FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); + FAPI_INF(" CR Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset )); + FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); + FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); + FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); + FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); + FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); + FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); + FAPI_INF("========================= CME Header End =================================="); + + FAPI_INF("==========================CPMR Header==========================================="); + temp = pCpmrHdr->magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); + FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); + FAPI_INF(" PS Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateLength)); + FAPI_INF(" CR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingOffset)); + FAPI_INF(" CR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeCommonRingLength)); + FAPI_INF(" CSR Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset)); + FAPI_INF(" CSR Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength)); + FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); + FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); + FAPI_INF("==================================CPMR Ends====================================="); + +} + //------------------------------------------------------------------------------ - /** - * @brief updates various QPMR header region in HOMER. - * @param i_pChipHomer points to start of P9 HOMER. - * @param io_qpmrHdr temp instance of QpmrHeaderLayout_t used for data collection. - */ - void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrHdr ) - { - QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader); - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); - //FIXME Populating headers fields with max possible values for now. This is to keep things in line with SGPE - //bootloader design. SGPE bootloader doesn't expect a hole in image layout how ever due to current design of - //hcode image build there are holes between various section of image say common and instance ring. - - pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER); - pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER); - pSgpeHdr->g_sgpe_scom_mem_offset = SWIZZLE_4_BYTE(QPMR_HOMER_OFFSET + QUAD_SCOM_RESTORE_QPMR_OFFSET ); - - FAPI_INF("==============================QPMR=================================="); - char magicWord[16] = {0}; - uint64_t temp = pQpmrHdr->magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_DBG(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate)); - FAPI_DBG(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion)); - FAPI_DBG(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset)); - FAPI_DBG(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset)); - FAPI_DBG(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength)); - FAPI_DBG(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset)); - FAPI_DBG(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength)); - FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); - FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); - FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) ); - FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) ); - FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); - FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); - FAPI_INF(" Quad SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomOffset) ); - FAPI_INF(" Quad SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomLength) ); - FAPI_DBG("==============================QPMR Ends=============================="); - - FAPI_DBG("===========================SGPE Image Hdr============================="); - temp = pSgpeHdr->g_sgpe_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG(" Magic Num : %s", magicWord); - FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); - FAPI_DBG(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); - FAPI_DBG(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); - FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); - FAPI_DBG(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset)); - FAPI_DBG(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset)); - FAPI_DBG(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length )); - FAPI_DBG(" 24x7 Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_offset )); - FAPI_DBG(" 24x7 Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_24x7_length )); - FAPI_DBG("========================SGPE Image Hdr Ends==========================="); +/** + * @brief updates various CPMR fields which are associated with self restore code. + * @param i_pChipHomer points to start of P9 HOMER. + * @param i_fuseState core fuse status + */ +void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) +{ + FAPI_INF("> updateCpmrHeaderSR"); + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); + + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + //populate CPMR header + pCpmrHdr->fusedModeStatus = i_fusedState ? uint32_t(FUSED_CORE_MODE) : + uint32_t(NONFUSED_CORE_MODE); + pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); + + FAPI_INF("CPMR SR"); + FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, + SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); + FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", + SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, + SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); + FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + + FAPI_INF("< updateCpmrHeaderSR"); +} - } +//------------------------------------------------------------------------------ +/** + * @brief updates various QPMR header region in HOMER. + * @param i_pChipHomer points to start of P9 HOMER. + * @param io_qpmrHdr temp instance of QpmrHeaderLayout_t used for data collection. + */ +void updateQpmrHeader( Homerlayout_t* i_pChipHomer, QpmrHeaderLayout_t& io_qpmrHdr ) +{ + QpmrHeaderLayout_t* pQpmrHdr = ( QpmrHeaderLayout_t*) & (i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader); + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + memcpy( pQpmrHdr, &io_qpmrHdr, sizeof( QpmrHeaderLayout_t ) ); + pQpmrHdr->magic_number = SWIZZLE_8_BYTE(QPMR_MAGIC_NUMBER); + pSgpeHdr->g_sgpe_magic_number = SWIZZLE_8_BYTE(SGPE_MAGIC_NUMBER); + pSgpeHdr->g_sgpe_scom_mem_offset = SWIZZLE_4_BYTE(QPMR_HOMER_OFFSET + QUAD_SCOM_RESTORE_QPMR_OFFSET ); + + FAPI_INF("==============================QPMR=================================="); + char magicWord[16] = {0}; + uint64_t temp = pQpmrHdr->magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_DBG(" Build Date : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildDate)); + FAPI_DBG(" Version : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->buildVersion)); + FAPI_DBG(" BC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset)); + FAPI_DBG(" BL Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderOffset)); + FAPI_DBG(" BL Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->bootLoaderLength)); + FAPI_DBG(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgOffset)); + FAPI_DBG(" HC Size : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->sgpeImgLength)); + FAPI_DBG(" Cmn Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingOffset) ); + FAPI_DBG(" Cmn Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonRingLength) ); + FAPI_DBG(" Cmn Ring Ovrd Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdOffset) ); + FAPI_DBG(" Cmn Ring Ovrd Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadCommonOvrdLength) ); + FAPI_DBG(" Quad Spec Ring Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingOffset) ); + FAPI_DBG(" Quad Spec Ring Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadSpecRingLength) ); + FAPI_INF(" Quad SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomOffset) ); + FAPI_INF(" Quad SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pQpmrHdr->quadScomLength) ); + FAPI_DBG("==============================QPMR Ends=============================="); + + FAPI_DBG("===========================SGPE Image Hdr============================="); + temp = pSgpeHdr->g_sgpe_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG(" Magic Num : %s", magicWord); + FAPI_DBG(" Cmn Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_occ_offset )); + FAPI_DBG(" Override Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_cmn_ring_ovrd_occ_offset )); + FAPI_DBG(" Flags : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags )); + FAPI_DBG(" Quad Spec Ring Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_spec_ring_occ_offset )); + FAPI_DBG(" Quad SCOM SRAM Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_offset)); + FAPI_DBG(" Quad SCOM Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_offset)); + FAPI_DBG(" Quad SCOM Mem Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_scom_mem_length )); + FAPI_DBG(" Auxiliary Func Offset : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_aux_offset )); + FAPI_DBG(" Auxiliary Func Length : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_aux_length )); + FAPI_DBG("========================SGPE Image Hdr Ends==========================="); + +} //------------------------------------------------------------------------------ - /** - * @brief copies image section associated with SGPE from HW Image to HOMER - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - */ - uint32_t buildSgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, - QpmrHeaderLayout_t& o_qpmrHdr ) +/** + * @brief copies image section associated with SGPE from HW Image to HOMER + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + */ +uint32_t buildSgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, + QpmrHeaderLayout_t& o_qpmrHdr ) +{ + FAPI_INF("> buildSgpeImage"); + uint32_t retCode = IMG_BUILD_SUCCESS; + + do { - FAPI_INF("> buildSgpeImage"); - uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t rcTemp = 0; + //Let us find XIP Header for SGPE + P9XipSection ppeSection; + uint8_t* pSgpeImg = NULL; - do + if(!i_imgType.sgpeHcodeBuild ) { - uint32_t rcTemp = 0; - //Let us find XIP Header for SGPE - P9XipSection ppeSection; - uint8_t* pSgpeImg = NULL; - - if(!i_imgType.sgpeHcodeBuild ) - { - break; - } + break; + } - // Let us start with a clean slate in quad common ring area. - memset( (uint8_t*)&i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, 0x00, SGPE_IMAGE_SIZE ); - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_SGPE, &ppeSection ); + // Let us start with a clean slate in quad common ring area. + memset( (uint8_t*)&i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, 0x00, SGPE_IMAGE_SIZE ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_SGPE, &ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get SGPE XIP Image Header" ); - retCode = BUILD_FAIL_SGPE_IMAGE; - break; - } - - pSgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("HW image SGPE Offset = 0x%08X", ppeSection.iv_offset); + if( rcTemp ) + { + FAPI_ERR("Failed to get SGPE XIP Image Header" ); + retCode = BUILD_FAIL_SGPE_IMAGE; + break; + } - FAPI_INF("QPMR Header"); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, - pSgpeImg, - P9_XIP_SECTION_SGPE_QPMR, - PLAT_SGPE, - ppeSection ); + pSgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("HW image SGPE Offset = 0x%08X", ppeSection.iv_offset); - if( rcTemp ) - { - FAPI_ERR("Failed to copy QPMR Header"); - retCode = BUILD_FAIL_SGPE_QPMR; - break; - } + FAPI_INF("QPMR Header"); + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, + pSgpeImg, + P9_XIP_SECTION_SGPE_QPMR, + PLAT_SGPE, + ppeSection ); - //updating local instance of QPMR header - memcpy( &o_qpmrHdr, i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, sizeof(QpmrHeaderLayout_t)); + if( rcTemp ) + { + FAPI_ERR("Failed to copy QPMR Header"); + retCode = BUILD_FAIL_SGPE_QPMR; + break; + } - FAPI_DBG("SGPE Boot Copier"); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l1BootLoader, - pSgpeImg, - P9_XIP_SECTION_SGPE_LVL1_BL, - PLAT_SGPE, - ppeSection ); + //updating local instance of QPMR header + memcpy( &o_qpmrHdr, i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader, sizeof(QpmrHeaderLayout_t)); - if( rcTemp ) - { - FAPI_ERR("Failed to copy Level1 bootloader"); - retCode = BUILD_FAIL_SGPE_BL1; - break; - } + FAPI_DBG("SGPE Boot Copier"); + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l1BootLoader, + pSgpeImg, + P9_XIP_SECTION_SGPE_LVL1_BL, + PLAT_SGPE, + ppeSection ); - o_qpmrHdr.bootCopierOffset = QPMR_HEADER_SIZE; - FAPI_DBG("SGPE Boot Copier Size = 0x%08X", - o_qpmrHdr.bootCopierOffset); + if( rcTemp ) + { + FAPI_ERR("Failed to copy Level1 bootloader"); + retCode = BUILD_FAIL_SGPE_BL1; + break; + } - FAPI_DBG(" SGPE Boot Loader"); + o_qpmrHdr.bootCopierOffset = QPMR_HEADER_SIZE; + FAPI_DBG("SGPE Boot Copier Size = 0x%08X", + o_qpmrHdr.bootCopierOffset); - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l2BootLoader, - pSgpeImg, - P9_XIP_SECTION_SGPE_LVL2_BL, - PLAT_SGPE, - ppeSection ); + FAPI_DBG(" SGPE Boot Loader"); - if( rcTemp ) - { - FAPI_ERR("Failed to copy Level2 bootloader"); - retCode = BUILD_FAIL_SGPE_BL2; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.l2BootLoader, + pSgpeImg, + P9_XIP_SECTION_SGPE_LVL2_BL, + PLAT_SGPE, + ppeSection ); - o_qpmrHdr.bootLoaderOffset = o_qpmrHdr.bootCopierOffset + SGPE_BOOT_COPIER_SIZE; - o_qpmrHdr.bootLoaderLength = ppeSection.iv_size; + if( rcTemp ) + { + FAPI_ERR("Failed to copy Level2 bootloader"); + retCode = BUILD_FAIL_SGPE_BL2; + break; + } - FAPI_INF("SGPE Boot Loader QPMR Offset = 0x%08X, Size = 0x%08X", - o_qpmrHdr.bootLoaderOffset, o_qpmrHdr.bootLoaderLength); + o_qpmrHdr.bootLoaderOffset = o_qpmrHdr.bootCopierOffset + SGPE_BOOT_COPIER_SIZE; + o_qpmrHdr.bootLoaderLength = ppeSection.iv_size; - rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, - pSgpeImg, - P9_XIP_SECTION_SGPE_HCODE, - PLAT_SGPE, - ppeSection ); + FAPI_INF("SGPE Boot Loader QPMR Offset = 0x%08X, Size = 0x%08X", + o_qpmrHdr.bootLoaderOffset, o_qpmrHdr.bootLoaderLength); - if( rcTemp ) - { - FAPI_ERR("Failed to copy SGPE hcode"); - retCode = BUILD_FAIL_SGPE_HCODE; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage, + pSgpeImg, + P9_XIP_SECTION_SGPE_HCODE, + PLAT_SGPE, + ppeSection ); - memset( i_pChipHomer->qpmrRegion.cacheScomRegion, 0x00, - QUAD_SCOM_RESTORE_SIZE_TOTAL ); + if( rcTemp ) + { + FAPI_ERR("Failed to copy SGPE hcode"); + retCode = BUILD_FAIL_SGPE_HCODE; + break; + } - o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; + memset( i_pChipHomer->qpmrRegion.cacheScomRegion, 0x00, + QUAD_SCOM_RESTORE_SIZE_TOTAL ); - FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X", - SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset), - SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgLength)); + o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; - o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; + FAPI_DBG("SGPE Hcode QPMR Offset = 0x%08X, Size = 0x%08X", + SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset), + SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgLength)); - o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size); - o_qpmrHdr.bootLoaderOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset); - //let us take care of endianess now. - o_qpmrHdr.bootCopierOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset); - o_qpmrHdr.bootLoaderLength = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderLength); - o_qpmrHdr.sgpeImgOffset = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset); + o_qpmrHdr.sgpeImgOffset = o_qpmrHdr.bootLoaderOffset + SGPE_BOOT_LOADER_SIZE; - o_qpmrHdr.quadScomOffset = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_QPMR_OFFSET); - o_qpmrHdr.quadScomLength = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_SIZE_TOTAL); + o_qpmrHdr.sgpeImgLength = SWIZZLE_4_BYTE(ppeSection.iv_size); + o_qpmrHdr.bootLoaderOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderOffset); + //let us take care of endianess now. + o_qpmrHdr.bootCopierOffset = SWIZZLE_4_BYTE(o_qpmrHdr.bootCopierOffset); + o_qpmrHdr.bootLoaderLength = SWIZZLE_4_BYTE(o_qpmrHdr.bootLoaderLength); + o_qpmrHdr.sgpeImgOffset = SWIZZLE_4_BYTE(o_qpmrHdr.sgpeImgOffset); - sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - pImgHdr->g_sgpe_ivpr_address = OCC_SRAM_SGPE_BASE_ADDR; - pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength; - pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = 0; - pImgHdr->g_sgpe_spec_ring_occ_offset = 0; - pImgHdr->g_sgpe_scom_offset = 0; + o_qpmrHdr.quadScomOffset = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_QPMR_OFFSET); + o_qpmrHdr.quadScomLength = SWIZZLE_4_BYTE(QUAD_SCOM_RESTORE_SIZE_TOTAL); - FAPI_INF("SGPE Header"); - FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number)); - FAPI_INF(" Reset Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_reset_address)); - FAPI_INF(" IVPR Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_ivpr_address)); - FAPI_INF(" Build Date = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date)); - FAPI_INF(" Version = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver)); - FAPI_INF(" CR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset)); - FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); + sgpeHeader_t* pImgHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + pImgHdr->g_sgpe_ivpr_address = OCC_SRAM_SGPE_BASE_ADDR; + pImgHdr->g_sgpe_cmn_ring_occ_offset = o_qpmrHdr.sgpeImgLength; + pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = 0; + pImgHdr->g_sgpe_spec_ring_occ_offset = 0; + pImgHdr->g_sgpe_scom_offset = 0; - } - while(0); + FAPI_INF("SGPE Header"); + FAPI_INF(" Magic Num = 0x%16lX", SWIZZLE_8_BYTE(pImgHdr->g_sgpe_magic_number)); + FAPI_INF(" Reset Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_reset_address)); + FAPI_INF(" IVPR Addr = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_ivpr_address)); + FAPI_INF(" Build Date = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_date)); + FAPI_INF(" Version = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_build_ver)); + FAPI_INF(" CR OCC Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_occ_offset)); + FAPI_INF(" CR Ovrd Offset = 0x%08X", SWIZZLE_4_BYTE(pImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); - FAPI_INF("< buildSgpeImage") - return retCode; } + while(0); + + FAPI_INF("< buildSgpeImage") + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies core self restore section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - * @param[in] i_fuseState fuse state of core. - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildCoreRestoreImage( void* const i_pImageIn, - Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, - uint8_t i_fusedState ) +/** + * @brief copies core self restore section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + * @param[in] i_fuseState fuse state of core. + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildCoreRestoreImage( void* const i_pImageIn, + Homerlayout_t* i_pChipHomer, ImageType_t i_imgType, + uint8_t i_fusedState ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; + + do { - uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t rcTemp = 0; + //Let us find XIP Header for Core Self Restore Image + P9XipSection ppeSection; + uint8_t* pSelfRestImg = NULL; + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_RESTORE, &ppeSection ); - do + if( rcTemp ) { - uint32_t rcTemp = 0; - //Let us find XIP Header for Core Self Restore Image - P9XipSection ppeSection; - uint8_t* pSelfRestImg = NULL; - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_RESTORE, &ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to get P9 Self restore Image Header" ); - retCode = BUILD_FAIL_SELF_REST_IMAGE; - break; - } - - pSelfRestImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - - if( i_imgType.selfRestoreBuild ) - { - // first 256 bytes is expected to be zero here. It is by purpose. Just after this step, - // we will add CPMR header in that area. - FAPI_INF("Self Restore Image install"); - FAPI_INF(" Offset = 0x%08X, Size = 0x%08X", - ppeSection.iv_offset, ppeSection.iv_size); - rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, - pSelfRestImg, - P9_XIP_SECTION_RESTORE_SELF, - PLAT_SELF, - ppeSection ); - - if( rcTemp ) - { - FAPI_ERR("Failed to copy SRESET Handler"); - retCode = BUILD_FAIL_SRESET_HNDLR; - break; - } + FAPI_ERR("Failed to get P9 Self restore Image Header" ); + retCode = BUILD_FAIL_SELF_REST_IMAGE; + break; + } - } + pSelfRestImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - // adding CPMR header in first 256 bytes of the CPMR. - FAPI_INF("Overlay CPMR Header at the beginning of CPMR"); + if( i_imgType.selfRestoreBuild ) + { + // first 256 bytes is expected to be zero here. It is by purpose. Just after this step, + // we will add CPMR header in that area. + FAPI_INF("Self Restore Image install"); + FAPI_INF(" Offset = 0x%08X, Size = 0x%08X", + ppeSection.iv_offset, ppeSection.iv_size); rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, pSelfRestImg, - P9_XIP_SECTION_RESTORE_CPMR, + P9_XIP_SECTION_RESTORE_SELF, PLAT_SELF, ppeSection ); if( rcTemp ) { - FAPI_ERR("Failed to copy CPMR header"); - retCode = BUILD_FAIL_CPMR_HDR; + FAPI_ERR("Failed to copy SRESET Handler"); + retCode = BUILD_FAIL_SRESET_HNDLR; break; } - //Pad undefined or runtime section with ATTN Opcode - //Padding SPR restore area with ATTN Opcode - FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes"); - uint32_t wordCnt = 0; - uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); - uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + } - while( wordCnt < SELF_RESTORE_CORE_REGS_SIZE ) - { + // adding CPMR header in first 256 bytes of the CPMR. + FAPI_INF("Overlay CPMR Header at the beginning of CPMR"); + rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.region, + pSelfRestImg, + P9_XIP_SECTION_RESTORE_CPMR, + PLAT_SELF, + ppeSection ); - uint32_t l_fillPattern = 0; + if( rcTemp ) + { + FAPI_ERR("Failed to copy CPMR header"); + retCode = BUILD_FAIL_CPMR_HDR; + break; + } - if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % CORE_RESTORE_SIZE_PER_THREAD ) )) - { - l_fillPattern = l_fillBlr; - } - else - { - l_fillPattern = l_fillAttn; - } + //Pad undefined or runtime section with ATTN Opcode + //Padding SPR restore area with ATTN Opcode + FAPI_INF("Padding CPMR Core Restore portion with Attn opcodes"); + uint32_t wordCnt = 0; + uint32_t l_fillBlr = SWIZZLE_4_BYTE(SELF_RESTORE_BLR_INST); + uint32_t l_fillAttn = SWIZZLE_4_BYTE(CORE_RESTORE_PAD_OPCODE); + + while( wordCnt < SELF_RESTORE_CORE_REGS_SIZE ) + { - //Lab Need: First instruction in thread SPR restore region should be a blr instruction. - //This helps in a specific lab scenario. If Self Restore region is populated only for - //select number of threads, other threads will not hit attention during the self restore - //sequence. Instead, execution will hit a blr and control should return to thread launcher - //region. + uint32_t l_fillPattern = 0; - memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt], - &l_fillPattern, - sizeof( uint32_t )); - wordCnt += 4; + if( ( 0 == wordCnt ) || ( 0 == ( wordCnt % CORE_RESTORE_SIZE_PER_THREAD ) )) + { + l_fillPattern = l_fillBlr; + } + else + { + l_fillPattern = l_fillAttn; } - updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); + //Lab Need: First instruction in thread SPR restore region should be a blr instruction. + //This helps in a specific lab scenario. If Self Restore region is populated only for + //select number of threads, other threads will not hit attention during the self restore + //sequence. Instead, execution will hit a blr and control should return to thread launcher + //region. - memset( i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom, - 0x00, CORE_SCOM_RESTORE_SIZE_TOTAL ); + memcpy( (uint32_t*)&i_pChipHomer->cpmrRegion.selfRestoreRegion.coreSelfRestore[wordCnt], + &l_fillPattern, + sizeof( uint32_t )); + wordCnt += 4; } - while(0); - return retCode; + updateCpmrHeaderSR( i_pChipHomer, i_fusedState ); + + memset( i_pChipHomer->cpmrRegion.selfRestoreRegion.coreScom, + 0x00, CORE_SCOM_RESTORE_SIZE_TOTAL ); } + while(0); + + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies cme section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image. - * @param[in] i_imgType image sections to be built - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, - ImageType_t i_imgType, uint64_t i_cpmrPhyAdd ) - { - uint32_t retCode = IMG_BUILD_SUCCESS; +/** + * @brief copies cme section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image. + * @param[in] i_imgType image sections to be built + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, + ImageType_t i_imgType, uint64_t i_cpmrPhyAdd ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; - do - { - uint32_t rcTemp = 0; - //Let us find XIP Header for CME Image - P9XipSection ppeSection; - uint8_t* pCmeImg = NULL; + do + { + uint32_t rcTemp = 0; + //Let us find XIP Header for CME Image + P9XipSection ppeSection; + uint8_t* pCmeImg = NULL; - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_CME, &ppeSection ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_CME, &ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get CME Image XIP header" ); - retCode = BUILD_FAIL_CME_IMAGE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to get CME Image XIP header" ); + retCode = BUILD_FAIL_CME_IMAGE; + break; + } - pCmeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("ppeSection.iv_offset = 0x%08X, ppeSection.iv_size = 0x%08X", - ppeSection.iv_offset, ppeSection.iv_size); + pCmeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("ppeSection.iv_offset = 0x%08X, ppeSection.iv_size = 0x%08X", + ppeSection.iv_offset, ppeSection.iv_size); - if( !i_imgType.cmeHcodeBuild ) - { - break; - } + if( !i_imgType.cmeHcodeBuild ) + { + break; + } - memset(i_pChipHomer->cpmrRegion.cmeSramRegion, 0x00, CME_REGION_SIZE); + memset(i_pChipHomer->cpmrRegion.cmeSramRegion, 0x00, CME_REGION_SIZE); - // The image in the HW Image has the Interrupt Vectors, CME Header and Debug - // Pointers already included. - rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeSramRegion, pCmeImg, - P9_XIP_SECTION_CME_HCODE, - PLAT_CME, - ppeSection ); + // The image in the HW Image has the Interrupt Vectors, CME Header and Debug + // Pointers already included. + rcTemp = copySectionToHomer( i_pChipHomer->cpmrRegion.cmeSramRegion, pCmeImg, + P9_XIP_SECTION_CME_HCODE, + PLAT_CME, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to append CME Hcode"); - retCode = BUILD_FAIL_CME_HCODE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to append CME Hcode"); + retCode = BUILD_FAIL_CME_HCODE; + break; + } - // Initializing CME Image header - // Names have g_ prefix as these global variables for CME Hcode - // Note: Only the *memory* addresses are updated - cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; - pImgHdr->g_cme_hcode_length = ppeSection.iv_size; - - //Populating common ring offset here. So, that other scan ring related field can be updated. - pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_HOMER_OFFSET); - pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; - pImgHdr->g_cme_pstate_region_length = 0; - pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; - pImgHdr->g_cme_common_ring_length = 0; - pImgHdr->g_cme_scom_offset = 0; - pImgHdr->g_cme_scom_length = CORE_SCOM_RESTORE_SIZE_PER_CME; - pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks - pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks - - //Let us handle the endianess at the end - pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); - pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); - pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); - pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); - pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); - pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(pImgHdr->g_cme_cpmr_PhyAddr); - } - while(0); - - return retCode; + // Initializing CME Image header + // Names have g_ prefix as these global variables for CME Hcode + // Note: Only the *memory* addresses are updated + cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; + pImgHdr->g_cme_hcode_length = ppeSection.iv_size; + + //Populating common ring offset here. So, that other scan ring related field can be updated. + pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_HOMER_OFFSET); + pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; + pImgHdr->g_cme_pstate_region_length = 0; + pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; + pImgHdr->g_cme_common_ring_length = 0; + pImgHdr->g_cme_scom_offset = 0; + pImgHdr->g_cme_scom_length = CORE_SCOM_RESTORE_SIZE_PER_CME; + pImgHdr->g_cme_core_spec_ring_offset = 0; // multiple of 32B blocks + pImgHdr->g_cme_max_spec_ring_length = 0; // multiple of 32B blocks + + //Let us handle the endianess at the end + pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); + pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); + pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); + pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); + pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); + pImgHdr->g_cme_cpmr_PhyAddr = SWIZZLE_8_BYTE(pImgHdr->g_cme_cpmr_PhyAddr); } + while(0); + + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief copies PGPE section from hardware image to HOMER. - * @param[in] i_pImageIn points to start of hardware image. - * @param[in] i_pChipHomer points to HOMER image in main memory. - * @param[io] io_ppmrHdr an instance of PpmrHeader_t - * @param[in] i_imgType image sections to be built - * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. - */ - uint32_t buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, - PpmrHeader_t& io_ppmrHdr, ImageType_t i_imgType ) - { - uint32_t retCode = IMG_BUILD_SUCCESS; - FAPI_INF("> PGPE Img build") +/** + * @brief copies PGPE section from hardware image to HOMER. + * @param[in] i_pImageIn points to start of hardware image. + * @param[in] i_pChipHomer points to HOMER image in main memory. + * @param[io] io_ppmrHdr an instance of PpmrHeader_t + * @param[in] i_imgType image sections to be built + * @return IMG_BUILD_SUCCESS if function succeeds, error code otherwise. + */ +uint32_t buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChipHomer, + PpmrHeader_t& io_ppmrHdr, ImageType_t i_imgType ) +{ + uint32_t retCode = IMG_BUILD_SUCCESS; + FAPI_INF("> PGPE Img build") - do - { - uint32_t rcTemp = 0; - //Let us find XIP Header for SGPE - P9XipSection ppeSection; - uint8_t* pPgpeImg = NULL; + do + { + uint32_t rcTemp = 0; + //Let us find XIP Header for SGPE + P9XipSection ppeSection; + uint8_t* pPgpeImg = NULL; - //Init PGPE region with zero - memset( i_pChipHomer->ppmrRegion.ppmrHeader, 0x00, ONE_MB ); + //Init PGPE region with zero + memset( i_pChipHomer->ppmrRegion.ppmrHeader, 0x00, ONE_MB ); - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) i_pChipHomer->ppmrRegion.ppmrHeader; - if(!i_imgType.pgpeImageBuild ) - { - break; - } + if(!i_imgType.pgpeImageBuild ) + { + break; + } - rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_PGPE, &ppeSection ); + rcTemp = p9_xip_get_section( i_pImageIn, P9_XIP_SECTION_HW_PGPE, &ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to get PGPE XIP Image Header" ); - retCode = BUILD_FAIL_PGPE_IMAGE; - break; - } + if( rcTemp ) + { + FAPI_ERR("Failed to get PGPE XIP Image Header" ); + retCode = BUILD_FAIL_PGPE_IMAGE; + break; + } - pPgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); - FAPI_DBG("HW image PGPE Offset = 0x%08X", ppeSection.iv_offset); + pPgpeImg = ppeSection.iv_offset + (uint8_t*) (i_pImageIn ); + FAPI_DBG("HW image PGPE Offset = 0x%08X", ppeSection.iv_offset); - FAPI_INF("PPMR Header"); - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.ppmrHeader, - pPgpeImg, - P9_XIP_SECTION_PGPE_PPMR, - PLAT_PGPE, - ppeSection ); + FAPI_INF("PPMR Header"); + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.ppmrHeader, + pPgpeImg, + P9_XIP_SECTION_PGPE_PPMR, + PLAT_PGPE, + ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PPMR Header"); - retCode = BUILD_FAIL_PGPE_PPMR; - break; - } - - memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t)); + if( rcTemp ) + { + FAPI_ERR("Failed to copy PPMR Header"); + retCode = BUILD_FAIL_PGPE_PPMR; + break; + } - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader, - pPgpeImg, - P9_XIP_SECTION_PGPE_LVL1_BL, - PLAT_PGPE, - ppeSection ); + memcpy( &io_ppmrHdr, pPpmrHdr, sizeof(PpmrHeader_t)); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE Level1 bootloader"); - retCode = BUILD_FAIL_PGPE_BL1; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l1BootLoader, + pPgpeImg, + P9_XIP_SECTION_PGPE_LVL1_BL, + PLAT_PGPE, + ppeSection ); - io_ppmrHdr.g_ppmr_bc_offset = PPMR_HEADER_SIZE; + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE Level1 bootloader"); + retCode = BUILD_FAIL_PGPE_BL1; + break; + } + io_ppmrHdr.g_ppmr_bc_offset = PPMR_HEADER_SIZE; - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader, - pPgpeImg, - P9_XIP_SECTION_PGPE_LVL2_BL, - PLAT_PGPE, - ppeSection ); - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE Level2 bootloader"); - retCode = BUILD_FAIL_PGPE_BL2; - break; - } + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.l2BootLoader, + pPgpeImg, + P9_XIP_SECTION_PGPE_LVL2_BL, + PLAT_PGPE, + ppeSection ); - io_ppmrHdr.g_ppmr_bl_offset = io_ppmrHdr.g_ppmr_bc_offset + PGPE_BOOT_COPIER_SIZE; - io_ppmrHdr.g_ppmr_bl_length = ppeSection.iv_size; - - rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeSramImage, - pPgpeImg, - P9_XIP_SECTION_PGPE_HCODE, - PLAT_PGPE, - ppeSection ); + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE Level2 bootloader"); + retCode = BUILD_FAIL_PGPE_BL2; + break; + } - if( rcTemp ) - { - FAPI_ERR("Failed to copy PGPE hcode"); - retCode = BUILD_FAIL_PGPE_HCODE; - break; - } + io_ppmrHdr.g_ppmr_bl_offset = io_ppmrHdr.g_ppmr_bc_offset + PGPE_BOOT_COPIER_SIZE; + io_ppmrHdr.g_ppmr_bl_length = ppeSection.iv_size; - io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_BOOT_LOADER_SIZE; - io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size; + rcTemp = copySectionToHomer( i_pChipHomer->ppmrRegion.pgpeSramImage, + pPgpeImg, + P9_XIP_SECTION_PGPE_HCODE, + PLAT_PGPE, + ppeSection ); - //Finally let us take care of endianess - io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); - io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); - io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length); - io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset); - io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + if( rcTemp ) + { + FAPI_ERR("Failed to copy PGPE hcode"); + retCode = BUILD_FAIL_PGPE_HCODE; + break; } - while(0); - FAPI_INF("< PGPE Img build") - return retCode; + io_ppmrHdr.g_ppmr_hcode_offset = io_ppmrHdr.g_ppmr_bl_offset + PGPE_BOOT_LOADER_SIZE; + io_ppmrHdr.g_ppmr_hcode_length = ppeSection.iv_size; + + //Finally let us take care of endianess + io_ppmrHdr.g_ppmr_bc_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bc_offset); + io_ppmrHdr.g_ppmr_bl_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_offset); + io_ppmrHdr.g_ppmr_bl_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_bl_length); + io_ppmrHdr.g_ppmr_hcode_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset); + io_ppmrHdr.g_ppmr_hcode_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); } + while(0); + + FAPI_INF("< PGPE Img build") + return retCode; +} //------------------------------------------------------------------------------ - /** - * @brief get a blob of platform rings in a temp buffer. - * @param i_hwImage points to hardware image. - * @param i_procTgt processor target - * @param i_ringData temp data struct - */ - uint32_t getPpeScanRings( void* const i_pHwImage, - PlatId i_ppeType, - CONST_FAPI2_PROC& i_procTgt, - RingBufData& i_ringData, - ImageType_t i_imgType ) - { - FAPI_INF(">getPpeScanRings"); - uint32_t retCode = IMG_BUILD_SUCCESS; - uint32_t hwImageSize = 0; +/** + * @brief get a blob of platform rings in a temp buffer. + * @param i_hwImage points to hardware image. + * @param i_procTgt processor target + * @param i_ringData temp data struct + */ +uint32_t getPpeScanRings( void* const i_pHwImage, + PlatId i_ppeType, + CONST_FAPI2_PROC& i_procTgt, + RingBufData& i_ringData, + ImageType_t i_imgType ) +{ + FAPI_INF(">getPpeScanRings"); + uint32_t retCode = IMG_BUILD_SUCCESS; + uint32_t hwImageSize = 0; - do + do + { + if(( !i_imgType.cmeCommonRingBuild && !i_imgType.cmeCoreSpecificRingBuild ) || + ( i_imgType.sgpeCommonRingBuild && !i_imgType.sgpeCacheSpecificRingBuild )) { - if(( !i_imgType.cmeCommonRingBuild && !i_imgType.cmeCoreSpecificRingBuild ) || - ( i_imgType.sgpeCommonRingBuild && !i_imgType.sgpeCacheSpecificRingBuild )) - { - break; - } - - p9_xip_image_size( i_pHwImage, &hwImageSize ); + break; + } - P9XipSection ppeSection; - retCode = p9_xip_get_section( i_pHwImage, P9_XIP_SECTION_HW_RINGS, &ppeSection ); + p9_xip_image_size( i_pHwImage, &hwImageSize ); - if( retCode ) - { - FAPI_ERR("Failed to access scan rings for %s", (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - retCode = BUILD_FAIL_RING_EXTRACTN; - break; - } + P9XipSection ppeSection; + retCode = p9_xip_get_section( i_pHwImage, P9_XIP_SECTION_HW_RINGS, &ppeSection ); - if( 0 == ppeSection.iv_size ) - { - retCode = BUILD_FAIL_RING_EXTRACTN; - FAPI_ERR("Empty .rings section not allowed: <.rings>.iv_size = %d Plat %s", - ppeSection.iv_size, (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - break; - } + if( retCode ) + { + FAPI_ERR("Failed to access scan rings for %s", (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + retCode = BUILD_FAIL_RING_EXTRACTN; + break; + } - FAPI_DBG("------------------ Input Buffer Specs --------------------"); - FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize); - FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); - FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", - (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); - FAPI_DBG("---------------=== Buffer Specs Ends --------------------"); - - FAPI_DBG("--------------- Buffer Initializaiton to 0 --------------------"); - //Init all temp buffers before using. - memset( (uint8_t*) i_ringData.iv_pRingBuffer, 0x00, i_ringData.iv_ringBufSize ); - memset( (uint8_t*) i_ringData.iv_pWorkBuf1, 0x00, i_ringData.iv_sizeWorkBuf1 ); - memset( (uint8_t*) i_ringData.iv_pWorkBuf2, 0x00, i_ringData.iv_sizeWorkBuf2 ); - - uint32_t l_bootMask = ENABLE_ALL_CORE; - fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; - - FAPI_EXEC_HWP( l_fapiRc, - p9_xip_customize, - i_procTgt, - i_pHwImage, - hwImageSize, - i_ringData.iv_pRingBuffer, - i_ringData.iv_ringBufSize, - (i_ppeType == PLAT_CME) ? SYSPHASE_RT_CME : SYSPHASE_RT_SGPE, - MODEBUILD_IPL, - i_ringData.iv_pWorkBuf1, - i_ringData.iv_sizeWorkBuf1, - i_ringData.iv_pWorkBuf2, - i_ringData.iv_sizeWorkBuf2, - l_bootMask ); - - if( l_fapiRc ) - { - retCode = BUILD_FAIL_RING_EXTRACTN; - FAPI_ERR("p9_xip_customize failed to extract rings for %s", - (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); - break; - } + if( 0 == ppeSection.iv_size ) + { + retCode = BUILD_FAIL_RING_EXTRACTN; + FAPI_ERR("Empty .rings section not allowed: <.rings>.iv_size = %d Plat %s", + ppeSection.iv_size, (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + break; } - while(0); - FAPI_INF("<getPpeScanRings " ); - return retCode; + FAPI_DBG("------------------ Input Buffer Specs --------------------"); + FAPI_DBG("Ring section (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pRingBuffer), i_ringData.iv_ringBufSize); + FAPI_DBG("Work buf1 (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pWorkBuf1), i_ringData.iv_sizeWorkBuf1); + FAPI_DBG("Work buf2 (buf,size)=(0x%016llX,0x%08X)", + (uintptr_t)(i_ringData.iv_pWorkBuf2), i_ringData.iv_sizeWorkBuf2); + FAPI_DBG("---------------=== Buffer Specs Ends --------------------"); + + FAPI_DBG("--------------- Buffer Initializaiton to 0 --------------------"); + //Init all temp buffers before using. + memset( (uint8_t*) i_ringData.iv_pRingBuffer, 0x00, i_ringData.iv_ringBufSize ); + memset( (uint8_t*) i_ringData.iv_pWorkBuf1, 0x00, i_ringData.iv_sizeWorkBuf1 ); + memset( (uint8_t*) i_ringData.iv_pWorkBuf2, 0x00, i_ringData.iv_sizeWorkBuf2 ); + + uint32_t l_bootMask = ENABLE_ALL_CORE; + fapi2::ReturnCode l_fapiRc = fapi2::FAPI2_RC_SUCCESS; + + FAPI_EXEC_HWP( l_fapiRc, + p9_xip_customize, + i_procTgt, + i_pHwImage, + hwImageSize, + i_ringData.iv_pRingBuffer, + i_ringData.iv_ringBufSize, + (i_ppeType == PLAT_CME) ? SYSPHASE_RT_CME : SYSPHASE_RT_SGPE, + MODEBUILD_IPL, + i_ringData.iv_pWorkBuf1, + i_ringData.iv_sizeWorkBuf1, + i_ringData.iv_pWorkBuf2, + i_ringData.iv_sizeWorkBuf2, + l_bootMask ); + + if( l_fapiRc ) + { + retCode = BUILD_FAIL_RING_EXTRACTN; + FAPI_ERR("p9_xip_customize failed to extract rings for %s", + (i_ppeType == PLAT_CME ) ? "CME" : "SGPE" ); + break; + } } + while(0); + + FAPI_INF("<getPpeScanRings " ); + return retCode; +} //------------------------------------------------------------------------------ - uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - QpmrHeaderLayout_t& i_qpmrHdr, - ImageType_t i_imgType ) +uint32_t layoutSgpeScanOverride( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + QpmrHeaderLayout_t& i_qpmrHdr, + ImageType_t i_imgType ) +{ + FAPI_INF("> layoutSgpeScanOverride "); + uint32_t rc = IMG_BUILD_SUCCESS; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + RingBucket sgpeOvrdRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do { - FAPI_INF("> layoutSgpeScanOverride "); - uint32_t rc = IMG_BUILD_SUCCESS; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - RingBucket sgpeOvrdRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); + if( !i_imgType.sgpeCommonRingBuild ) + { + break; + } - do + if( !i_pOverride ) { - if( !i_imgType.sgpeCommonRingBuild ) - { - break; - } + break; + } - if( !i_pOverride ) - { - break; - } + uint32_t commonRingLength = i_qpmrHdr.quadCommonRingLength; + + //Start override ring from the actual end of base common rings. Remeber overrides reside within area + //earmarked for common rings + uint8_t* pOverrideStart = + &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[commonRingLength + SWIZZLE_4_BYTE(i_qpmrHdr.sgpeImgLength)]; + uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; - uint32_t commonRingLength = i_qpmrHdr.quadCommonRingLength; + //get core common rings + uint8_t* pOvrdRingPayload = pOverrideStart + QUAD_COMMON_RING_INDEX_SIZE; + uint32_t tempRingLength = 0; + uint32_t tempBufSize = 0; + bool overrideNotFound = true; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + FAPI_DBG("TOR Version : 0x%02x", P9_TOR::tor_version() ); - //Start override ring from the actual end of base common rings. Remeber overrides reside within area - //earmarked for common rings - uint8_t* pOverrideStart = - &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[commonRingLength + SWIZZLE_4_BYTE(i_qpmrHdr.sgpeImgLength)]; - uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; + for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_common_rings; + ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf1; - //get core common rings - uint8_t* pOvrdRingPayload = pOverrideStart + QUAD_COMMON_RING_INDEX_SIZE; - uint32_t tempRingLength = 0; - uint32_t tempBufSize = 0; - bool overrideNotFound = true; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - FAPI_DBG("TOR Version : 0x%02x", P9_TOR::tor_version() ); + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); + rc = tor_get_single_ring( i_pOverride, + P9_XIP_MAGIC_SEEPROM, + i_chipState.getChipLevel(), + sgpeOvrdRings.getCommonRingId( ringIndex ), + P9_TOR::SBE, + OVERRIDE, + CACHE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf2, + tempBufSize, + i_debugMode ); - for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_common_rings; - ringIndex++ ) + if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) { - tempBufSize = i_ringData.iv_sizeWorkBuf1; + tempBufSize = 0; + continue; + } - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); - rc = tor_get_single_ring( i_pOverride, - P9_XIP_MAGIC_SEEPROM, - i_chipState.getChipLevel(), - sgpeOvrdRings.getCommonRingId( ringIndex ), - P9_TOR::SBE, - OVERRIDE, - CACHE0_CHIPLET_ID, - &i_ringData.iv_pWorkBuf2, - tempBufSize, - i_debugMode ); + overrideNotFound = false; + ALIGN_DWORD(tempRingLength, tempBufSize) + ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload ); - if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) - { - tempBufSize = 0; - continue; - } - overrideNotFound = false; - ALIGN_DWORD(tempRingLength, tempBufSize) - ALIGN_RING_LOC( pOverrideStart, pOvrdRingPayload ); + memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + ringStartToHdrOffset); + sgpeOvrdRings.setRingOffset(pOvrdRingPayload, sgpeOvrdRings.getCommonRingId( ringIndex )); + sgpeOvrdRings.setRingSize( sgpeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + sgpeOvrdRings.extractRing( i_ringData.iv_pWorkBuf2, tempBufSize, sgpeOvrdRings.getCommonRingId( ringIndex ) ); - memcpy( pOvrdRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOvrdRingPayload - pOverrideStart) + ringStartToHdrOffset); + pOvrdRingPayload = pOvrdRingPayload + tempBufSize; - sgpeOvrdRings.setRingOffset(pOvrdRingPayload, sgpeOvrdRings.getCommonRingId( ringIndex )); - sgpeOvrdRings.setRingSize( sgpeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); - sgpeOvrdRings.extractRing( i_ringData.iv_pWorkBuf2, tempBufSize, sgpeOvrdRings.getCommonRingId( ringIndex ) ); + //cleaning up what we wrote in temp buffer last time + memset( i_ringData.iv_pWorkBuf2, 0x00, tempBufSize ); + } - pOvrdRingPayload = pOvrdRingPayload + tempBufSize; + if( overrideNotFound ) + { + FAPI_INF("Overrides not found for SGPE"); + rc = BUILD_FAIL_OVERRIDE; // Not considered an error + break; + } - //cleaning up what we wrote in temp buffer last time - memset( i_ringData.iv_pWorkBuf2, 0x00, tempBufSize ); - } + tempRingLength = (pOvrdRingPayload - pOverrideStart ); + pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + commonRingLength; + i_qpmrHdr.quadCommonRingLength = commonRingLength + tempRingLength; + i_qpmrHdr.quadCommonOvrdLength = tempRingLength; + i_qpmrHdr.quadCommonOvrdOffset = i_qpmrHdr.quadCommonRingOffset + commonRingLength; + pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset); - if( overrideNotFound ) - { - FAPI_INF("Overrides not found for SGPE"); - rc = BUILD_FAIL_OVERRIDE; // Not considered an error - break; - } + } + while(0); - tempRingLength = (pOvrdRingPayload - pOverrideStart ); - pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset) + commonRingLength; - i_qpmrHdr.quadCommonRingLength = commonRingLength + tempRingLength; - i_qpmrHdr.quadCommonOvrdLength = tempRingLength; - i_qpmrHdr.quadCommonOvrdOffset = i_qpmrHdr.quadCommonRingOffset + commonRingLength; - pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset); + FAPI_DBG("--------------------SGPE Override Rings---------------=" ); + FAPI_DBG("--------------------SGPE Header --------------------===="); + FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); - } - while(0); + sgpeOvrdRings.dumpOverrideRings(); - FAPI_DBG("--------------------SGPE Override Rings---------------=" ); - FAPI_DBG("--------------------SGPE Header --------------------===="); - FAPI_DBG("Override Ring Offset 0x%08X", SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_ovrd_occ_offset)); + FAPI_INF("< layoutSgpeScanOverride") + return rc; +} - sgpeOvrdRings.dumpOverrideRings(); +/** + * @brief update fields of PGPE image header region with parameter block info. + * @param i_pHomer points to start of chip's HOMER. + */ - FAPI_INF("< layoutSgpeScanOverride") - return rc; - } - /** - * @brief update fields of PGPE image header region with parameter block info. - * @param i_pHomer points to start of chip's HOMER. - */ +void updatePgpeHeader( void* const i_pHomer ) +{ + FAPI_DBG("> updatePgpeHeader"); + Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; + PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)&pHomerLayout->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; + PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) pHomerLayout->ppmrRegion.ppmrHeader; + + //Updating PGPE Image Header + pPgpeHdr->g_pgpe_ivpr_addr = OCC_SRAM_PGPE_BASE_ADDR; + + //Global P-State Parameter Block SRAM address + pPgpeHdr->g_pgpe_gppb_sram_addr = 0; // set by PGPE Hcode + + //PGPE Hcode length + pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length); + + //Global P-State Parameter Block HOMER address + pPgpeHdr->g_pgpe_gppb_mem_offset = (HOMER_PPMR_BASE_ADDR | + (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset))); + + //Global P-State Parameter Block length + pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length); + + //P-State Parameter Block HOMER offset + pPgpeHdr->g_pgpe_gen_pstables_mem_offset = (HOMER_PPMR_BASE_ADDR | + (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset))); + + //P-State Table length + pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length); + + //OCC P-State Table SRAM address + pPgpeHdr->g_pgpe_occ_pstables_sram_addr = 0; + + //OCC P-State Table Length + pPgpeHdr->g_pgpe_occ_pstables_len = 0; + + //PGPE Beacon SRAM address + pPgpeHdr->g_pgpe_beacon_addr = 0; + pPgpeHdr->g_quad_status_addr = 0; + pPgpeHdr->g_wof_table_addr = 0; + pPgpeHdr->g_wof_table_length = 0; + + //Finally handling the endianess + pPgpeHdr->g_pgpe_magic_number = SWIZZLE_8_BYTE(PGPE_MAGIC_NUMBER); + pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr); + pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length); + pPgpeHdr->g_pgpe_gppb_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset); + pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length); + pPgpeHdr->g_pgpe_gen_pstables_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset); + pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length); + pPgpeHdr->g_pgpe_occ_pstables_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr); + pPgpeHdr->g_pgpe_occ_pstables_len = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len); + pPgpeHdr->g_pgpe_beacon_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr); + pPgpeHdr->g_quad_status_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr); + pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr); + pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length); + + FAPI_DBG("================================PGPE Image Header==========================================") + char magicWord[16] = {0}; + uint64_t temp = pPgpeHdr->g_pgpe_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG("PGPE Magic Word : %s", magicWord); + FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); + FAPI_DBG("GPPB SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr)); + FAPI_DBG("GPPB Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset)); + FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); + FAPI_DBG("PS Table Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset)); + FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length)); + FAPI_DBG("OCC PST SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr)); + FAPI_DBG("OCC PST Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len)); + FAPI_DBG("Beacon Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr)); + FAPI_DBG("Quad Status : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr)); + FAPI_DBG("WOF Addr : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr)); + FAPI_DBG("WOF Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length)); + FAPI_DBG("==============================PGPE Image Header End========================================") + + FAPI_DBG("< updatePgpeHeader"); +} +//--------------------------------------------------------------------------- - void updatePgpeHeader( void* const i_pHomer ) - { - FAPI_DBG("> updatePgpeHeader"); - Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)&pHomerLayout->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; - PpmrHeader_t* pPpmrHdr = ( PpmrHeader_t* ) pHomerLayout->ppmrRegion.ppmrHeader; - - //Updating PGPE Image Header - pPgpeHdr->g_pgpe_ivpr_addr = OCC_SRAM_PGPE_BASE_ADDR; - - //Global P-State Parameter Block SRAM address - pPgpeHdr->g_pgpe_gppb_sram_addr = 0; // set by PGPE Hcode - - //PGPE Hcode length - pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length); - - //Global P-State Parameter Block HOMER address - pPgpeHdr->g_pgpe_gppb_mem_offset = (HOMER_PPMR_BASE_ADDR | - (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset))); - - //Global P-State Parameter Block length - pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length); - - //P-State Parameter Block HOMER offset - pPgpeHdr->g_pgpe_gen_pstables_mem_offset = (HOMER_PPMR_BASE_ADDR | - (SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset))); - - //P-State Table length - pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length); - - //OCC P-State Table SRAM address - pPgpeHdr->g_pgpe_occ_pstables_sram_addr = 0; - - //OCC P-State Table Length - pPgpeHdr->g_pgpe_occ_pstables_len = 0; - - //PGPE Beacon SRAM address - pPgpeHdr->g_pgpe_beacon_addr = 0; - pPgpeHdr->g_quad_status_addr = 0; - pPgpeHdr->g_wof_table_addr = 0; - pPgpeHdr->g_wof_table_length = 0; - - //Finally handling the endianess - pPgpeHdr->g_pgpe_magic_number = SWIZZLE_8_BYTE(PGPE_MAGIC_NUMBER); - pPgpeHdr->g_pgpe_gppb_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr); - pPgpeHdr->g_pgpe_hcode_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_hcode_length); - pPgpeHdr->g_pgpe_gppb_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset); - pPgpeHdr->g_pgpe_gppb_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length); - pPgpeHdr->g_pgpe_gen_pstables_mem_offset = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset); - pPgpeHdr->g_pgpe_gen_pstables_length = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length); - pPgpeHdr->g_pgpe_occ_pstables_sram_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr); - pPgpeHdr->g_pgpe_occ_pstables_len = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len); - pPgpeHdr->g_pgpe_beacon_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr); - pPgpeHdr->g_quad_status_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr); - pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr); - pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length); - - FAPI_DBG("================================PGPE Image Header==========================================") - char magicWord[16] = {0}; - uint64_t temp = pPgpeHdr->g_pgpe_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG("PGPE Magic Word : %s", magicWord); - FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); - FAPI_DBG("GPPB SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_sram_addr)); - FAPI_DBG("GPPB Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_mem_offset)); - FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gppb_length)); - FAPI_DBG("PS Table Mem Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_mem_offset)); - FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_gen_pstables_length)); - FAPI_DBG("OCC PST SRAM : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_sram_addr)); - FAPI_DBG("OCC PST Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_occ_pstables_len)); - FAPI_DBG("Beacon Offset : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_pgpe_beacon_addr)); - FAPI_DBG("Quad Status : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_quad_status_addr)); - FAPI_DBG("WOF Addr : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_addr)); - FAPI_DBG("WOF Length : 0x%08x", SWIZZLE_4_BYTE(pPgpeHdr->g_wof_table_length)); - FAPI_DBG("==============================PGPE Image Header End========================================") - - FAPI_DBG("< updatePgpeHeader"); - } +void updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrHdr ) +{ + FAPI_DBG("> updatePpmrHeader"); + Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; + PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) &pHomerLayout->ppmrRegion.ppmrHeader; + memcpy( pPpmrHdr, &io_ppmrHdr, sizeof(PpmrHeader_t) ); + + FAPI_DBG("=========================== PPMR Header ====================================" ); + char magicWord[16] = {0}; + uint64_t temp = io_ppmrHdr.g_ppmr_magic_number; + memcpy(magicWord, &temp, sizeof(uint64_t)); + FAPI_DBG("Magic Word : %s", magicWord); + FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset)); + FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset)); + FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length)); + FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset)); + FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length)); + FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset)); + FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length)); + FAPI_DBG("LPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_offset)); + FAPI_DBG("LPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_length)); + FAPI_DBG("OPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_offset)); + FAPI_DBG("OPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_length)); + FAPI_DBG("PS Table Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset)); + FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length)); + FAPI_DBG("PSGPE SRAM Size : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size)); + FAPI_DBG("=========================== PPMR Header ends ==================================" ); + + updatePgpeHeader( i_pHomer ); + + FAPI_DBG("< updatePpmrHeader"); +} //--------------------------------------------------------------------------- - void updatePpmrHeader( void* const i_pHomer, PpmrHeader_t& io_ppmrHdr ) +/** + * @brief updates the PState parameter block info in CPMR and PPMR region. + * @param i_pHomer points to start of of chip's HOMER. + * @param i_procTgt fapi2 target associated with P9 chip. + * @param i_imgType image type to be built. + * return fapi2::Returncode + */ +fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i_procTgt, + PpmrHeader_t& io_ppmrHdr, + ImageType_t i_imgType ) +{ + FAPI_INF("buildParameterBlock entered"); + + do { - FAPI_DBG("> updatePpmrHeader"); + if( !i_imgType.pgpePstateParmBlockBuild ) + { + break; + } + + fapi2::ReturnCode retCode; Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) &pHomerLayout->ppmrRegion.ppmrHeader; - memcpy( pPpmrHdr, &io_ppmrHdr, sizeof(PpmrHeader_t) ); - - FAPI_DBG("=========================== PPMR Header ====================================" ); - char magicWord[16] = {0}; - uint64_t temp = io_ppmrHdr.g_ppmr_magic_number; - memcpy(magicWord, &temp, sizeof(uint64_t)); - FAPI_DBG("Magic Word : %s", magicWord); - FAPI_DBG("BC Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset)); - FAPI_DBG("BL Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_offset)); - FAPI_DBG("BL Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bl_length)); - FAPI_DBG("Hcode Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_offset)); - FAPI_DBG("Hcode Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_hcode_length)); - FAPI_DBG("GPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_offset)); - FAPI_DBG("GPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_gppb_length)); - FAPI_DBG("LPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_offset)); - FAPI_DBG("LPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_lppb_length)); - FAPI_DBG("OPPB Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_offset)); - FAPI_DBG("OPPB Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_oppb_length)); - FAPI_DBG("PS Table Offset : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_offset)); - FAPI_DBG("PS Table Length : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pstables_length)); - FAPI_DBG("PSGPE SRAM Size : 0x%08x", SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_pgpe_sram_img_size)); - FAPI_DBG("=========================== PPMR Header ends ==================================" ); - - updatePgpeHeader( i_pHomer ); - - FAPI_DBG("< updatePpmrHeader"); - } + PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; -//--------------------------------------------------------------------------- + uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) + + SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - /** - * @brief updates the PState parameter block info in CPMR and PPMR region. - * @param i_pHomer points to start of of chip's HOMER. - * @param i_procTgt fapi2 target associated with P9 chip. - * @param i_imgType image type to be built. - * return fapi2::Returncode - */ - fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i_procTgt, - PpmrHeader_t& io_ppmrHdr, - ImageType_t i_imgType ) - { - FAPI_INF("buildParameterBlock entered"); + FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset ); - do - { - if( !i_imgType.pgpePstateParmBlockBuild ) - { - break; - } + uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - fapi2::ReturnCode retCode; - Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; - PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset ); - uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) + - SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + uint32_t sizeAligned = 0; + uint32_t sizePStateBlock = 0; + PstateSuperStructure pStateSupStruct; + memset( &pStateSupStruct, 0x00, sizeof(PstateSuperStructure) ); - FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset ); + //Building P-State Parameter block info by calling a HWP + FAPI_DBG("Generating P-State Parameter Block" ); + FAPI_EXEC_HWP(retCode, p9_pstate_parameter_block, i_procTgt, &pStateSupStruct); + FAPI_TRY(retCode); - uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); + //-------------------------- Local P-State Parameter Block ------------------------------ - FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset ); + uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); + uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; - uint32_t sizeAligned = 0; - uint32_t sizePStateBlock = 0; - PstateSuperStructure pStateSupStruct; - memset( &pStateSupStruct, 0x00, sizeof(PstateSuperStructure) ); + sizePStateBlock = sizeof(LocalPstateParmBlock); - //Building P-State Parameter block info by calling a HWP - FAPI_DBG("Generating P-State Parameter Block" ); - FAPI_EXEC_HWP(retCode, p9_pstate_parameter_block, i_procTgt, &pStateSupStruct); - FAPI_TRY(retCode); + FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); + memcpy( pLocalPState, &pStateSupStruct.localppb, sizePStateBlock ); - //-------------------------- Local P-State Parameter Block ------------------------------ + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + uint32_t localPStateBlock = sizeAligned; + FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); - uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); - uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; + pCmeHdr->g_cme_pstate_region_length = localPStateBlock; + pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock; - sizePStateBlock = sizeof(LocalPstateParmBlock); + //-------------------------- Local P-State Parameter Block Ends -------------------------- - FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); - memcpy( pLocalPState, &pStateSupStruct.localppb, sizePStateBlock ); + //-------------------------- Global P-State Parameter Block ------------------------------ - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - uint32_t localPStateBlock = sizeAligned; - FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); + FAPI_DBG("Copying Global P-State Parameter Block" ); + sizePStateBlock = sizeof(GlobalPstateParmBlock); - pCmeHdr->g_cme_pstate_region_length = localPStateBlock; - pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock; + // MAKE ASSERT + if (sizePStateBlock > PGPE_PSTATE_OUTPUT_TABLES_SIZE) + { + FAPI_ERR("GlobalPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", + sizePStateBlock, sizePStateBlock, + PGPE_PSTATE_OUTPUT_TABLES_SIZE, PGPE_PSTATE_OUTPUT_TABLES_SIZE); + } - //-------------------------- Local P-State Parameter Block Ends -------------------------- + FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset ); + memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &pStateSupStruct.globalppb, sizePStateBlock ); - //-------------------------- Global P-State Parameter Block ------------------------------ + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + FAPI_DBG("GPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); - FAPI_DBG("Copying Global P-State Parameter Block" ); - sizePStateBlock = sizeof(GlobalPstateParmBlock); + //Updating PPMR header info with GPSPB offset and length + io_ppmrHdr.g_ppmr_gppb_offset = ppmrRunningOffset; + io_ppmrHdr.g_ppmr_gppb_length = sizeAligned; - // MAKE ASSERT - if (sizePStateBlock > PGPE_PSTATE_OUTPUT_TABLES_SIZE) - { - FAPI_ERR("GlobalPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", - sizePStateBlock, sizePStateBlock, - PGPE_PSTATE_OUTPUT_TABLES_SIZE, PGPE_PSTATE_OUTPUT_TABLES_SIZE); - } + ppmrRunningOffset += sizeAligned; + pgpeRunningOffset += sizeAligned; + FAPI_DBG("OPPB pgpeRunningOffset 0x%08x OPPB ppmrRunningOffset 0x%08x", + pgpeRunningOffset, ppmrRunningOffset ); - FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset ); - memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &pStateSupStruct.globalppb, sizePStateBlock ); + //------------------------------ Global P-State Parameter Block Ends ---------------------- - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - FAPI_DBG("GPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); + //------------------------------ OCC P-State Parameter Block ------------------------------ - //Updating PPMR header info with GPSPB offset and length - io_ppmrHdr.g_ppmr_gppb_offset = ppmrRunningOffset; - io_ppmrHdr.g_ppmr_gppb_length = sizeAligned; + FAPI_INF("Copying OCC P-State Parameter Block" ); + sizePStateBlock = sizeof(OCCPstateParmBlock); + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - ppmrRunningOffset += sizeAligned; - pgpeRunningOffset += sizeAligned; - FAPI_DBG("OPPB pgpeRunningOffset 0x%08x OPPB ppmrRunningOffset 0x%08x", - pgpeRunningOffset, ppmrRunningOffset ); + FAPI_DBG("OPPB size 0x%08x (%d)", sizeAligned, sizeAligned ); + FAPI_DBG("OPSPB Actual size = 0x%08x (%d); After Alignment = 0x%08x (%d)", + sizePStateBlock, sizePStateBlock, + sizeAligned, sizeAligned ); - //------------------------------ Global P-State Parameter Block Ends ---------------------- + // MAKE ASSERT + if (sizePStateBlock > OCC_PSTATE_PARAM_BLOCK_SIZE) + { + FAPI_ERR("OCCPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", + sizePStateBlock, sizePStateBlock, + OCC_PSTATE_PARAM_BLOCK_SIZE, OCC_PSTATE_PARAM_BLOCK_SIZE); + } - //------------------------------ OCC P-State Parameter Block ------------------------------ + // The PPMR offset is from the begining --- which is the ppmrHeader + io_ppmrHdr.g_ppmr_oppb_offset = pPpmr->occParmBlock - pPpmr->ppmrHeader; + io_ppmrHdr.g_ppmr_oppb_length = sizeAligned; + FAPI_DBG("OPPB ppmrRunningOffset 0x%08x", io_ppmrHdr.g_ppmr_oppb_offset); - FAPI_INF("Copying OCC P-State Parameter Block" ); - sizePStateBlock = sizeof(OCCPstateParmBlock); - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + memcpy( &pPpmr->occParmBlock, &pStateSupStruct.occppb, sizePStateBlock ); + + //-------------------------- OCC P-State Parameter Block Ends ------------------------------ - FAPI_DBG("OPPB size 0x%08x (%d)", sizeAligned, sizeAligned ); - FAPI_DBG("OPSPB Actual size = 0x%08x (%d); After Alignment = 0x%08x (%d)", - sizePStateBlock, sizePStateBlock, - sizeAligned, sizeAligned ); - // MAKE ASSERT - if (sizePStateBlock > OCC_PSTATE_PARAM_BLOCK_SIZE) - { - FAPI_ERR("OCCPstateParmBlock exceeds allocation: size = %X (%d), allocation = %X (%d)", - sizePStateBlock, sizePStateBlock, - OCC_PSTATE_PARAM_BLOCK_SIZE, OCC_PSTATE_PARAM_BLOCK_SIZE); - } - // The PPMR offset is from the begining --- which is the ppmrHeader - io_ppmrHdr.g_ppmr_oppb_offset = pPpmr->occParmBlock - pPpmr->ppmrHeader; - io_ppmrHdr.g_ppmr_oppb_length = sizeAligned; - FAPI_DBG("OPPB ppmrRunningOffset 0x%08x", io_ppmrHdr.g_ppmr_oppb_offset); + io_ppmrHdr.g_ppmr_lppb_offset = CPMR_HOMER_OFFSET + CME_IMAGE_CPMR_OFFSET + localPspbStartIndex; + io_ppmrHdr.g_ppmr_lppb_length = + localPStateBlock; //FIXME RTC 159737 Need to clarify it from booting perspective - memcpy( &pPpmr->occParmBlock, &pStateSupStruct.occppb, sizePStateBlock ); - //-------------------------- OCC P-State Parameter Block Ends ------------------------------ + //------------------------------ OCC P-State Table Allocation ------------------------------ + // The PPMR offset is from the begining --- which is the ppmrHeader + io_ppmrHdr.g_ppmr_pstables_offset = pPpmr->pstateTable - pPpmr->ppmrHeader;; + io_ppmrHdr.g_ppmr_pstables_length = sizeof(GeneratedPstateInfo); + //------------------------------ OCC P-State Table Allocation Ends ------------------------- - io_ppmrHdr.g_ppmr_lppb_offset = CPMR_HOMER_OFFSET + CME_IMAGE_CPMR_OFFSET + localPspbStartIndex; - io_ppmrHdr.g_ppmr_lppb_length = - localPStateBlock; //FIXME RTC 159737 Need to clarify it from booting perspective + //------------------------------ Calculating total PGPE Image Size in SRAM ------------------------ - //------------------------------ OCC P-State Table Allocation ------------------------------ + io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length) + + io_ppmrHdr.g_ppmr_gppb_length; - // The PPMR offset is from the begining --- which is the ppmrHeader - io_ppmrHdr.g_ppmr_pstables_offset = pPpmr->pstateTable - pPpmr->ppmrHeader;; - io_ppmrHdr.g_ppmr_pstables_length = sizeof(GeneratedPstateInfo); + FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x", + pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size ); - //------------------------------ OCC P-State Table Allocation Ends ------------------------- + //Finally let us handle endianess + //CME Header + pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); + pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + + //PPMR Header + io_ppmrHdr.g_ppmr_magic_number = SWIZZLE_8_BYTE(PPMR_MAGIC_NUMBER); + io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset); + io_ppmrHdr.g_ppmr_gppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_length); + io_ppmrHdr.g_ppmr_oppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_offset); + io_ppmrHdr.g_ppmr_oppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_length); + io_ppmrHdr.g_ppmr_lppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_offset); + io_ppmrHdr.g_ppmr_lppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_length); + io_ppmrHdr.g_ppmr_pstables_offset = SWIZZLE_4_BYTE( io_ppmrHdr.g_ppmr_pstables_offset); + io_ppmrHdr.g_ppmr_pstables_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pstables_length); + io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pgpe_sram_img_size); + } + while(0); +fapi_try_exit: + FAPI_INF("buildParameterBlock exit"); - //------------------------------ Calculating total PGPE Image Size in SRAM ------------------------ + return fapi2::current_err; +} - io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length) + - io_ppmrHdr.g_ppmr_gppb_length; +//--------------------------------------------------------------------------- + +/** + * @brief copies override flavor of scan rings + * @param i_pImageIn points to start of hardware image. + * @param i_pOverride points to override rings. + * @param o_pImageOut points to HOMER image. + * @param i_ddLevel dd level associated with P9 chip. + * @param i_pBuf1 work buffer1 + * @param i_bufSize1 work buffer1 size. + * @param i_pBuf2 work buffer2 + * @param i_bufSize2 work buffer2 size. + * @param i_imgType image type to be built. + * @param o_qpmr temp instance of QpmrHeaderLayout_t + * @param i_platId platform associated with scan ring. + * @return IMG_BUILD_SUCCESS if successful else error code. + */ +uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + ImageType_t i_imgType, + RingBucket& io_cmeRings, + uint32_t& io_cmnRingSize ) +{ + FAPI_DBG( "> layoutCmnRingsForCme"); + uint32_t rc = IMG_BUILD_SUCCESS; - FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x", - pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size ); + do + { - //Finally let us handle endianess - //CME Header - pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); - pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + uint32_t tempSize = 0; + uint32_t ringSize = 0; + uint8_t* pRingStart = &i_pHomer->cpmrRegion.cmeSramRegion[io_cmnRingSize]; + uint16_t* pScanRingIndex = (uint16_t*) pRingStart; + uint8_t* pRingPayload = pRingStart + CORE_COMMON_RING_INDEX_SIZE; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - //PPMR Header - io_ppmrHdr.g_ppmr_magic_number = SWIZZLE_8_BYTE(PPMR_MAGIC_NUMBER); - io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset); - io_ppmrHdr.g_ppmr_gppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_length); - io_ppmrHdr.g_ppmr_oppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_offset); - io_ppmrHdr.g_ppmr_oppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_oppb_length); - io_ppmrHdr.g_ppmr_lppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_offset); - io_ppmrHdr.g_ppmr_lppb_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_lppb_length); - io_ppmrHdr.g_ppmr_pstables_offset = SWIZZLE_4_BYTE( io_ppmrHdr.g_ppmr_pstables_offset); - io_ppmrHdr.g_ppmr_pstables_length = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pstables_length); - io_ppmrHdr.g_ppmr_pgpe_sram_img_size = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_pgpe_sram_img_size); + if( !i_imgType.cmeCommonRingBuild ) + { + break; } - while(0); - fapi_try_exit: - FAPI_INF("buildParameterBlock exit"); + for( uint32_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; + ringIndex++ ) + { + ringSize = i_ringData.iv_sizeWorkBuf1; + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_CME, + i_chipState.getChipLevel(), + io_cmeRings.getCommonRingId( ringIndex ), + P9_TOR::CME, + i_ringVariant, + CORE0_CHIPLET_ID , + &i_ringData.iv_pWorkBuf1, + ringSize, + i_debugMode ); + + if( ( i_ringData.iv_sizeWorkBuf1 == ringSize ) || ( 0 == ringSize ) || + ( 0 != rc ) ) + { + FAPI_INF( "Did not find core common ring Id %d ", ringIndex ); + rc = 0; + ringSize = 0; + continue; + } - return fapi2::current_err; + ALIGN_DWORD(tempSize, ringSize) + ALIGN_RING_LOC( pRingStart, pRingPayload ); + + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, ringSize ); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart) + ringStartToHdrOffset); + + + io_cmeRings.setRingOffset( pRingPayload, io_cmeRings.getCommonRingId( ringIndex )); + io_cmeRings.setRingSize( io_cmeRings.getCommonRingId( ringIndex ), ringSize ); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, ringSize, io_cmeRings.getCommonRingId( ringIndex ) ); + + pRingPayload = pRingPayload + ringSize; + + //cleaning up what we wrote in temp buffer last time. + memset( i_ringData.iv_pWorkBuf1, 0x00, ringSize ); + } + + ringSize = (pRingPayload - pRingStart); + + if( ringSize > CORE_COMMON_RING_INDEX_SIZE ) + { + io_cmnRingSize += (pRingPayload - pRingStart); + ALIGN_DWORD(tempSize, io_cmnRingSize) + } } + while(0); -//--------------------------------------------------------------------------- + FAPI_DBG( "< layoutCmnRingsForCme"); - /** - * @brief copies override flavor of scan rings - * @param i_pImageIn points to start of hardware image. - * @param i_pOverride points to override rings. - * @param o_pImageOut points to HOMER image. - * @param i_ddLevel dd level associated with P9 chip. - * @param i_pBuf1 work buffer1 - * @param i_bufSize1 work buffer1 size. - * @param i_pBuf2 work buffer2 - * @param i_bufSize2 work buffer2 size. - * @param i_imgType image type to be built. - * @param o_qpmr temp instance of QpmrHeaderLayout_t - * @param i_platId platform associated with scan ring. - * @return IMG_BUILD_SUCCESS if successful else error code. - */ - uint32_t layoutCmnRingsForCme( Homerlayout_t* i_pHomer, + return rc; +} + +//------------------------------------------------------------------------------ +/** + * @brief creates a lean scan ring layout for core specific rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData scan ring related data + * @param i_debugMode debug type set for scan rings + * @param i_ringVariant scan ring flavor + * @param i_imgType image type to be built + * @param io_cmeRings instance of RingBucket + * @param io_ringLength input: CME region length populated. Output: Max possible size of instance spec ring + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ + +uint32_t layoutInstRingsForCme( Homerlayout_t* i_pHomer, const P9FuncModel& i_chipState, RingBufData& i_ringData, RingDebugMode_t i_debugMode, RingVariant_t i_ringVariant, ImageType_t i_imgType, RingBucket& io_cmeRings, - uint32_t& io_cmnRingSize ) + uint32_t& io_ringLength ) +{ + FAPI_DBG( "> layoutInstRingsForCme"); + uint32_t rc = IMG_BUILD_SUCCESS; + // Let us find out ring-pair which is biggest in list of 12 ring pairs + uint32_t maxCoreSpecRingLength = 0; + uint32_t ringLength = 0; + uint32_t tempSize = 0; + uint32_t tempRepairLength = 0; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + do { - FAPI_DBG( "> layoutCmnRingsForCme"); - uint32_t rc = IMG_BUILD_SUCCESS; - - do + if( !i_imgType.cmeCoreSpecificRingBuild ) { + break; + } - uint32_t tempSize = 0; - uint32_t ringSize = 0; - uint8_t* pRingStart = &i_pHomer->cpmrRegion.cmeSramRegion[io_cmnRingSize]; - uint16_t* pScanRingIndex = (uint16_t*) pRingStart; - uint8_t* pRingPayload = pRingStart + CORE_COMMON_RING_INDEX_SIZE; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - - if( !i_imgType.cmeCommonRingBuild ) + for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) + { + if( !i_chipState.isExFunctional( exId ) ) { - break; + FAPI_DBG( "ignoring ex %d for instance ring size consideration", exId); + continue; } - for( uint32_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; - ringIndex++ ) + ringLength = 0; + + for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) { - ringSize = i_ringData.iv_sizeWorkBuf1; + if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) + { + FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); + continue; + } + + tempSize = i_ringData.iv_sizeWorkBuf1; rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_CME, i_chipState.getChipLevel(), - io_cmeRings.getCommonRingId( ringIndex ), + io_cmeRings.getInstRingId(0), P9_TOR::CME, i_ringVariant, - CORE0_CHIPLET_ID , + CORE0_CHIPLET_ID + ((2 * exId) + coreId), &i_ringData.iv_pWorkBuf1, - ringSize, + tempSize, i_debugMode ); - if( ( i_ringData.iv_sizeWorkBuf1 == ringSize ) || ( 0 == ringSize ) || + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || ( 0 != rc ) ) { - FAPI_INF( "Did not find core common ring Id %d ", ringIndex ); - rc = 0; - ringSize = 0; + FAPI_DBG( "could not determine size of ring id %d of core %d", + io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); continue; } - ALIGN_DWORD(tempSize, ringSize) - ALIGN_RING_LOC( pRingStart, pRingPayload ); - - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, ringSize ); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pRingPayload - pRingStart) + ringStartToHdrOffset); - - - io_cmeRings.setRingOffset( pRingPayload, io_cmeRings.getCommonRingId( ringIndex )); - io_cmeRings.setRingSize( io_cmeRings.getCommonRingId( ringIndex ), ringSize ); - io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, ringSize, io_cmeRings.getCommonRingId( ringIndex ) ); - - pRingPayload = pRingPayload + ringSize; - - //cleaning up what we wrote in temp buffer last time. - memset( i_ringData.iv_pWorkBuf1, 0x00, ringSize ); + ALIGN_DWORD(tempRepairLength, tempSize); + ringLength += tempSize; } - ringSize = (pRingPayload - pRingStart); + maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; + } - if( ringSize > CORE_COMMON_RING_INDEX_SIZE ) - { - io_cmnRingSize += (pRingPayload - pRingStart); - ALIGN_DWORD(tempSize, io_cmnRingSize) - } + if( maxCoreSpecRingLength > 0 ) + { + maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); + ROUND_OFF_32B(maxCoreSpecRingLength); } - while(0); - FAPI_DBG( "< layoutCmnRingsForCme"); + FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); + // Let us copy the rings now. - return rc; - } + uint8_t* pRingStart = NULL; + uint8_t* pRingPayload = NULL; + uint16_t* pScanRingIndex = NULL; -//------------------------------------------------------------------------------ - /** - * @brief creates a lean scan ring layout for core specific rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData scan ring related data - * @param i_debugMode debug type set for scan rings - * @param i_ringVariant scan ring flavor - * @param i_imgType image type to be built - * @param io_cmeRings instance of RingBucket - * @param io_ringLength input: CME region length populated. Output: Max possible size of instance spec ring - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - - uint32_t layoutInstRingsForCme( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - ImageType_t i_imgType, - RingBucket& io_cmeRings, - uint32_t& io_ringLength ) - { - FAPI_DBG( "> layoutInstRingsForCme"); - uint32_t rc = IMG_BUILD_SUCCESS; - // Let us find out ring-pair which is biggest in list of 12 ring pairs - uint32_t maxCoreSpecRingLength = 0; - uint32_t ringLength = 0; - uint32_t tempSize = 0; - uint32_t tempRepairLength = 0; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - - do + for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) { - if( !i_imgType.cmeCoreSpecificRingBuild ) + pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); + pScanRingIndex = (uint16_t*)pRingStart; + + if( !i_chipState.isExFunctional( exId ) ) { - break; + FAPI_DBG("skipping copy of core specific rings of ex %d", exId); + continue; } - for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) + for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) { - if( !i_chipState.isExFunctional( exId ) ) + if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) { - FAPI_DBG( "ignoring ex %d for instance ring size consideration", exId); + FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); continue; } - ringLength = 0; + tempSize = i_ringData.iv_sizeWorkBuf1; + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_CME, + i_chipState.getChipLevel(), + io_cmeRings.getInstRingId(0), + P9_TOR::CME, + i_ringVariant, + CORE0_CHIPLET_ID + ((2 * exId) + coreId), + &i_ringData.iv_pWorkBuf1, + tempSize, + i_debugMode ); - for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) + if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || + ( 0 != rc ) ) { - if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) - { - FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); - continue; - } - - tempSize = i_ringData.iv_sizeWorkBuf1; - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_CME, - i_chipState.getChipLevel(), - io_cmeRings.getInstRingId(0), - P9_TOR::CME, - i_ringVariant, - CORE0_CHIPLET_ID + ((2 * exId) + coreId), - &i_ringData.iv_pWorkBuf1, - tempSize, - i_debugMode ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || - ( 0 != rc ) ) - { - FAPI_DBG( "could not determine size of ring id %d of core %d", - io_cmeRings.getInstRingId(0), ((2 * exId) + coreId) ); - continue; - } - - ALIGN_DWORD(tempRepairLength, tempSize); - ringLength += tempSize; + FAPI_INF("Instance ring Id %d not found for EX %d core %d", + io_cmeRings.getInstRingId(0), exId, coreId ); + rc = 0; + tempSize = 0; + continue; } - maxCoreSpecRingLength = ringLength > maxCoreSpecRingLength ? ringLength : maxCoreSpecRingLength; - } + ALIGN_RING_LOC( pRingStart, pRingPayload ); + memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempSize); + io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, tempSize, io_cmeRings.getInstRingId(0) ); + io_cmeRings.setRingOffset( pRingPayload, + io_cmeRings.getInstRingId(0), + ( MAX_CORES_PER_EX * exId ) + coreId ); + *(pScanRingIndex + coreId) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + ringStartToHdrOffset); - if( maxCoreSpecRingLength > 0 ) - { - maxCoreSpecRingLength += sizeof(CoreSpecRingList_t); - ROUND_OFF_32B(maxCoreSpecRingLength); + pRingPayload = pRingPayload + tempSize; + io_cmeRings.setRingSize( io_cmeRings.getInstRingId(0), tempSize, ((MAX_CORES_PER_EX * exId) + coreId) ); + + //cleaning up what we wrote in temp buffer last time. + memset( i_ringData.iv_pWorkBuf1, 0x00, tempSize ); } + } - FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); - // Let us copy the rings now. + io_ringLength = maxCoreSpecRingLength; + } + while(0); - uint8_t* pRingStart = NULL; - uint8_t* pRingPayload = NULL; - uint16_t* pScanRingIndex = NULL; + FAPI_DBG( "< layoutInstRingsForCme"); - for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) - { - pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; - pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); - pScanRingIndex = (uint16_t*)pRingStart; + return rc; +} - if( !i_chipState.isExFunctional( exId ) ) - { - FAPI_DBG("skipping copy of core specific rings of ex %d", exId); - continue; - } +//------------------------------------------------------------------------------ - for( uint32_t coreId = 0; coreId < MAX_CORES_PER_EX; coreId++ ) - { - if( !i_chipState.isCoreFunctional( ((2 * exId ) + coreId)) ) - { - FAPI_DBG( "ignoring core %d for instance ring size consideration", (2 * exId ) + coreId ); - continue; - } - - tempSize = i_ringData.iv_sizeWorkBuf1; - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_CME, - i_chipState.getChipLevel(), - io_cmeRings.getInstRingId(0), - P9_TOR::CME, - i_ringVariant, - CORE0_CHIPLET_ID + ((2 * exId) + coreId), - &i_ringData.iv_pWorkBuf1, - tempSize, - i_debugMode ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempSize) || (0 == tempSize ) || - ( 0 != rc ) ) - { - FAPI_INF("Instance ring Id %d not found for EX %d core %d", - io_cmeRings.getInstRingId(0), exId, coreId ); - rc = 0; - tempSize = 0; - continue; - } - - ALIGN_RING_LOC( pRingStart, pRingPayload ); - memcpy( pRingPayload, i_ringData.iv_pWorkBuf1, tempSize); - io_cmeRings.extractRing( i_ringData.iv_pWorkBuf1, tempSize, io_cmeRings.getInstRingId(0) ); - io_cmeRings.setRingOffset( pRingPayload, - io_cmeRings.getInstRingId(0), - ( MAX_CORES_PER_EX * exId ) + coreId ); - *(pScanRingIndex + coreId) = SWIZZLE_2_BYTE((pRingPayload - pRingStart ) + ringStartToHdrOffset); - - pRingPayload = pRingPayload + tempSize; - io_cmeRings.setRingSize( io_cmeRings.getInstRingId(0), tempSize, ((MAX_CORES_PER_EX * exId) + coreId) ); - - //cleaning up what we wrote in temp buffer last time. - memset( i_ringData.iv_pWorkBuf1, 0x00, tempSize ); - } - } +uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + ImageType_t i_imgType, + uint32_t& io_ovrdRingLength ) +{ + FAPI_INF("> layoutCmeScanOverride" ); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t tempRingLength = io_ovrdRingLength; + uint32_t tempBufSize = 0; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + RingBucket cmeOvrdRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); - io_ringLength = maxCoreSpecRingLength; + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; } - while(0); - FAPI_DBG( "< layoutInstRingsForCme"); + //Start override ring from the actual end of base common rings. Remember overrides reside within + //common rings region + uint8_t* pOverrideStart = &i_pHomer->cpmrRegion.cmeSramRegion[tempRingLength]; + uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; - return rc; - } + //get core common rings + uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; + bool overrideNotFound = true; -//------------------------------------------------------------------------------ + for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; + ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf2; - uint32_t layoutCmeScanOverride( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - ImageType_t i_imgType, - uint32_t& io_ovrdRingLength ) - { - FAPI_INF("> layoutCmeScanOverride" ); - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t tempRingLength = io_ovrdRingLength; - uint32_t tempBufSize = 0; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); + rc = tor_get_single_ring( i_pOverride, + P9_XIP_MAGIC_SEEPROM, + i_chipState.getChipLevel(), + cmeOvrdRings.getCommonRingId( ringIndex ), + P9_TOR::SBE, + OVERRIDE, + CORE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf2, + tempBufSize, + i_debugMode ); - RingBucket cmeOvrdRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); + if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) - do - { - if( !i_imgType.cmeCommonRingBuild ) { - break; + tempBufSize = 0; + continue; } - //Start override ring from the actual end of base common rings. Remember overrides reside within - //common rings region - uint8_t* pOverrideStart = &i_pHomer->cpmrRegion.cmeSramRegion[tempRingLength]; - uint16_t* pScanRingIndex = (uint16_t*)pOverrideStart; + overrideNotFound = false; + ALIGN_DWORD(tempRingLength, tempBufSize) + ALIGN_RING_LOC( pOverrideStart, pOverrideRingPayload ); - //get core common rings - uint8_t* pOverrideRingPayload = pOverrideStart + CORE_COMMON_RING_INDEX_SIZE; - bool overrideNotFound = true; + memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); + *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + ringStartToHdrOffset); - for( uint8_t ringIndex = 0; ringIndex < EC::g_ecData.iv_num_common_rings; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf2; + cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); + cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); + cmeOvrdRings.extractRing( i_ringData.iv_pWorkBuf2, tempBufSize, cmeOvrdRings.getCommonRingId( ringIndex ) ); - FAPI_DBG("Calling P9_TOR::tor_get_single_ring ring 0x%08X", ringIndex); - rc = tor_get_single_ring( i_pOverride, - P9_XIP_MAGIC_SEEPROM, - i_chipState.getChipLevel(), - cmeOvrdRings.getCommonRingId( ringIndex ), - P9_TOR::SBE, - OVERRIDE, - CORE0_CHIPLET_ID, - &i_ringData.iv_pWorkBuf2, - tempBufSize, - i_debugMode ); + pOverrideRingPayload = pOverrideRingPayload + tempBufSize; - if( (i_ringData.iv_sizeWorkBuf2 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) + //cleaning up what we wrote in temp bufffer last time. + memset( i_ringData.iv_pWorkBuf2, 0x00, tempBufSize ); + } - { - tempBufSize = 0; - continue; - } + if( overrideNotFound ) + { + FAPI_INF("Overrides not found for CME"); + rc = BUILD_FAIL_OVERRIDE; // Not considered an error + break; + } - overrideNotFound = false; - ALIGN_DWORD(tempRingLength, tempBufSize) - ALIGN_RING_LOC( pOverrideStart, pOverrideRingPayload ); + io_ovrdRingLength += (pOverrideRingPayload - pOverrideStart ); + ALIGN_DWORD(tempRingLength, io_ovrdRingLength) - memcpy( pOverrideRingPayload, i_ringData.iv_pWorkBuf2, tempBufSize); - *(pScanRingIndex + ringIndex) = SWIZZLE_2_BYTE((pOverrideRingPayload - pOverrideStart) + ringStartToHdrOffset); + FAPI_DBG( "Override Ring Length 0x%08X", io_ovrdRingLength ); + } + while(0); - cmeOvrdRings.setRingOffset(pOverrideRingPayload, cmeOvrdRings.getCommonRingId( ringIndex )); - cmeOvrdRings.setRingSize( cmeOvrdRings.getCommonRingId( ringIndex ), tempBufSize ); - cmeOvrdRings.extractRing( i_ringData.iv_pWorkBuf2, tempBufSize, cmeOvrdRings.getCommonRingId( ringIndex ) ); + cmeOvrdRings.dumpOverrideRings(); - pOverrideRingPayload = pOverrideRingPayload + tempBufSize; + FAPI_INF("< layoutCmeScanOverride" ); + return rc; +} - //cleaning up what we wrote in temp bufffer last time. - memset( i_ringData.iv_pWorkBuf2, 0x00, tempBufSize ); - } +//------------------------------------------------------------------------------ - if( overrideNotFound ) +/** + * @brief creates a lean scan ring layout for core rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData processor target + * @param i_debugMode debug mode type for scan rings + * @param i_riskLevel IPL type + * @param i_imgType image type to be built + * @param i_pOverride points to override binary. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + ImageType_t i_imgType, + void* i_pOverride ) +{ + FAPI_DBG( "> layoutRingsForCME"); + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t ringLength = 0; + uint32_t tempLength = 0; + RingVariant_t l_ringVariant = BASE; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + RingBucket cmeRings( PLAT_CME, + (uint8_t*)&i_pHomer->cpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.cmeCommonRingBuild ) + { + break; + } + + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) + { + l_ringVariant = RL; + } + + ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( + pCmeHdr->g_cme_pstate_region_length); + //save the length where hcode ends + tempLength = ringLength; + + layoutCmnRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + i_imgType, + cmeRings, + ringLength ); + + if( i_pOverride ) + { + uint32_t temp = 0; + uint32_t tempRc = 0; + ALIGN_DWORD( temp, ringLength ); + temp = ringLength; + + tempRc = layoutCmeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + i_imgType, + ringLength ); + + if( BUILD_FAIL_OVERRIDE == tempRc ) { - FAPI_INF("Overrides not found for CME"); - rc = BUILD_FAIL_OVERRIDE; // Not considered an error - break; + //found no core overrides + pCmeHdr->g_cme_cmn_ring_ovrd_offset = 0; } + else + { + pCmeHdr->g_cme_cmn_ring_ovrd_offset = temp; + } + } - io_ovrdRingLength += (pOverrideRingPayload - pOverrideStart ); - ALIGN_DWORD(tempRingLength, io_ovrdRingLength) + pCmeHdr->g_cme_common_ring_length = ringLength - tempLength; //cmn ring end - hcode end - FAPI_DBG( "Override Ring Length 0x%08X", io_ovrdRingLength ); + if( !pCmeHdr->g_cme_common_ring_length ) + { + //No common ring , so force offset to be 0 + pCmeHdr->g_cme_common_ring_offset = 0; } - while(0); - cmeOvrdRings.dumpOverrideRings(); + tempLength = ringLength; + tempLength = (( tempLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT ); //multiple of 32B + ringLength = tempLength << CME_BLK_SIZE_SHIFT; //start position of instance rings - FAPI_INF("< layoutCmeScanOverride" ); - return rc; - } + layoutInstRingsForCme( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + BASE, // VPD rings are always BASE + i_imgType, + cmeRings, + ringLength ); -//------------------------------------------------------------------------------ + if( ringLength ) + { + pCmeHdr->g_cme_max_spec_ring_length = + ( ringLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; + pCmeHdr->g_cme_core_spec_ring_offset = tempLength; + } - /** - * @brief creates a lean scan ring layout for core rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData processor target - * @param i_debugMode debug mode type for scan rings - * @param i_riskLevel IPL type - * @param i_imgType image type to be built - * @param i_pOverride points to override binary. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutRingsForCME( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - ImageType_t i_imgType, - void* i_pOverride ) - { - FAPI_DBG( "> layoutRingsForCME"); - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t ringLength = 0; - uint32_t tempLength = 0; - RingVariant_t l_ringVariant = BASE; - cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - RingBucket cmeRings( PLAT_CME, - (uint8_t*)&i_pHomer->cpmrRegion, - i_debugMode ); + //Let us handle endianess now + pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); + pCmeHdr->g_cme_core_spec_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset); + pCmeHdr->g_cme_max_spec_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); + pCmeHdr->g_cme_cmn_ring_ovrd_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset); + } + while(0); - do - { - if( !i_imgType.cmeCommonRingBuild ) - { - break; - } + cmeRings.dumpRings(); + FAPI_DBG("CME Header Ring Details "); + FAPI_DBG( "PS Offset %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); + FAPI_DBG("PS Lengtrh %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) ); + FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); + FAPI_DBG("Common Ring Length %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); + FAPI_DBG("Instance Ring Offset / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), + SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); + FAPI_DBG("Instance Ring Length / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } + SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); - ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( - pCmeHdr->g_cme_pstate_region_length); - //save the length where hcode ends - tempLength = ringLength; - - layoutCmnRingsForCme( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - l_ringVariant, - i_imgType, - cmeRings, - ringLength ); - - if( i_pOverride ) - { - uint32_t temp = 0; - uint32_t tempRc = 0; - ALIGN_DWORD( temp, ringLength ); - temp = ringLength; - - tempRc = layoutCmeScanOverride( i_pHomer, - i_pOverride, - i_chipState, - i_ringData, - i_debugMode, - i_imgType, - ringLength ); - - if( BUILD_FAIL_OVERRIDE == tempRc ) - { - //found no core overrides - pCmeHdr->g_cme_cmn_ring_ovrd_offset = 0; - } - else - { - pCmeHdr->g_cme_cmn_ring_ovrd_offset = temp; - } - } + FAPI_DBG( "< layoutRingsForCME"); - pCmeHdr->g_cme_common_ring_length = ringLength - tempLength; //cmn ring end - hcode end + return rc; +} - if( !pCmeHdr->g_cme_common_ring_length ) - { - //No common ring , so force offset to be 0 - pCmeHdr->g_cme_common_ring_offset = 0; - } - tempLength = ringLength; - tempLength = (( tempLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT ); //multiple of 32B - ringLength = tempLength << CME_BLK_SIZE_SHIFT; //start position of instance rings +//------------------------------------------------------------------------------ - layoutInstRingsForCme( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - BASE, // VPD rings are always BASE - i_imgType, - cmeRings, - ringLength ); +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) +{ + FAPI_DBG("> layoutCmnRingsForSgpe"); + + uint32_t rc = IMG_BUILD_SUCCESS; + uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); + uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + + QUAD_COMMON_RING_INDEX_SIZE];; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; + uint32_t ringIndex = 0; + uint32_t tempLength = 0; + uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + + RingBucket sgpeRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do + { + if( !i_imgType.sgpeCommonRingBuild ) + { + break; + } - if( ringLength ) - { - pCmeHdr->g_cme_max_spec_ring_length = - ( ringLength + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT; - pCmeHdr->g_cme_core_spec_ring_offset = tempLength; - } + //get core common rings + for( ; ringIndex < EQ::g_eqData.iv_num_common_rings; ringIndex++ ) + { + tempBufSize = i_ringData.iv_sizeWorkBuf1; + + rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, + P9_XIP_MAGIC_SGPE, + i_chipState.getChipLevel(), + io_sgpeRings.getCommonRingId( ringIndex ), + P9_TOR::SGPE, + i_ringVariant, + CACHE0_CHIPLET_ID, + &i_ringData.iv_pWorkBuf1, + tempBufSize, + i_debugMode ); + + if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || + ( 0 != rc ) ) + { + FAPI_INF( "did not find quad common ring %d", ringIndex ); + rc = IMG_BUILD_SUCCESS; + tempBufSize = 0; + continue; + } + + ALIGN_DWORD(tempLength, tempBufSize) + ALIGN_RING_LOC( pRingStart, pCmnRingPayload ); + + memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pCmnRingPayload - pRingStart ) + ringStartToHdrOffset); + io_sgpeRings.setRingSize( io_sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getCommonRingId( ringIndex ) ); + pCmnRingPayload = pCmnRingPayload + tempBufSize; + + //cleaning up what we wrote in temp buffer last time. + memset( i_ringData.iv_pWorkBuf1, 0x00, tempBufSize ); + + }//for common rings + + tempLength = pCmnRingPayload - pRingStart; + io_qpmrHdr.quadCommonRingLength = tempLength; + io_qpmrHdr.quadCommonRingOffset = i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage - + (uint8_t*)&i_pHomer->qpmrRegion; + io_qpmrHdr.quadCommonRingOffset += sgpeHcodeSize; + FAPI_DBG("Quad Cmn Ring Length 0x%08X", io_qpmrHdr.quadCommonRingLength ); - //Let us handle endianess now - pCmeHdr->g_cme_common_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); - pCmeHdr->g_cme_core_spec_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset); - pCmeHdr->g_cme_max_spec_ring_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_cmn_ring_ovrd_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_cmn_ring_ovrd_offset); - } - while(0); - - cmeRings.dumpRings(); - FAPI_DBG("CME Header Ring Details "); - FAPI_DBG( "PS Offset %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset)); - FAPI_DBG("PS Lengtrh %d (0x%08X)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) ); - FAPI_DBG("Common Ring Offset %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset)); - FAPI_DBG("Common Ring Length %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); - FAPI_DBG("Instance Ring Offset / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset), - SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); - FAPI_DBG("Instance Ring Length / 32 %d (0x%08X) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length), - - SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length)); - - FAPI_DBG( "< layoutRingsForCME"); - - return rc; } + while(0); //building common rings + + FAPI_DBG("< layoutCmnRingsForSgpe"); + return rc; +} //------------------------------------------------------------------------------ - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_ringVariant variant of the scan ring to be copied. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param io_sgpeRings stores position and length of all quad common rings. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType, - RingBucket& io_sgpeRings ) +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_ringVariant variant of the scan ring to be copied. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param io_sgpeRings stores position and length of all quad common rings. + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + RingVariant_t i_ringVariant, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType, + RingBucket& io_sgpeRings ) +{ + uint32_t rc = IMG_BUILD_SUCCESS; + + do { - FAPI_DBG("> layoutCmnRingsForSgpe"); + if( !i_imgType.sgpeCacheSpecificRingBuild ) + { + break; + } - uint32_t rc = IMG_BUILD_SUCCESS; - uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); - uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + - QUAD_COMMON_RING_INDEX_SIZE];; - uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; - uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize]; - uint32_t ringIndex = 0; - uint32_t tempLength = 0; - uint32_t tempBufSize = i_ringData.iv_sizeWorkBuf1; + uint32_t quadSpecRingStart = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength; + uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart ]; + uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[quadSpecRingStart]; + uint8_t* instRingPayLoad = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart + + QUAD_SPEC_RING_INDEX_LEN ]; uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; - RingBucket sgpeRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); - - do + for( uint32_t cacheInst = 0; cacheInst < MAX_QUADS_PER_CHIP; cacheInst++ ) { - if( !i_imgType.sgpeCommonRingBuild ) + if( !i_chipState.isQuadFunctional( cacheInst ) ) { - break; + pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index + //Quad is not functional. Don't populate rings. Ring Index will be zero by design + FAPI_INF("Skipping copy of cache chiplet%d", cacheInst); + continue; } - //get core common rings - for( ; ringIndex < EQ::g_eqData.iv_num_common_rings; ringIndex++ ) + ExIdMap ExChipletRingMap; + uint32_t chipletId = 0; + uint32_t tempBufSize = 0; + uint32_t tempLength = 0; + + for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; + ringIndex++ ) { tempBufSize = i_ringData.iv_sizeWorkBuf1; + chipletId = ExChipletRingMap.getInstanceId( CACHE0_CHIPLET_ID + cacheInst , ringIndex ); rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, P9_XIP_MAGIC_SGPE, i_chipState.getChipLevel(), - io_sgpeRings.getCommonRingId( ringIndex ), + io_sgpeRings.getInstRingId( ringIndex ), P9_TOR::SGPE, i_ringVariant, - CACHE0_CHIPLET_ID, + chipletId, &i_ringData.iv_pWorkBuf1, tempBufSize, i_debugMode ); @@ -2492,1031 +2598,990 @@ extern "C" if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || ( 0 != rc ) ) { - FAPI_INF( "did not find quad common ring %d", ringIndex ); - rc = IMG_BUILD_SUCCESS; + FAPI_DBG( "did not find quad spec ring %d for cache Inst %d", ringIndex , cacheInst ); + rc = 0; tempBufSize = 0; continue; } ALIGN_DWORD(tempLength, tempBufSize) - ALIGN_RING_LOC( pRingStart, pCmnRingPayload ); + ALIGN_RING_LOC( pRingStart, instRingPayLoad ); - memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); - io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((pCmnRingPayload - pRingStart ) + ringStartToHdrOffset); - io_sgpeRings.setRingSize( io_sgpeRings.getCommonRingId( ringIndex ), tempBufSize ); - io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getCommonRingId( ringIndex ) ); - pCmnRingPayload = pCmnRingPayload + tempBufSize; + memcpy( instRingPayLoad, i_ringData.iv_pWorkBuf1, tempBufSize); + io_sgpeRings.setRingOffset( instRingPayLoad, io_sgpeRings.getInstRingId( ringIndex ), chipletId ); + *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((instRingPayLoad - pRingStart ) + ringStartToHdrOffset); + io_sgpeRings.setRingSize( io_sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); + instRingPayLoad = instRingPayLoad + tempBufSize; + io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getInstRingId( ringIndex ) ); //cleaning up what we wrote in temp buffer last time. memset( i_ringData.iv_pWorkBuf1, 0x00, tempBufSize ); - }//for common rings - - tempLength = pCmnRingPayload - pRingStart; - io_qpmrHdr.quadCommonRingLength = tempLength; - io_qpmrHdr.quadCommonRingOffset = i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage - - (uint8_t*)&i_pHomer->qpmrRegion; - io_qpmrHdr.quadCommonRingOffset += sgpeHcodeSize; - FAPI_DBG("Quad Cmn Ring Length 0x%08X", io_qpmrHdr.quadCommonRingLength ); + }//for quad spec rings + pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index } - while(0); //building common rings - FAPI_DBG("< layoutCmnRingsForSgpe"); - - return rc; + io_qpmrHdr.quadSpecRingOffset = io_qpmrHdr.quadCommonRingOffset + io_qpmrHdr.quadCommonRingLength; + io_qpmrHdr.quadSpecRingLength = (instRingPayLoad - pRingStart); + FAPI_DBG("Instance Ring Length 0x%08X", io_qpmrHdr.quadSpecRingLength); } + while(0); + + return rc; +} //------------------------------------------------------------------------------ - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_ringVariant variant of the scan ring to be copied. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param io_sgpeRings stores position and length of all quad common rings. - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutInstRingsForSgpe( Homerlayout_t* i_pHomer, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - RingVariant_t i_ringVariant, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType, - RingBucket& io_sgpeRings ) +/** + * @brief creates a scan ring layout for quad common rings in HOMER. + * @param i_pHOMER points to HOMER image. + * @param i_chipState functional state of all cores within P9 chip + * @param i_ringData contains ring buffers and respective sizes + * @param i_debugMode scan ring debug state + * @param i_riskLevel true if system IPL is in risk level mode else false. + * @param io_qpmrHdr instance of QPMR header. + * @param i_imgType image type to be built + * @param IMG_BUILD_SUCCESS if function succeeds else error code. + */ +uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, + void* i_pOverride, + const P9FuncModel& i_chipState, + RingBufData& i_ringData, + RingDebugMode_t i_debugMode, + uint32_t i_riskLevel, + QpmrHeaderLayout_t& io_qpmrHdr, + ImageType_t i_imgType ) +{ + FAPI_DBG( "> layoutRingsForSGPE"); + uint32_t rc = IMG_BUILD_SUCCESS; + RingVariant_t l_ringVariant = BASE; + sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + RingBucket sgpeRings( PLAT_SGPE, + (uint8_t*)&i_pHomer->qpmrRegion, + i_debugMode ); + + do { - uint32_t rc = IMG_BUILD_SUCCESS; - do + // get all the rings pertaining to CME in a work buffer first. + if( i_riskLevel ) { - if( !i_imgType.sgpeCacheSpecificRingBuild ) - { - break; - } + l_ringVariant = RL; + } - uint32_t quadSpecRingStart = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength; - uint16_t* pCmnRingIndex = (uint16_t*)&i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart ]; - uint8_t* pRingStart = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[quadSpecRingStart]; - uint8_t* instRingPayLoad = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[ quadSpecRingStart + - QUAD_SPEC_RING_INDEX_LEN ]; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == P9_TOR::tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + //Manage the Quad Common rings in HOMER + layoutCmnRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + l_ringVariant, + io_qpmrHdr, + i_imgType, + sgpeRings ); + + //Manage the Quad Override rings in HOMER + layoutSgpeScanOverride( i_pHomer, + i_pOverride, + i_chipState, + i_ringData, + i_debugMode, + io_qpmrHdr, + i_imgType ); + + //Manage the Quad specific rings in HOMER + layoutInstRingsForSgpe( i_pHomer, + i_chipState, + i_ringData, + i_debugMode, + BASE, // VPD rings are always BASE + io_qpmrHdr, + i_imgType, + sgpeRings ); + + if( 0 == io_qpmrHdr.quadCommonRingLength ) + { + //If quad common rings don't exist ensure its offset in image header is zero + pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset = 0; + } - for( uint32_t cacheInst = 0; cacheInst < MAX_QUADS_PER_CHIP; cacheInst++ ) - { - if( !i_chipState.isQuadFunctional( cacheInst ) ) - { - pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index - //Quad is not functional. Don't populate rings. Ring Index will be zero by design - FAPI_INF("Skipping copy of cache chiplet%d", cacheInst); - continue; - } + if( io_qpmrHdr.quadSpecRingLength > 0 ) + { + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = io_qpmrHdr.quadCommonRingLength + + SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); + pSgpeImgHdr->g_sgpe_scom_offset = + SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength + + io_qpmrHdr.quadSpecRingLength; + } + } + while(0); //building instance rings + + //Let us handle endianes at last + io_qpmrHdr.quadCommonRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingOffset); + io_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength); + io_qpmrHdr.quadCommonOvrdOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdOffset); + io_qpmrHdr.quadCommonOvrdLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdLength); + io_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingOffset); + io_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); + pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); + pSgpeImgHdr->g_sgpe_scom_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_scom_offset); + sgpeRings.dumpRings(); + + FAPI_DBG("SGPE Header Ring Details "); + FAPI_DBG("Common Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); + FAPI_DBG("Instance Ring Offset %d (0x%08X) ", + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), + SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); + + + return rc; +} +//--------------------------------------------------------------------------- +/** + * @brief updates the IVPR attributes for SGPE, PGPE. + * @brief i_pChipHomer points to start of HOMER + */ +fapi2::ReturnCode updateGpeAttributes( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ + QpmrHeaderLayout_t* pQpmrHdr = (QpmrHeaderLayout_t*)i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader; + PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) i_pChipHomer->ppmrRegion.ppmrHeader; - ExIdMap ExChipletRingMap; - uint32_t chipletId = 0; - uint32_t tempBufSize = 0; - uint32_t tempLength = 0; + uint32_t attrVal = SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset); + attrVal |= (0x80000000 | ONE_MB); - for( uint32_t ringIndex = 0; ringIndex < EQ::g_eqData.iv_num_instance_rings_scan_addrs; - ringIndex++ ) - { - tempBufSize = i_ringData.iv_sizeWorkBuf1; - chipletId = ExChipletRingMap.getInstanceId( CACHE0_CHIPLET_ID + cacheInst , ringIndex ); - - rc = tor_get_single_ring( i_ringData.iv_pRingBuffer, - P9_XIP_MAGIC_SGPE, - i_chipState.getChipLevel(), - io_sgpeRings.getInstRingId( ringIndex ), - P9_TOR::SGPE, - i_ringVariant, - chipletId, - &i_ringData.iv_pWorkBuf1, - tempBufSize, - i_debugMode ); - - if( (i_ringData.iv_sizeWorkBuf1 == tempBufSize) || (0 == tempBufSize ) || - ( 0 != rc ) ) - { - FAPI_DBG( "did not find quad spec ring %d for cache Inst %d", ringIndex , cacheInst ); - rc = 0; - tempBufSize = 0; - continue; - } - - ALIGN_DWORD(tempLength, tempBufSize) - ALIGN_RING_LOC( pRingStart, instRingPayLoad ); - - memcpy( instRingPayLoad, i_ringData.iv_pWorkBuf1, tempBufSize); - io_sgpeRings.setRingOffset( instRingPayLoad, io_sgpeRings.getInstRingId( ringIndex ), chipletId ); - *(pCmnRingIndex + ringIndex) = SWIZZLE_2_BYTE((instRingPayLoad - pRingStart ) + ringStartToHdrOffset); - io_sgpeRings.setRingSize( io_sgpeRings.getInstRingId( ringIndex ), tempBufSize, chipletId ); - instRingPayLoad = instRingPayLoad + tempBufSize; - io_sgpeRings.extractRing( i_ringData.iv_pWorkBuf1, tempBufSize, io_sgpeRings.getInstRingId( ringIndex ) ); - - //cleaning up what we wrote in temp buffer last time. - memset( i_ringData.iv_pWorkBuf1, 0x00, tempBufSize ); - - }//for quad spec rings + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET, + i_procTgt, + attrVal ), + "Error from FAPI_ATTR_SET for attribute ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET"); - pCmnRingIndex = pCmnRingIndex + QUAD_SPEC_RING_INDEX_SIZE; // Jump to next Quad Index - } + FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); - io_qpmrHdr.quadSpecRingOffset = io_qpmrHdr.quadCommonRingOffset + io_qpmrHdr.quadCommonRingLength; - io_qpmrHdr.quadSpecRingLength = (instRingPayLoad - pRingStart); - FAPI_DBG("Instance Ring Length 0x%08X", io_qpmrHdr.quadSpecRingLength); - } - while(0); + attrVal = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset); + attrVal |= (0x80000000 | PPMR_HOMER_OFFSET); - return rc; - } + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET, + i_procTgt, + attrVal ), + "Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET"); -//------------------------------------------------------------------------------ + FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); - /** - * @brief creates a scan ring layout for quad common rings in HOMER. - * @param i_pHOMER points to HOMER image. - * @param i_chipState functional state of all cores within P9 chip - * @param i_ringData contains ring buffers and respective sizes - * @param i_debugMode scan ring debug state - * @param i_riskLevel true if system IPL is in risk level mode else false. - * @param io_qpmrHdr instance of QPMR header. - * @param i_imgType image type to be built - * @param IMG_BUILD_SUCCESS if function succeeds else error code. - */ - uint32_t layoutRingsForSGPE( Homerlayout_t* i_pHomer, - void* i_pOverride, - const P9FuncModel& i_chipState, - RingBufData& i_ringData, - RingDebugMode_t i_debugMode, - uint32_t i_riskLevel, - QpmrHeaderLayout_t& io_qpmrHdr, - ImageType_t i_imgType ) - { - FAPI_DBG( "> layoutRingsForSGPE"); - uint32_t rc = IMG_BUILD_SUCCESS; - RingVariant_t l_ringVariant = BASE; - sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - RingBucket sgpeRings( PLAT_SGPE, - (uint8_t*)&i_pHomer->qpmrRegion, - i_debugMode ); +fapi_try_exit: + return fapi2::current_err; +} - do - { +//--------------------------------------------------------------------------- +/** + * @brief Set the Fabric System, Group and Chip IDs into SGPE and CME headers + * @brief i_pChipHomer points to start of HOMER + */ +fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ - // get all the rings pertaining to CME in a work buffer first. - if( i_riskLevel ) - { - l_ringVariant = RL; - } + uint32_t l_system_id; + uint8_t l_group_id; + uint8_t l_chip_id; + fapi2::buffer<uint16_t> l_location_id = 0; + uint16_t l_locationVal = 0; - //Manage the Quad Common rings in HOMER - layoutCmnRingsForSgpe( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - l_ringVariant, - io_qpmrHdr, - i_imgType, - sgpeRings ); - - //Manage the Quad Override rings in HOMER - layoutSgpeScanOverride( i_pHomer, - i_pOverride, - i_chipState, - i_ringData, - i_debugMode, - io_qpmrHdr, - i_imgType ); + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; - //Manage the Quad specific rings in HOMER - layoutInstRingsForSgpe( i_pHomer, - i_chipState, - i_ringData, - i_debugMode, - BASE, // VPD rings are always BASE - io_qpmrHdr, - i_imgType, - sgpeRings ); - - if( 0 == io_qpmrHdr.quadCommonRingLength ) - { - //If quad common rings don't exist ensure its offset in image header is zero - pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset = 0; - } + FAPI_DBG(" ==================== Fabric IDs ================="); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, + i_procTgt, + l_system_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_SYSTEM_ID"); - if( io_qpmrHdr.quadSpecRingLength > 0 ) - { - pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = io_qpmrHdr.quadCommonRingLength + - SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); - pSgpeImgHdr->g_sgpe_scom_offset = - SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength) + io_qpmrHdr.quadCommonRingLength + - io_qpmrHdr.quadSpecRingLength; - } - } - while(0); //building instance rings - - //Let us handle endianes at last - io_qpmrHdr.quadCommonRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingOffset); - io_qpmrHdr.quadCommonRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonRingLength); - io_qpmrHdr.quadCommonOvrdOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdOffset); - io_qpmrHdr.quadCommonOvrdLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadCommonOvrdLength); - io_qpmrHdr.quadSpecRingOffset = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingOffset); - io_qpmrHdr.quadSpecRingLength = SWIZZLE_4_BYTE(io_qpmrHdr.quadSpecRingLength); - pSgpeImgHdr->g_sgpe_spec_ring_occ_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset); - pSgpeImgHdr->g_sgpe_scom_offset = SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_scom_offset); - sgpeRings.dumpRings(); - - FAPI_DBG("SGPE Header Ring Details "); - FAPI_DBG("Common Ring Offset %d (0x%08X) ", - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset), - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_cmn_ring_occ_offset)); - FAPI_DBG("Instance Ring Offset %d (0x%08X) ", - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset), - SWIZZLE_4_BYTE(pSgpeImgHdr->g_sgpe_spec_ring_occ_offset)); - - - return rc; - } -//--------------------------------------------------------------------------- - /** - * @brief updates the IVPR attributes for SGPE, PGPE. - * @brief i_pChipHomer points to start of HOMER - */ - fapi2::ReturnCode updateGpeAttributes( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) - { - QpmrHeaderLayout_t* pQpmrHdr = (QpmrHeaderLayout_t*)i_pChipHomer->qpmrRegion.sgpeRegion.qpmrHeader; - PpmrHeader_t* pPpmrHdr = (PpmrHeader_t*) i_pChipHomer->ppmrRegion.ppmrHeader; + FAPI_DBG("Fabric System ID : 0x%04X", l_system_id); - uint32_t attrVal = SWIZZLE_4_BYTE(pQpmrHdr->bootCopierOffset); - attrVal |= (0x80000000 | ONE_MB); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, + i_procTgt, + l_group_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_GROUP_ID"); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_SET for attribute ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET"); + FAPI_DBG("Fabric Group ID : 0x%01X", l_group_id); - FAPI_DBG("Set ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, + i_procTgt, + l_chip_id), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_CHIP_ID"); - attrVal = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_bc_offset); - attrVal |= (0x80000000 | PPMR_HOMER_OFFSET); + FAPI_DBG("Fabric Chip ID : 0x%01X", l_chip_id); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_SET for attribute ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET"); + // Create a unit16_t Location Ids in the form of: + // 0:3 Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID) + // 4:6 Chip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID) + // 7 0 + // 8:12 System ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID) + // 13:15 00 - FAPI_DBG("Set ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET to 0x%08X", attrVal ); + l_location_id.insert < 0, 4, 8 - 4, uint8_t > ( l_group_id ); + l_location_id.insert < 4, 3, 8 - 3, uint8_t > ( l_chip_id ); + l_location_id.insert < 8, 5, 32 - 5, uint32_t > ( l_system_id ); - fapi_try_exit: - return fapi2::current_err; - } + FAPI_DBG("Location ID : 0x%04X", l_location_id); -//--------------------------------------------------------------------------- - /** - * @brief Set the Fabric System, Group and Chip IDs into SGPE and CME headers - * @brief i_pChipHomer points to start of HOMER - */ - fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) - { + l_location_id.extract<0, 16>(l_locationVal); + // Populate the CME Header + pCmeHdr->g_cme_location_id = SWIZZLE_2_BYTE(l_locationVal); - uint32_t l_system_id; - uint8_t l_group_id; - uint8_t l_chip_id; - fapi2::buffer<uint16_t> l_location_id = 0; - uint16_t l_locationVal = 0; + // Populate the SGPE Header + pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal); - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; +fapi_try_exit: + return fapi2::current_err; - FAPI_DBG(" ==================== Fabric IDs ================="); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, - i_procTgt, - l_system_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_SYSTEM_ID"); +} - FAPI_DBG("Fabric System ID : 0x%04X", l_system_id); +//--------------------------------------------------------------------------------------------------- - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, - i_procTgt, - l_group_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_GROUP_ID"); +/** + * @brief populates EQ SCOM restore region of HOMER with SCOM restore value for NCU RNG BAR ENABLE. + * @param i_pChipHomer points to start of P9 HOMER + * @param i_procTgt fapi2 target for p9 chip. + * @return faip2 return code. + */ +fapi2::ReturnCode populateNcuRingBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +{ + FAPI_DBG("> populateNcuRingBarScomReg"); - FAPI_DBG("Fabric Group ID : 0x%01X", l_group_id); + do + { + uint8_t attrVal = 0; + uint64_t nxRangeBarAddrOffset = 0; + uint64_t regNcuRngBarData = 0; + uint64_t baseAddressNm0 = 0; + uint64_t baseAddressNm1 = 0; + uint64_t baseAddressMirror = 0; + uint32_t ncuBarRegisterAddr = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, i_procTgt, - l_chip_id), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_FABRIC_CHIP_ID"); + attrVal ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_ENABLE"); - FAPI_DBG("Fabric Chip ID : 0x%01X", l_chip_id); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, + FAPI_SYSTEM, + nxRangeBarAddrOffset ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET"); - // Create a unit16_t Location Ids in the form of: - // 0:3 Group ID (loaded from ATTR_PROC_FABRIC_GROUP_ID) - // 4:6 Chip ID (loaded from ATTR_PROC_FABRIC_CHIP_ID) - // 7 0 - // 8:12 System ID (loaded from ATTR_PROC_FABRIC_SYSTEM_ID) - // 13:15 00 + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_procTgt, + baseAddressNm0, + baseAddressNm1, + baseAddressMirror, + regNcuRngBarData), + "Failed in p9_fbc_utils_get_chip_base_address" ); - l_location_id.insert < 0, 4, 8 - 4, uint8_t > ( l_group_id ); - l_location_id.insert < 4, 3, 8 - 3, uint8_t > ( l_chip_id ); - l_location_id.insert < 8, 5, 32 - 5, uint32_t > ( l_system_id ); - FAPI_DBG("Location ID : 0x%04X", l_location_id); + if( fapi2::ENUM_ATTR_PROC_NX_RNG_BAR_ENABLE_ENABLE == attrVal ) + { + //Set bit0 which corresponds to bit DARN_BAR_EN of reg NCU_DAR_BAR + regNcuRngBarData |= DARN_BAR_EN_POS ; + } - l_location_id.extract<0, 16>(l_locationVal); - // Populate the CME Header - pCmeHdr->g_cme_location_id = SWIZZLE_2_BYTE(l_locationVal); + regNcuRngBarData += nxRangeBarAddrOffset; - // Populate the SGPE Header - pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal); + for( uint32_t exIndex = 0; exIndex < MAX_CMES_PER_CHIP; exIndex++ ) + { + ncuBarRegisterAddr = EX_0_NCU_DARN_BAR_REG; + ncuBarRegisterAddr |= (( exIndex >> 1) << 24 ); + ncuBarRegisterAddr |= ( exIndex & 0x01 ) ? 0x0400 : 0x0000; + + FAPI_DBG("CME%d NCU_DARN_BAR Addr 0x%08x Data 0x%016lx ", + exIndex, ncuBarRegisterAddr, regNcuRngBarData ); + + StopReturnCode_t stopRc = + stopImageSection::p9_stop_save_scom( i_pChipHomer, + ncuBarRegisterAddr, + regNcuRngBarData , + stopImageSection::P9_STOP_SCOM_REPLACE, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - fapi_try_exit: - return fapi2::current_err; + if( stopRc ) + { + FAPI_ERR("Failed to update CME%d NCU_DARN_RNG_BAR Reg RC: 0x%08x", + exIndex, stopRc ); + break; + } + } } + while(0); -//--------------------------------------------------------------------------------------------------- + FAPI_DBG("< populateNcuRingBarScomReg"); +fapi_try_exit: + return fapi2::current_err; +} - /** - * @brief populates EQ SCOM restore region of HOMER with SCOM restore value for NCU RNG BAR ENABLE. - * @param i_pChipHomer points to start of P9 HOMER - * @param i_procTgt fapi2 target for p9 chip. - * @return faip2 return code. - */ - fapi2::ReturnCode populateNcuRingBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) +//-------------------------------------------------------------------------------------------- + +/** + * @brief populate L2 Epsilon SCOM register. + * @param i_pChipHomer points to start of P9 HOMER. + * @return fapi2 return code. + */ +fapi2::ReturnCode populateEpsilonL2ScomReg( void* i_pChipHomer ) +{ + FAPI_DBG("> populateEpsilonL2ScomReg"); + + do { - FAPI_DBG("> populateNcuRingBarScomReg"); - - do - { - uint8_t attrVal = 0; - uint64_t nxRangeBarAddrOffset = 0; - uint64_t regNcuRngBarData = 0; - uint64_t baseAddressNm0 = 0; - uint64_t baseAddressNm1 = 0; - uint64_t baseAddressMirror = 0; - uint32_t ncuBarRegisterAddr = 0; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE, - i_procTgt, - attrVal ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_ENABLE"); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET, - FAPI_SYSTEM, - nxRangeBarAddrOffset ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET"); - - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_procTgt, - baseAddressNm0, - baseAddressNm1, - baseAddressMirror, - regNcuRngBarData), - "Failed in p9_fbc_utils_get_chip_base_address" ); - - - if( fapi2::ENUM_ATTR_PROC_NX_RNG_BAR_ENABLE_ENABLE == attrVal ) - { - //Set bit0 which corresponds to bit DARN_BAR_EN of reg NCU_DAR_BAR - regNcuRngBarData |= DARN_BAR_EN_POS ; - } + uint32_t attrValT0 = 0; + uint32_t attrValT1 = 0; + uint32_t attrValT2 = 0; + uint32_t scomAddr = 0; + uint32_t rc = IMG_BUILD_SUCCESS; - regNcuRngBarData += nxRangeBarAddrOffset; + uint64_t l_epsilonScomVal; + fapi2::buffer<uint64_t> epsilonValBuf; - for( uint32_t exIndex = 0; exIndex < MAX_CMES_PER_CHIP; exIndex++ ) - { - ncuBarRegisterAddr = EX_0_NCU_DARN_BAR_REG; - ncuBarRegisterAddr |= (( exIndex >> 1) << 24 ); - ncuBarRegisterAddr |= ( exIndex & 0x01 ) ? 0x0400 : 0x0000; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - FAPI_DBG("CME%d NCU_DARN_BAR Addr 0x%08x Data 0x%016lx ", - exIndex, ncuBarRegisterAddr, regNcuRngBarData ); + //============================================================================= + //Determine SCOM register data value for EX_L2_RD_EPS_REG by reading attributes + //============================================================================= - StopReturnCode_t stopRc = - stopImageSection::p9_stop_save_scom( i_pChipHomer, - ncuBarRegisterAddr, - regNcuRngBarData , - stopImageSection::P9_STOP_SCOM_REPLACE, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + //----------------------------- Tier0(T0)-------------------------------------- - if( stopRc ) - { - FAPI_ERR("Failed to update CME%d NCU_DARN_RNG_BAR Reg RC: 0x%08x", - exIndex, stopRc ); - break; - } - } + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, + FAPI_SYSTEM, + attrValT0 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); - } - while(0); + attrValT0 = attrValT0 / 8 + 1; + epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); - FAPI_DBG("< populateNcuRingBarScomReg"); - fapi_try_exit: - return fapi2::current_err; - } + //----------------------------- Tier1(T1)-------------------------------------- -//-------------------------------------------------------------------------------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); - /** - * @brief populate L2 Epsilon SCOM register. - * @param i_pChipHomer points to start of P9 HOMER. - * @return fapi2 return code. - */ - fapi2::ReturnCode populateEpsilonL2ScomReg( void* i_pChipHomer ) - { - FAPI_DBG("> populateEpsilonL2ScomReg"); + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); + + //----------------------------- Tier2(T2)-------------------------------------- + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); + + + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); - do + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + + //----------------------- Updating SCOM Registers using STOP API -------------------- + uint32_t eqCnt = 0; + + for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) { - uint32_t attrValT0 = 0; - uint32_t attrValT1 = 0; - uint32_t attrValT2 = 0; - uint32_t scomAddr = 0; - uint32_t rc = IMG_BUILD_SUCCESS; + scomAddr = (EX_L2_RD_EPS_REG | (eqCnt << QUAD_BIT_POS)); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - uint64_t l_epsilonScomVal; - fapi2::buffer<uint64_t> epsilonValBuf; + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + scomAddr |= ODD_EVEN_EX_POS; + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - //============================================================================= - //Determine SCOM register data value for EX_L2_RD_EPS_REG by reading attributes - //============================================================================= + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } + } - //----------------------------- Tier0(T0)-------------------------------------- + //=============================================================================== + //Determine SCOM register data value for EX_L2_WR_EPS_REG by reading attributes + //=============================================================================== + l_epsilonScomVal = 0; + epsilonValBuf.flush<0>(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, - FAPI_SYSTEM, - attrValT0 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); + //----------------------------- Tier1(T1)-------------------------------------- - attrValT0 = attrValT0 / 8 + 1; - epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); - //----------------------------- Tier1(T1)-------------------------------------- + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); + //----------------------------- Tier2(T2)-------------------------------------- - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); - //----------------------------- Tier2(T2)-------------------------------------- + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); + // p9.l2.scom.inifile: + // EPS_DIVIDER_MODE = 0001 + // EPS_MODE_SEL = 0 + // EPS_CNT_USE_L2_DIVIDER_EN = 0 + // L2_EPS_STEP_MODE = 0000 + epsilonValBuf.setBit<27>(); + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); + //----------------------- Updating SCOM Registers using STOP API -------------------- - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L2_WR_EPS_REG | (eqCnt << QUAD_BIT_POS)); + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); - //----------------------- Updating SCOM Registers using STOP API -------------------- - uint32_t eqCnt = 0; + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + if( rc ) { - scomAddr = (EX_L2_RD_EPS_REG | (eqCnt << QUAD_BIT_POS)); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + scomAddr |= ODD_EVEN_EX_POS; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); - scomAddr |= ODD_EVEN_EX_POS; - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; } + } - //=============================================================================== - //Determine SCOM register data value for EX_L2_WR_EPS_REG by reading attributes - //=============================================================================== - l_epsilonScomVal = 0; - epsilonValBuf.flush<0>(); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::EPSILON_SCOM_UPDATE_FAIL() + .set_STOP_API_SCOM_ERR( rc ) + .set_EPSILON_REG_ADDR( scomAddr ) + .set_EPSILON_REG_DATA( l_epsilonScomVal ), + "Failed to create restore entry for L2 Epsilon register" ); - //----------------------------- Tier1(T1)-------------------------------------- + } + while(0); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); + FAPI_DBG("< populateEpsilonL2ScomReg"); +fapi_try_exit: + return fapi2::current_err; +} - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); +//--------------------------------------------------------------------------- - //----------------------------- Tier2(T2)-------------------------------------- +/** + * @brief populate L3 Epsilon SCOM register. + * @param i_pChipHomer points to start of P9 HOMER. + * @return fapi2 return code. + */ +fapi2::ReturnCode populateEpsilonL3ScomReg( void* i_pChipHomer ) +{ + FAPI_DBG("> populateEpsilonL3ScomReg"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); + do + { + uint32_t attrValT0 = 0; + uint32_t attrValT1 = 0; + uint32_t attrValT2 = 0; + uint32_t scomAddr = 0; + uint32_t rc = IMG_BUILD_SUCCESS; + uint64_t l_epsilonScomVal; + fapi2::buffer<uint64_t> epsilonValBuf; - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - // p9.l2.scom.inifile: - // EPS_DIVIDER_MODE = 0001 - // EPS_MODE_SEL = 0 - // EPS_CNT_USE_L2_DIVIDER_EN = 0 - // L2_EPS_STEP_MODE = 0000 - epsilonValBuf.setBit<27>(); + //===================================================================================== + //Determine SCOM register data value for EX_L3_RD_EPSILON_CFG_REG by reading attributes + //===================================================================================== - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + //----------------------------- Tier0(T0)-------------------------------------- - //----------------------- Updating SCOM Registers using STOP API -------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, + FAPI_SYSTEM, + attrValT0 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); - for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) - { - scomAddr = (EX_L2_WR_EPS_REG | (eqCnt << QUAD_BIT_POS)); - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + attrValT0 = attrValT0 / 8 + 1; + epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + //----------------------------- Tier1(T1)-------------------------------------- - scomAddr |= ODD_EVEN_EX_POS; - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } - } + //----------------------------- Tier2(T2)-------------------------------------- - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::EPSILON_SCOM_UPDATE_FAIL() - .set_STOP_API_SCOM_ERR( rc ) - .set_EPSILON_REG_ADDR( scomAddr ) - .set_EPSILON_REG_DATA( l_epsilonScomVal ), - "Failed to create restore entry for L2 Epsilon register" ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); - } - while(0); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); - FAPI_DBG("< populateEpsilonL2ScomReg"); - fapi_try_exit: - return fapi2::current_err; - } + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); -//--------------------------------------------------------------------------- + //----------------------- Updating SCOM Registers using STOP API -------------------- - /** - * @brief populate L3 Epsilon SCOM register. - * @param i_pChipHomer points to start of P9 HOMER. - * @return fapi2 return code. - */ - fapi2::ReturnCode populateEpsilonL3ScomReg( void* i_pChipHomer ) - { - FAPI_DBG("> populateEpsilonL3ScomReg"); + uint32_t eqCnt = 0; - do + for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) { - uint32_t attrValT0 = 0; - uint32_t attrValT1 = 0; - uint32_t attrValT2 = 0; - uint32_t scomAddr = 0; - uint32_t rc = IMG_BUILD_SUCCESS; - uint64_t l_epsilonScomVal; - fapi2::buffer<uint64_t> epsilonValBuf; + scomAddr = (EX_L3_RD_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - //===================================================================================== - //Determine SCOM register data value for EX_L3_RD_EPSILON_CFG_REG by reading attributes - //===================================================================================== + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } - //----------------------------- Tier0(T0)-------------------------------------- + scomAddr |= ODD_EVEN_EX_POS; + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, - FAPI_SYSTEM, - attrValT0 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T0"); + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } + } - attrValT0 = attrValT0 / 8 + 1; - epsilonValBuf.insert<0, 12, 20, uint32_t>( attrValT0 ); + //===================================================================================== + //Determine SCOM register data value for EX_L3_L3_WR_EPSILON_CFG_REG by reading attributes + //===================================================================================== - //----------------------------- Tier1(T1)-------------------------------------- + l_epsilonScomVal = 0; + epsilonValBuf.flush<0>(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T1"); + //----------------------------- Tier1(T1)-------------------------------------- - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert<12, 12, 20, uint32_t>( attrValT1 ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, + FAPI_SYSTEM, + attrValT1 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); - //----------------------------- Tier2(T2)-------------------------------------- + attrValT1 = attrValT1 / 8 + 1; + epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_READ_CYCLES_T2"); + //----------------------------- Tier2(T2)-------------------------------------- - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert<24, 12, 20, uint32_t>( attrValT2 ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, + FAPI_SYSTEM, + attrValT2 ), + "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + attrValT2 = attrValT2 / 8 + 1; + epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); - //----------------------- Updating SCOM Registers using STOP API -------------------- + // p9.l3.scom.initfile: + // L3_EPS_STEP_MODE = 0000 + // L3_EPS_DIVIDER_MODE = 0001 + // EPS_CNT_USE_L3_DIVIDER_EN = 0 + epsilonValBuf.setBit<33>(); - uint32_t eqCnt = 0; + epsilonValBuf.extract<0, 64>(l_epsilonScomVal); - for( ; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) - { - scomAddr = (EX_L3_RD_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + //----------------------- Updating SCOM Registers using STOP API -------------------- - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) + { + scomAddr = (EX_L3_L3_WR_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - scomAddr |= ODD_EVEN_EX_POS; - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; } - //===================================================================================== - //Determine SCOM register data value for EX_L3_L3_WR_EPSILON_CFG_REG by reading attributes - //===================================================================================== + scomAddr |= ODD_EVEN_EX_POS; - l_epsilonScomVal = 0; - epsilonValBuf.flush<0>(); + FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", + scomAddr, l_epsilonScomVal); - //----------------------------- Tier1(T1)-------------------------------------- + rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, + scomAddr, + l_epsilonScomVal, + stopImageSection::P9_STOP_SCOM_APPEND, + stopImageSection::P9_STOP_SECTION_EQ_SCOM ); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, - FAPI_SYSTEM, - attrValT1 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T1"); + if( rc ) + { + FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); + break; + } + } - attrValT1 = attrValT1 / 8 + 1; - epsilonValBuf.insert< 0, 12, 20, uint32_t >(attrValT1); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), + fapi2::EPSILON_SCOM_UPDATE_FAIL() + .set_STOP_API_SCOM_ERR( rc ) + .set_EPSILON_REG_ADDR( scomAddr ) + .set_EPSILON_REG_DATA( l_epsilonScomVal ), + "Failed to create restore entry for L3 Epsilon register" ); - //----------------------------- Tier2(T2)-------------------------------------- + } + while(0); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, - FAPI_SYSTEM, - attrValT2 ), - "Error from FAPI_ATTR_GET for attribute ATTR_PROC_EPS_WRITE_CYCLES_T2"); + FAPI_DBG("< populateEpsilonL3ScomReg"); +fapi_try_exit: + return fapi2::current_err; +} - attrValT2 = attrValT2 / 8 + 1; - epsilonValBuf.insert< 12, 12, 20, uint32_t >(attrValT2); +//--------------------------------------------------------------------------- - // p9.l3.scom.initfile: - // L3_EPS_STEP_MODE = 0000 - // L3_EPS_DIVIDER_MODE = 0001 - // EPS_CNT_USE_L3_DIVIDER_EN = 0 - epsilonValBuf.setBit<33>(); +/** + * @brief Reads an attribute to determine aux function invocation interval. + * @param i_pHomer points to HOMER. + * @param o_auxFuncIntControl Invocation interval for the auxiliary function. + * return fapi2 return code. + */ +fapi2::ReturnCode initReadIntervalForAuxFunc( Homerlayout_t* i_pHomer, uint32_t& o_auxFuncIntControl ) +{ + FAPI_DBG("> initReadIntervalForAuxFunc"); + uint8_t readInterAttr = 0; + o_auxFuncIntControl = 0; - epsilonValBuf.extract<0, 64>(l_epsilonScomVal); + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - //----------------------- Updating SCOM Registers using STOP API -------------------- + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PERF_24x7_INVOCATION_TIME_MS, + FAPI_SYSTEM, + readInterAttr), + "Error from FAPI_ATTR_GET for attribute ATTR_PERF_24x7_INVOCATION_TIME_MS"); - for( eqCnt = 0; eqCnt < MAX_QUADS_PER_CHIP; eqCnt++ ) - { - scomAddr = (EX_L3_L3_WR_EPSILON_CFG_REG | (eqCnt << QUAD_BIT_POS)); - - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + if( readInterAttr ) + { + o_auxFuncIntControl = ( readInterAttr << SGPE_AUX_FUNC_INERVAL_SHIFT ); + FAPI_DBG("sgpeReadAttrInterval 0x%08x", o_auxFuncIntControl ); + } - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } + FAPI_DBG("< initReadIntervalForAuxFunc"); +fapi_try_exit: + return fapi2::current_err; +} - scomAddr |= ODD_EVEN_EX_POS; +//--------------------------------------------------------------------------- - FAPI_DBG("Calling STOP API to update SCOM reg 0x%08x value 0x%016llx", - scomAddr, l_epsilonScomVal); +/** + * @brief builds HOMER section supporting Auxiliary functions. + * @param i_procTgt fapi2 target for P9 chip + * @param i_pHomer points to HOMER. + * @param o_qpmrHdr instance of QpmrHeaderLayout_t + */ +fapi2::ReturnCode buildSgpeAux( CONST_FAPI2_PROC& i_procTgt, Homerlayout_t* i_pHomer, + QpmrHeaderLayout_t& o_qpmrHdr ) +{ + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; + uint32_t l_sgpeAuxFunc = 0; - rc = stopImageSection::p9_stop_save_scom( i_pChipHomer, - scomAddr, - l_epsilonScomVal, - stopImageSection::P9_STOP_SCOM_APPEND, - stopImageSection::P9_STOP_SECTION_EQ_SCOM ); + //SGPE Image Header + //Offset represented as OCI PBA memory address + pSgpeHdr->g_sgpe_aux_offset = SWIZZLE_4_BYTE(HOMER_AUX_BASE_ADDR); + pSgpeHdr->g_sgpe_aux_length = SWIZZLE_4_BYTE(QPMR_AUX_LENGTH); - if( rc ) - { - FAPI_DBG(" p9_stop_save_scom Failed rc 0x%08x", rc ); - break; - } - } + //QPMR Header + o_qpmrHdr.quadAuxOffset = SWIZZLE_4_BYTE(QPMR_AUX_OFFSET); + o_qpmrHdr.quadAuxLength = SWIZZLE_4_BYTE(QPMR_AUX_LENGTH); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rc ), - fapi2::EPSILON_SCOM_UPDATE_FAIL() - .set_STOP_API_SCOM_ERR( rc ) - .set_EPSILON_REG_ADDR( scomAddr ) - .set_EPSILON_REG_DATA( l_epsilonScomVal ), - "Failed to create restore entry for L3 Epsilon register" ); + FAPI_TRY(initReadIntervalForAuxFunc( i_pHomer, l_sgpeAuxFunc ), + "Failed in initReadIntervalForAuxFunc" ); + pSgpeHdr->g_sgpe_aux_control = SWIZZLE_4_BYTE(l_sgpeAuxFunc); - } - while(0); +fapi_try_exit: + return fapi2::current_err; - FAPI_DBG("< populateEpsilonL3ScomReg"); - fapi_try_exit: - return fapi2::current_err; - } +} //--------------------------------------------------------------------------- - fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, - void* const i_pImageIn, - void* i_pHomerImage, - void* const i_pRingOverride, - SysPhase_t i_phase, - ImageType_t i_imgType, - void* const i_pBuf1, - const uint32_t i_sizeBuf1, - void* const i_pBuf2, - const uint32_t i_sizeBuf2, - void* const i_pBuf3, - const uint32_t i_sizeBuf3 ) +fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, + void* const i_pImageIn, + void* i_pHomerImage, + void* const i_pRingOverride, + SysPhase_t i_phase, + ImageType_t i_imgType, + void* const i_pBuf1, + const uint32_t i_sizeBuf1, + void* const i_pBuf2, + const uint32_t i_sizeBuf2, + void* const i_pBuf3, + const uint32_t i_sizeBuf3 ) - { - FAPI_IMP("Entering p9_hcode_image_build "); - - do - { - FAPI_DBG("validating argument .."); - - FAPI_TRY( validateInputArguments( i_pImageIn, i_pHomerImage, i_phase, - i_imgType, - i_pBuf1, - i_sizeBuf1, - i_pBuf2, - i_sizeBuf2, - i_pBuf3, - i_sizeBuf3 ), - "Invalid arguments, escaping hcode image build" ); - - uint8_t ecLevel = 0; - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, - i_procTgt, - ecLevel), - "Error from for attribute ATTR_EC"); - - FAPI_INF("Creating chip functional model"); - - P9FuncModel l_chipFuncModel( i_procTgt, ecLevel ); - Homerlayout_t* pChipHomer = ( Homerlayout_t*) i_pHomerImage; - const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - uint32_t ppeImgRc = IMG_BUILD_SUCCESS; - QpmrHeaderLayout_t l_qpmrHdr; - // HW Image is a nested XIP Image. Let us read global TOC of hardware image - // and find out if XIP header of PPE image is contained therein. - // Let us start with SGPE - FAPI_INF("SGPE building"); - ppeImgRc = buildSgpeImage( i_pImageIn, pChipHomer, i_imgType, l_qpmrHdr ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SGPE_BUILD_FAIL() - .set_SGPE_FAIL_SECTN( ppeImgRc ), - "Failed to copy SGPE section in HOMER" ); - FAPI_INF("SGPE built"); - - // copy sections pertaining to self restore - // Note: this creates the CPMR header portion - - //let us determine if system is configured in fuse mode. This needs to - //be updated in a CPMR region. - uint8_t fuseModeState = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, - FAPI_SYSTEM, - fuseModeState), - "Error from FAPI_ATTR_GET for attribute ATTR_FUSED_CORE_MODE"); - - FAPI_INF("CPMR / Self Restore building"); - ppeImgRc = buildCoreRestoreImage( i_pImageIn, pChipHomer, i_imgType, fuseModeState ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SELF_RESTORE_BUILD_FAIL() - .set_SELF_RESTORE_FAIL_SECTN( ppeImgRc ), - "Failed to copy core self restore section in HOMER" ); - FAPI_INF("Self Restore built "); - - // copy sections pertaining to CME - FAPI_INF("CPMR / CME building"); - uint64_t cpmrPhyAdd = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOMER_PHYS_ADDR, i_procTgt, cpmrPhyAdd ), - "Error from FAPI_ATTR_GET for ATTR_HOMER_PHYS_ADDR"); - FAPI_DBG("HOMER base address 0x%016lX", cpmrPhyAdd ); - ppeImgRc = buildCmeImage( i_pImageIn, pChipHomer, i_imgType, cpmrPhyAdd ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::CME_BUILD_FAIL() - .set_CME_FAIL_SECTN( ppeImgRc ), - "Failed to copy CME section in HOMER" ); - - FAPI_INF("CME built"); - - FAPI_INF("PGPE building"); - PpmrHeader_t l_ppmrHdr; - ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, l_ppmrHdr, i_imgType ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::PGPE_BUILD_FAIL() - .set_PGPE_FAIL_SECTN( ppeImgRc ), - "Failed to copy PGPE section in HOMER" ); - - //Update P State parameter block info in HOMER - FAPI_TRY( buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType ), - "Failed to add parameter block" ); - - FAPI_INF("PGPE built"); - //Let us add Scan Rings to the image. - uint8_t l_ringDebug = 0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, - FAPI_SYSTEM, - l_ringDebug), - "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_RING_DBG_MODE"); - FAPI_DBG("Ring Debug Level 0x%02x", l_ringDebug ); - - RingBufData l_ringData( i_pBuf1, - i_sizeBuf1, - i_pBuf2, - i_sizeBuf2, - i_pBuf3, - i_sizeBuf3 ); - - //Extract all the rings for CME platform from HW Image and VPD - ppeImgRc = getPpeScanRings( i_pImageIn, - PLAT_CME, - i_procTgt, - l_ringData, - i_imgType ); +{ + FAPI_IMP("Entering p9_hcode_image_build "); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SCAN_RING_EXTRACTION_FAIL() - .set_EXTRACTION_FAIL_PLAT( PLAT_CME ) - .set_EXTRACTION_FAILURE_CODE( ppeImgRc ), - "Failed to extract core scan rings" ); - - uint8_t l_iplPhase = 0 ; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, - FAPI_SYSTEM, - l_iplPhase), - "Error from FAPI_ATTR_GET for ATTR_RISK_LEVEL"); - - // create a layout of rings in HOMER for consumption of CME - ppeImgRc = layoutRingsForCME( pChipHomer, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - i_imgType, - i_pRingOverride ); - - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SCAN_RING_PLACEMENT_FAIL() - .set_PLACEMENT_FAIL_PLAT( PLAT_CME ) - .set_PLACEMENT_FAILURE_CODE( ppeImgRc ), - "Failed to place core scan rings" ); - - l_ringData.iv_ringBufSize = i_sizeBuf1; - ppeImgRc = getPpeScanRings( i_pImageIn, - PLAT_SGPE, - i_procTgt, - l_ringData, - i_imgType ); + do + { + FAPI_DBG("validating argument .."); + + FAPI_TRY( validateInputArguments( i_pImageIn, i_pHomerImage, i_phase, + i_imgType, + i_pBuf1, + i_sizeBuf1, + i_pBuf2, + i_sizeBuf2, + i_pBuf3, + i_sizeBuf3 ), + "Invalid arguments, escaping hcode image build" ); + + uint8_t ecLevel = 0; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, + i_procTgt, + ecLevel), + "Error from for attribute ATTR_EC"); + + FAPI_INF("Creating chip functional model"); + + P9FuncModel l_chipFuncModel( i_procTgt, ecLevel ); + Homerlayout_t* pChipHomer = ( Homerlayout_t*) i_pHomerImage; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + uint32_t ppeImgRc = IMG_BUILD_SUCCESS; + QpmrHeaderLayout_t l_qpmrHdr; + // HW Image is a nested XIP Image. Let us read global TOC of hardware image + // and find out if XIP header of PPE image is contained therein. + // Let us start with SGPE + FAPI_INF("SGPE building"); + ppeImgRc = buildSgpeImage( i_pImageIn, pChipHomer, i_imgType, l_qpmrHdr ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SGPE_BUILD_FAIL() + .set_SGPE_FAIL_SECTN( ppeImgRc ), + "Failed to copy SGPE section in HOMER" ); + + FAPI_TRY( buildSgpeAux( i_procTgt, pChipHomer, l_qpmrHdr ), + "Failed to build Auxiliary section" ); + + FAPI_INF("SGPE built"); + + // copy sections pertaining to self restore + // Note: this creates the CPMR header portion + + //let us determine if system is configured in fuse mode. This needs to + //be updated in a CPMR region. + uint8_t fuseModeState = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE, + FAPI_SYSTEM, + fuseModeState), + "Error from FAPI_ATTR_GET for attribute ATTR_FUSED_CORE_MODE"); + + FAPI_INF("CPMR / Self Restore building"); + ppeImgRc = buildCoreRestoreImage( i_pImageIn, pChipHomer, i_imgType, fuseModeState ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SELF_RESTORE_BUILD_FAIL() + .set_SELF_RESTORE_FAIL_SECTN( ppeImgRc ), + "Failed to copy core self restore section in HOMER" ); + FAPI_INF("Self Restore built "); + + // copy sections pertaining to CME + FAPI_INF("CPMR / CME building"); + uint64_t cpmrPhyAdd = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOMER_PHYS_ADDR, i_procTgt, cpmrPhyAdd ), + "Error from FAPI_ATTR_GET for ATTR_HOMER_PHYS_ADDR"); + FAPI_DBG("HOMER base address 0x%016lX", cpmrPhyAdd ); + ppeImgRc = buildCmeImage( i_pImageIn, pChipHomer, i_imgType, cpmrPhyAdd ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::CME_BUILD_FAIL() + .set_CME_FAIL_SECTN( ppeImgRc ), + "Failed to copy CME section in HOMER" ); + + FAPI_INF("CME built"); + + FAPI_INF("PGPE building"); + PpmrHeader_t l_ppmrHdr; + ppeImgRc = buildPgpeImage( i_pImageIn, pChipHomer, l_ppmrHdr, i_imgType ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::PGPE_BUILD_FAIL() + .set_PGPE_FAIL_SECTN( ppeImgRc ), + "Failed to copy PGPE section in HOMER" ); + + //Update P State parameter block info in HOMER + FAPI_TRY( buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType ), + "Failed to add parameter block" ); + + FAPI_INF("PGPE built"); + //Let us add Scan Rings to the image. + uint8_t l_ringDebug = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, + FAPI_SYSTEM, + l_ringDebug), + "Error from FAPI_ATTR_GET for attribute ATTR_SYSTEM_RING_DBG_MODE"); + FAPI_DBG("Ring Debug Level 0x%02x", l_ringDebug ); + + RingBufData l_ringData( i_pBuf1, + i_sizeBuf1, + i_pBuf2, + i_sizeBuf2, + i_pBuf3, + i_sizeBuf3 ); + + //Extract all the rings for CME platform from HW Image and VPD + ppeImgRc = getPpeScanRings( i_pImageIn, + PLAT_CME, + i_procTgt, + l_ringData, + i_imgType ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SCAN_RING_EXTRACTION_FAIL() - .set_EXTRACTION_FAIL_PLAT( PLAT_SGPE ) - .set_EXTRACTION_FAILURE_CODE( ppeImgRc ), - "Failed to extract quad scan rings" ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SCAN_RING_EXTRACTION_FAIL() + .set_EXTRACTION_FAIL_PLAT( PLAT_CME ) + .set_EXTRACTION_FAILURE_CODE( ppeImgRc ), + "Failed to extract core scan rings" ); - // create a layout of rings in HOMER for consumption of SGPE - ppeImgRc = layoutRingsForSGPE( pChipHomer, - i_pRingOverride, - l_chipFuncModel, - l_ringData, - (RingDebugMode_t)l_ringDebug, - l_iplPhase, - l_qpmrHdr, - i_imgType ); + uint8_t l_iplPhase = 0 ; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, + FAPI_SYSTEM, + l_iplPhase), + "Error from FAPI_ATTR_GET for ATTR_RISK_LEVEL"); + + // create a layout of rings in HOMER for consumption of CME + ppeImgRc = layoutRingsForCME( pChipHomer, + l_chipFuncModel, + l_ringData, + (RingDebugMode_t)l_ringDebug, + l_iplPhase, + i_imgType, + i_pRingOverride ); + + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SCAN_RING_PLACEMENT_FAIL() + .set_PLACEMENT_FAIL_PLAT( PLAT_CME ) + .set_PLACEMENT_FAILURE_CODE( ppeImgRc ), + "Failed to place core scan rings" ); + + l_ringData.iv_ringBufSize = i_sizeBuf1; + ppeImgRc = getPpeScanRings( i_pImageIn, + PLAT_SGPE, + i_procTgt, + l_ringData, + i_imgType ); - FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), - fapi2::SCAN_RING_PLACEMENT_FAIL() - .set_PLACEMENT_FAIL_PLAT( PLAT_SGPE ) - .set_PLACEMENT_FAILURE_CODE( ppeImgRc ), - "Failed to place quad scan rings" ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SCAN_RING_EXTRACTION_FAIL() + .set_EXTRACTION_FAIL_PLAT( PLAT_SGPE ) + .set_EXTRACTION_FAILURE_CODE( ppeImgRc ), + "Failed to extract quad scan rings" ); - //Update CPMR Header with Scan Ring details - updateCpmrCmeRegion( pChipHomer ); + // create a layout of rings in HOMER for consumption of SGPE + ppeImgRc = layoutRingsForSGPE( pChipHomer, + i_pRingOverride, + l_chipFuncModel, + l_ringData, + (RingDebugMode_t)l_ringDebug, + l_iplPhase, + l_qpmrHdr, + i_imgType ); - //Update QPMR Header area in HOMER - updateQpmrHeader( pChipHomer, l_qpmrHdr ); + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == ppeImgRc ), + fapi2::SCAN_RING_PLACEMENT_FAIL() + .set_PLACEMENT_FAIL_PLAT( PLAT_SGPE ) + .set_PLACEMENT_FAILURE_CODE( ppeImgRc ), + "Failed to place quad scan rings" ); - //update PPMR Header area in HOMER - updatePpmrHeader( pChipHomer, l_ppmrHdr ); + //Update CPMR Header with Scan Ring details + updateCpmrCmeRegion( pChipHomer ); - //Update L2 Epsilon SCOM Registers - FAPI_TRY( populateEpsilonL2ScomReg( pChipHomer ), - "populateEpsilonL2ScomReg failed" ); + //Update QPMR Header area in HOMER + updateQpmrHeader( pChipHomer, l_qpmrHdr ); - //Update L3 Epsilon SCOM Registers - FAPI_TRY( populateEpsilonL3ScomReg( pChipHomer ), - "populateEpsilonL3ScomReg failed" ); + //update PPMR Header area in HOMER + updatePpmrHeader( pChipHomer, l_ppmrHdr ); - //populate HOMER with SCOM restore value of NCU RNG BAR SCOM Register - FAPI_TRY( populateNcuRingBarScomReg( pChipHomer, i_procTgt ), - "populateNcuRingBarScomReg failed" ); + //Update L2 Epsilon SCOM Registers + FAPI_TRY( populateEpsilonL2ScomReg( pChipHomer ), + "populateEpsilonL2ScomReg failed" ); - //validate SRAM Image Sizes of PPE's - uint32_t sramImgSize = 0; - FAPI_TRY( validateSramImageSize( pChipHomer, sramImgSize ), - "Final SRAM Image Size Check Failed" ); + //Update L3 Epsilon SCOM Registers + FAPI_TRY( populateEpsilonL3ScomReg( pChipHomer ), + "populateEpsilonL3ScomReg failed" ); - //Update CME/SGPE Flags in respective image header. - FAPI_TRY( updateImageFlags( pChipHomer, i_procTgt ), - "updateImageFlags Failed" ); + //populate HOMER with SCOM restore value of NCU RNG BAR SCOM Register + FAPI_TRY( populateNcuRingBarScomReg( pChipHomer, i_procTgt ), + "populateNcuRingBarScomReg failed" ); - //Set the Fabric IDs - FAPI_TRY(setFabricIds( pChipHomer, i_procTgt ), - "Failed to set Fabric IDs"); + //validate SRAM Image Sizes of PPE's + uint32_t sramImgSize = 0; + FAPI_TRY( validateSramImageSize( pChipHomer, sramImgSize ), + "Final SRAM Image Size Check Failed" ); - //Update the attributes storing PGPE and SGPE's boot copier offset. - FAPI_TRY( updateGpeAttributes( pChipHomer, i_procTgt ), - "Failed to update SGPE/PGPE IVPR attributes" ); - } - while(0); + //Update CME/SGPE Flags in respective image header. + FAPI_TRY( updateImageFlags( pChipHomer, i_procTgt ), + "updateImageFlags Failed" ); - FAPI_IMP("Exit p9_hcode_image_build" ); + //Set the Fabric IDs + FAPI_TRY(setFabricIds( pChipHomer, i_procTgt ), + "Failed to set Fabric IDs"); - fapi_try_exit: - return fapi2::current_err; + //Update the attributes storing PGPE and SGPE's boot copier offset. + FAPI_TRY( updateGpeAttributes( pChipHomer, i_procTgt ), + "Failed to update SGPE/PGPE IVPR attributes" ); } + while(0); + + FAPI_IMP("Exit p9_hcode_image_build" ); + +fapi_try_exit: + return fapi2::current_err; +} - } //namespace p9_hcodeImageBuild ends +} //namespace p9_hcodeImageBuild ends }// extern "C" diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index 3381bdf4e..3424a2d7d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -172,8 +172,8 @@ Producer: Machine Readable Workbook Consumers: p9_set_avsbus_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE </description> <valueType>uint8</valueType> <platInit/> @@ -1566,8 +1566,8 @@ <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id> <description> Time between invocations of the 24x7 performance collection function on - GPE1. The time (in milliseconds) is derived as - 2^PERF_24x7_INVOCATION_TIME_MS with 0 indicating the function is OFF. + GPE1. The time (in milliseconds) is derived as 2^PERF_24x7_INVOCATION_TIME_MS + with 0 indicating the function is OFF. Consumer: p9_hcode_image_build.c -> SGPE Header field @@ -1578,6 +1578,7 @@ </description> <targetType>TARGET_TYPE_SYSTEM</targetType> <valueType>uint8</valueType> + <initToZero/> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -1652,4 +1653,24 @@ <initToZero/> </attribute> <!-- ********************************************************************* --> + <attribute> + <id>ATTR_AUX_FUNC_INVOCATION_TIME_MS</id> + <description> + Time between invocations of auxiliary function on + GPE1. The time (in milliseconds) is derived as 2^ATTR_AUX_FUNC_INVOCATION_TIME_MS + with 0 indicating the function is OFF. + + Consumer: p9_hcode_image_build.c -> + SGPE Header field + + Provided by the Machine Readable Workbook to tune the collection. + + Platform default: 1 + </description> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <valueType>uint8</valueType> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> </attributes> diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml index 813022be0..3e114e76e 100644 --- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml +++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml @@ -157,6 +157,10 @@ <id>ATTR_SYSTEM_DISABLE_QUEUED_SCAN</id> <default>0x00</default> </attribute> + <attribute> + <id>ATTR_AUX_FUNC_INVOCATION_TIME_MS</id> + <default>0x01</default> + </attribute> <!-- ===================================================================== End of temporary definitions diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index cfce7e87e..929875b9b 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -32475,6 +32475,30 @@ Measured in GB</description> </attribute> <attribute> + <id>PERF_24x7_INVOCATION_TIME_MS</id> + <description> + Time between invocations of the 24x7 performance collection function on + GPE1. The time (in milliseconds) is derived as 2^PERF_24x7_INVOCATION_TIME_MS + with 0 indicating the function is OFF. + Consumer: p9_hcode_image_build.c -> + SGPE Header field + Provided by the Machine Readable Workbook to tune the collection. + Platform default: 1 + </description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> <id>CME_INSTRUCTION_TRACE_ENABLE</id> <description> Enables the SGPE Hcode to enable the CME instruction traces into the L3 @@ -32945,6 +32969,30 @@ Measured in GB</description> </attribute> <attribute> + <id>AUX_FUNC_INVOCATION_TIME_MS</id> + <description> + Time between invocations of auxiliary function on + GPE1. The time (in milliseconds) is derived as 2^ATTR_AUX_FUNC_INVOCATION_TIME_MS + with 0 indicating the function is OFF. + Consumer: p9_hcode_image_build.c -> + SGPE Header field + Provided by the Machine Readable Workbook to tune the collection. + Platform default: 1 + </description> + <simpleType> + <uint8_t> + </uint8_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_AUX_FUNC_INVOCATION_TIME_MS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> <id>PGPE_HCODE_FUNCTION_ENABLE</id> <description> Enables the PGPE Hcode to physically perform frequency and voltage diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 61f3fec4f..d5b8454d6 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -918,6 +918,8 @@ <attribute><id>POUND_W_STATIC_DATA_ENABLE</id></attribute> <attribute><id>PGPE_HCODE_FUNCTION_ENABLE</id></attribute> <attribute><id>SYSTEM_DISABLE_QUEUED_SCAN</id></attribute> + <attribute><id>PERF_24x7_INVOCATION_TIME_MS</id></attribute> + <attribute><id>AUX_FUNC_INVOCATION_TIME_MS</id></attribute> </targetType> <!-- enc-node-power9 --> |
