SW209368 : INITPROC: Hostboot - High Priority HW Init Procedures for week of 6/11

    proc_stop_deadman_timer.C (v1.8)
    proc_cen_frame_lock.C (v1.16)
    cen_scom_addresses.H (v1.61)
    p8_ocb_init.C (v1.7)
    p8_pmc_init.C (v1.35)

Change-Id: I5cf18c5a7027f2b2b1fb1466cd688674c13f7de3
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5036
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 328 insertions, 116 deletions

diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
index fda8bcc98..6708a8a07 100644
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
+++ b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_stop_deadman_timer.C,v 1.7 2012/10/24 22:23:37 jmcgill Exp $
+// $Id: proc_stop_deadman_timer.C,v 1.8 2013/06/05 14:40:54 jeshua Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -180,6 +180,23 @@ extern "C"
                 }
             }
 
+            // Reset the SBE so it can be used for MPIPL if needed
+            rc_ecmd |= data.flushTo0();
+            rc_ecmd |= data.setBit(0);
+
+            if(rc_ecmd)
+            {
+                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, PORE_SBE_RESET_0x000E0002, data);
+            if(!rc.ok())
+            {
+                FAPI_ERR("Scom error resetting SBE\n");
+                break;
+            }
+            
         } while (0);
 
         // mark function exit
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index a26cb6b68..5de100b6f 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-/// $Id: proc_cen_framelock.C,v 1.13 2013/04/28 05:48:24 baysah Exp $
+/// $Id: proc_cen_framelock.C,v 1.16 2013/06/05 18:15:39 baysah Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -2007,7 +2007,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
     }
 
 
-    // Return bad code from while loops here, before the get overwritten by the procedure EXIT scoms below
+    // Return bad code from while loops here, before it gets overwritten by the procedure EXIT scoms below
     if (l_rc)
     {
         //FAPI_DBG(" HELLO...THIS IS A BAD RETURN CODE");
@@ -2043,14 +2043,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            // return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firact0_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action0 Register");
-            // return l_rc;
+            return l_rc;
         }
 
 
@@ -2069,24 +2069,25 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mci_data.setBit(20);    //Scom Register parity error
         l_ecmdRc |= mci_data.setBit(22);    //mcicfgq parity error
         l_ecmdRc |= mci_data.setBit(23);    //Replay Buffer Overrun
+        l_ecmdRc |= mci_data.setBit(24);    //MCIFIRQ_MCS_RECOVERABLE_ERROR
         l_ecmdRc |= mci_data.setBit(27);    //MCS Command List Timeout due to PowerBus
         l_ecmdRc |= mci_data.setBit(35);    //PowerBus Write Data Buffer CE
         l_ecmdRc |= mci_data.setBit(36);    //PowerBus Write Data Buffer UE
-        l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
+        //l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error (On 5/06/2013 changed this fir to xstop, have to re-eval for Murano dd2)
         l_ecmdRc |= mci_data.copy(mci_mask);
         if (l_ecmdRc)
         {
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            //return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firact1_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action1 Register");
-            //return l_rc;
+            return l_rc;
         }
 
 
@@ -2106,14 +2107,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCS Mode4 Register",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            //return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mcs_mode4_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCS Mode4 Register");
-            //return l_rc;
+            return l_rc;
         }
 
 
@@ -2180,14 +2181,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MCI FIRs",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            // return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firmask_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Mask Register");
-            //return l_rc;
+            return l_rc;
         }
 
 
@@ -2210,14 +2211,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MBI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            //return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_cen_mbi_firact1_reg(i_mem_target, mbi_data, mbi_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Action1 Register");
-            //return l_rc;
+            return l_rc;
         }
 
 
@@ -2251,14 +2252,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MBI FIRs",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-            // return l_rc;
+            return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_cen_mbi_firmask_reg(i_mem_target, mbi_data, mbi_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Mask Register");
-            //return l_rc;
+            return l_rc;
         }
 
 
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index a06f96e50..807705d3f 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.57 2013/04/11 23:41:36 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.61 2013/06/10 22:36:15 lapietra Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,16 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.60   | dcadiga  |10-Jun-13| Added DP18 Read Diagnostic Configuration 5
+//  1.59   | mwuu     |07-Jun-13| Added PHY N/PFET SLICE broadcast regs,
+//         |          |         | renamed DATA_BIT_ENABLE1 regs to match address,
+//         |          |         | added DATA_BIT_DIR0, and ADR_BIT_ENABLE regs,
+//         |          |         | added ADR_OUTPUT_DRIVER_FORCE_VALUE regs,
+//         |          |         | added ADR_OUTPUT_FORCE_ATEST_CNTL regs,
+//         |          |         | added ADR_IO_FET_SLICE_EN_MAP regs,
+//         |          |         | for ADR/DP18 flush workaround.
+//  1.58   | bellows  |28-May-13| Added PHY power down regs
+//  1.57   | jdsloat  |15-May-13| Added WC_CONFIG1 and WC_CONFIG2 regs
 //  1.56   | jdsloat  |11-Apr-13| Added DQS Gate Delay Values
 //  1.55   | jdsloat  |04-Apr-13| Added DPHY01_DDRPHY_WC_CONFIG3 regs
 //  1.54   | jdsloat  |03-Apr-13| Fixed MR Sec shadow regs
@@ -456,6 +466,10 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F,                  ULL(0x8000C0350301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F,                  ULL(0x8001C0350301143F) );
 
+CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG1_P0_0x8000CC010301143F,                  ULL(0x8000CC010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG1_P1_0x8001CC010301143F,                  ULL(0x8001CC010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG2_P0_0x8000CC020301143F,                  ULL(0x8000CC020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG2_P1_0x8001CC020301143F,                  ULL(0x8001CC020301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F,                  ULL(0x8000CC050301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F,                  ULL(0x8001CC050301143F) );
 
@@ -535,6 +549,12 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143F,              ULL(0x8001C00F0301143F) );
 
 //------------------------------------------------------------------------------
+// PHY POWER Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F,              ULL(0x8000C0100301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F,              ULL(0x8001C0100301143F) );
+
+//------------------------------------------------------------------------------
 //      MBA Fault Isolation Register
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MBAFIRQ_0x03010600           , ULL(0x03010600) );
@@ -1132,6 +1152,9 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,	   ULL(0
 //------------------------------------------------------------------------------
 //      NFET Slice Registers
 //------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_5_0x80003C780301143F , ULL(0x80003C780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_5_0x80013C780301143F , ULL(0x80013C780301143F) );
+
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F , ULL(0x800000780301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_0x800004780301143F , ULL(0x800004780301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_0x800008780301143F , ULL(0x800008780301143F) );
@@ -1146,6 +1169,9 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_0x800110780301143F , UL
 //------------------------------------------------------------------------------
 //      PFET Slice Registers
 //------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_5_0x80003C790301143F , ULL(0x80003C790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_5_0x80013C790301143F , ULL(0x80013C790301143F) );
+
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_0x800000790301143F , ULL(0x800000790301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_0x800004790301143F , ULL(0x800004790301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_0x800008790301143F , ULL(0x800008790301143F) );
@@ -1158,6 +1184,32 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_0x80010C790301143F , UL
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F , ULL(0x800110790301143F) );
 
 //------------------------------------------------------------------------------
+//      ADR IO FET Slice Enable Map Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_3_0x80007C200301143F , ULL(0x80007C200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_3_0x80007C200301143F , ULL(0x80007C210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_3_0x80017C200301143F , ULL(0x80017C200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_3_0x80017C200301143F , ULL(0x80017C210301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_0x800040200301143F , ULL(0x800040200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_0x800044200301143F , ULL(0x800044200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_0x800048200301143F , ULL(0x800048200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_0x80004C200301143F , ULL(0x80004C200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_0x800040200301143F , ULL(0x800040210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_0x800044200301143F , ULL(0x800044210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_0x800048200301143F , ULL(0x800048210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_0x80004C200301143F , ULL(0x80004C210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0_0x800140200301143F , ULL(0x800140200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1_0x800144200301143F , ULL(0x800144200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2_0x800148200301143F , ULL(0x800148200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3_0x80014C200301143F , ULL(0x80014C200301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0_0x800140200301143F , ULL(0x800140210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1_0x800144200301143F , ULL(0x800144210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2_0x800148200301143F , ULL(0x800148210301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3_0x80014C200301143F , ULL(0x80014C210301143F) );
+
+
+//------------------------------------------------------------------------------
 //      DFT Wrap Status Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_0x8000001D0301143F , ULL(0x8000001D0301143F) );
@@ -1172,6 +1224,42 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_0x80010C1D0301143F , ULL
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_0x8001101D0301143F , ULL(0x8001101D0301143F) );
 
 //------------------------------------------------------------------------------
+//      ADR Output Force ATEST Control Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_0x800080350301143F , ULL(0x800080350301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_0x800084350301143F , ULL(0x800084350301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0_0x800180350301143F , ULL(0x800180350301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1_0x800184350301143F , ULL(0x800184350301143F) );
+
+//------------------------------------------------------------------------------
+//      ADR Output Driver Force Value Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_0x800080360301143F , ULL(0x800080360301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_0x800084360301143F , ULL(0x800084360301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_0x800080370301143F , ULL(0x800080370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_0x800084370301143F , ULL(0x800084370301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0_0x800180360301143F , ULL(0x800180360301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1_0x800184360301143F , ULL(0x800184360301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0_0x800180370301143F , ULL(0x800180370301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1_0x800184370301143F , ULL(0x800184370301143F) );
+
+//------------------------------------------------------------------------------
+//      ADR Bit Enable Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_3_0x80007C000301143F , ULL(0x80007C000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_3_0x80017C000301143F , ULL(0x80017C000301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_0x800040000301143F , ULL(0x800040000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_0x800044000301143F , ULL(0x800044000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_0x800048000301143F , ULL(0x800048000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_0x80004C000301143F , ULL(0x80004C000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P1_ADR0_0x800140000301143F , ULL(0x800140000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P1_ADR1_0x800144000301143F , ULL(0x800144000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P1_ADR2_0x800148000301143F , ULL(0x800148000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_BIT_ENABLE_P1_ADR3_0x80014C000301143F , ULL(0x80014C000301143F) );
+
+//------------------------------------------------------------------------------
 //      Data Bit Enable 0 Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_0x800000000301143F , ULL(0x800000000301143F) );
@@ -1188,16 +1276,33 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_0x800110000301143F , UL
 //------------------------------------------------------------------------------
 //      Data Bit Enable 1 Registers
 //------------------------------------------------------------------------------
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_0x800000010301143F , ULL(0x800000010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1_0x800004010301143F , ULL(0x800004010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2_0x800008010301143F , ULL(0x800008010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3_0x80000C010301143F , ULL(0x80000C010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4_0x800010010301143F , ULL(0x800010010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0_0x800100010301143F , ULL(0x800100010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1_0x800104010301143F , ULL(0x800104010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2_0x800108010301143F , ULL(0x800108010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3_0x80010C010301143F , ULL(0x80010C010301143F) );
-CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_0x800110010301143F , ULL(0x800110010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_0x800000010301143F , ULL(0x800000010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_0x800004010301143F , ULL(0x800004010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_0x800008010301143F , ULL(0x800008010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_0x80000C010301143F , ULL(0x80000C010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_0x800010010301143F , ULL(0x800010010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_0x800100010301143F , ULL(0x800100010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_0x800104010301143F , ULL(0x800104010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_0x800108010301143F , ULL(0x800108010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_0x80010C010301143F , ULL(0x80010C010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_0x800110010301143F , ULL(0x800110010301143F) );
+
+//------------------------------------------------------------------------------
+//      Data Bit Direction 0 Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_0_5_0x80003C020301143F , ULL(0x80003C020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_0_5_0x80013C020301143F , ULL(0x80013C020301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_0_0x800000020301143F , ULL(0x800000020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_1_0x800004020301143F , ULL(0x800004020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_2_0x800008020301143F , ULL(0x800008020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_3_0x80000C020301143F , ULL(0x80000C020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_4_0x800010020301143F , ULL(0x800010020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_0_0x800100020301143F , ULL(0x800100020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_1_0x800104020301143F , ULL(0x800104020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_2_0x800108020301143F , ULL(0x800108020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_3_0x80010C020301143F , ULL(0x80010C020301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P1_4_0x800110020301143F , ULL(0x800110020301143F) );
 
 //------------------------------------------------------------------------------
 //      DQS CLK Phase Rotators 0
@@ -1603,6 +1708,26 @@ CONST_UINT64_T( CEN_SCAN_PLL_BNDY_FUNC,             ULL(0x0810080800000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_GPTR_TIME_REP_NO_PLL,          ULL(0x0FE0023000000000) );
 
+//------------------------------------------------------------------------------
+////    DPHYXX_DDRPHY_DP18_RD_DIA_CONFIG5 Registers
+////------------------------------------------------------------------------------
+//
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_0x800000120301143F , ULL(0x800000120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_0x800004120301143F , ULL(0x800004120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_0x800008120301143F , ULL(0x800008120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_0x80000C120301143F , ULL(0x80000C120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_0x800010120301143F , ULL(0x800010120301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_0x800100120301143F , ULL(0x800100120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_0x800104120301143F , ULL(0x800104120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_0x800108120301143F , ULL(0x800108120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_0x80010C120301143F , ULL(0x80010C120301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_0x800110120301143F,  ULL(0x800110120301143F) );
+
+
+
+
 #endif
 
 
@@ -1612,6 +1737,25 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.61  2013/06/10 22:36:15  lapietra
+Added DP18 Cfg 5 Regs
+
+Revision 1.60  2013/06/10 14:51:12  mwuu
+Added PHY N/PFET SLICE broadcast regs,
+renamed DATA_BIT_ENABLE1 regs to match address,
+added DATA_BIT_DIR0, and ADR_BIT_ENABLE regs,
+added ADR_OUTPUT_DRIVER_FORCE_VALUE regs,
+added ADR_OUTPUT_FORCE_ATEST_CNTL regs,
+added ADR_IO_FET_SLICE_EN_MAP regs
+for ADR/DP18 flush workaround.
+
+Revision 1.59  2013/05/28 12:59:24  bellows
+Added power down regs
+
+Revision 1.58  2013/05/15 14:49:54  jdsloat
+
+Added WC_CONFIG1 and WC_CONFIG2 regs
+
 Revision 1.57  2013/04/11 23:41:36  jdsloat
 Added DQS Gate Delay Values
 
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C
index 59745ec57..137f62ee5 100755
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_ocb_init.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_ocb_init.C,v 1.5 2013/04/23 16:30:58 jimyac Exp $
+// $Id: p8_ocb_init.C,v 1.7 2013/06/05 17:39:01 jimyac Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_ocb_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -242,7 +242,7 @@ ReturnCode proc_ocb_setup(const Target& i_target,  const uint8_t  i_ocb_chan,
   //    bit 4 => ocb_stream_mode        (0=disabled 1=enabled)
   //    bit 5 => ocb_stream_type        (0=linear   1=circular)
   // --------------------------------------------------------------------
-  l_ecmdRc |= mask_or.flushTo0();
+  l_ecmdRc |= mask_or.flushTo0();  
   l_ecmdRc |= mask_and.flushTo1();
 
   if (i_ocb_type == OCB_TYPE_LIN) {                    // linear non-streaming
@@ -585,7 +585,9 @@ ReturnCode proc_ocb_reset(const Target& i_target) {
   // Set Interrupt Source Mask Registers 0 & 1 
   // OIMR0/1 @ 0X0006A006 & 0X0006A016
   // -----------------------------------------
-  l_ecmdRc = data.flushTo1();
+  l_ecmdRc  = data.flushTo0();
+  l_ecmdRc |= data.setWord(0, 0xFFFFFFFF);  // keep word1 0's for simics
+    
   if (l_ecmdRc) {
     FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
     rc.setEcmdError(l_ecmdRc);
@@ -729,3 +731,16 @@ ReturnCode proc_ocb_reset(const Target& i_target) {
 
 } //end extern C
 
+/*
+*************** Do not edit this area ***************
+This section is automatically updated by CVS when you check in this file.
+Be sure to create CVS comments when you commit so that they can be included here.
+
+$Log: p8_ocb_init.C,v $
+Revision 1.7  2013/06/05 17:39:01  jimyac
+fixed SW207126 - simics issue of writing non-zero value to reserved bits
+
+
+
+
+*/
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C
index 66eb704e7..faa456221 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pmc_init.C,v 1.33 2013/05/24 10:53:38 pchatnah Exp $
+// $Id: p8_pmc_init.C,v 1.35 2013/06/07 19:17:24 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -110,7 +110,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             "ATTR_FREQ_PB",
                             NULL,
                             attr_proc_nest_frequency);
-        
+
         //----------------------------------------------------------
         GETATTR_DEFAULT(    ATTR_PM_SPIVID_FREQUENCY,
                             "ATTR_PM_SPIVID_FREQUENCY",
@@ -119,7 +119,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             default_spivid_frequency);
 
         // calculation of clock divider
-        attr_pm_spivid_clock_divider =  (attr_proc_nest_frequency / 
+        attr_pm_spivid_clock_divider =  (attr_proc_nest_frequency /
                                             (attr_pm_spivid_frequency*8)-1 );
 
 
@@ -127,7 +127,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             "ATTR_PM_SPIVID_CLOCK_DIVIDER",
                             &l_pTarget,
                             attr_pm_spivid_clock_divider);
-                            
+
         //----------------------------------------------------------
         // Delay between command and status frames of a SPIVID WRITE operation
         // (binary in nanoseconds)
@@ -137,7 +137,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             &l_pTarget,
                             attr_pm_spivid_interframe_delay_write_status,
                             default_spivid_interframe_delay_write_status);
-	   
+
         // Delay is computed as: (value * ~100ns_hang_pulse)
         // +0/-~100ns_hang_pulse time
         // Thus, value = delay / 100
@@ -148,7 +148,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE",
                             &l_pTarget,
                             attr_pm_spivid_interframe_delay_write_status_value);
-        
+
         //----------------------------------------------------------
 
         // Delay between SPIVID reture attempts when WRITE command status
@@ -159,10 +159,10 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             &l_pTarget,
                             attr_pm_spivid_inter_retry_delay,
                             default_spivid_inter_retry_delay);
-        
-        FAPI_DBG (" attr_pm_spivid_inter_retry_delay value in config function = 0x%x", 
+
+        FAPI_DBG (" attr_pm_spivid_inter_retry_delay value in config function = 0x%x",
                             attr_pm_spivid_inter_retry_delay );
-                            
+
         // Delay is computed as: (value * ~100ns_hang_pulse)
         // +0/-~100ns_hang_pulse time
         // Thus, value = delay / 100
@@ -173,7 +173,7 @@ pmc_config_spivid_settings(const Target& l_pTarget)
                             "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE",
                             &l_pTarget,
                             attr_pm_spivid_inter_retry_delay_value);
-        
+
         FAPI_INF("Exiting the config function");
 
     } while(0);
@@ -267,26 +267,26 @@ pmc_reset_function(const fapi::Target& i_target1 , const fapi::Target& i_target2
             //    break;
             //}
 
-	  if (i_target2.getType() != TARGET_TYPE_NONE  )
+      if (i_target2.getType() != TARGET_TYPE_NONE  )
             {            rc = FAPI_ATTR_GET(ATTR_PROC_DCM_INSTALLED, &i_target2, attr_dcm_installed_2);
-	      if (rc)
-		{
-		  FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc);
-		  break;
-		}
-	      FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 );
-	      
-	      if (attr_dcm_installed_2 != 1)
-		{
-		  FAPI_ERR ("config error:  DCM_INSTALLED target2 does not match target1");
-		  FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR);
-		  break;
-		}
-	      
-	      dcm = true;
-	    }
-        }
-	
+          if (rc)
+        {
+          FAPI_ERR("fapiGetAttribute of ATTR_DCM_INSTALLED with rc = 0x%x", (uint32_t)rc);
+          break;
+        }
+          FAPI_INF (" ATTR_DCM_INSTALLED value in reset function = 0x%x", attr_dcm_installed_2 );
+
+          if (attr_dcm_installed_2 != 1)
+        {
+          FAPI_ERR ("config error:  DCM_INSTALLED target2 does not match target1");
+          FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCRESET_DCM_INSTALL_ERROR);
+          break;
+        }
+
+          dcm = true;
+        }
+        }
+
         ////////////////////////////////////////////////////////////////////////////
         // 1) Determine master chip and slave chip. By reading the SPIVID_EN attribute
         //    If SPIVID_EN is != 0 then that target is master
@@ -1668,7 +1668,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
                     &i_target1,
                     attr_pm_spivid_port_enable,
                     default_spivid_port_enable );
-                    
+
            //----------------------------------------------------------
        GETATTR(     ATTR_PM_SPIVID_CLOCK_DIVIDER,
                     "ATTR_PM_SPIVID_CLOCK_DIVIDER",
@@ -1680,7 +1680,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
                    "ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE",
                     &i_target1,
                     attr_pm_spivid_interframe_delay_write_status_value);
-        
+
             //----------------------------------------------------------
         GETATTR(    ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE,
                     "ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE",
@@ -1758,7 +1758,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
         }
 
         any_error = data.getDoubleWord(0);
-    
+
         if (any_error)
         {
            FAPI_ERR(" PMC_FIR has error(s) active.  0x%16llX ", data.getDoubleWord(0));
@@ -1787,7 +1787,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             rc.setEcmdError(e_rc);
             break;
         }
-    
+
         FAPI_INF("  PMC_O2S_CTRL_REG0A / PMC_SPIV_CTRL_REG0A  Configuration");
         FAPI_INF("    frame size                 => %d ",  o2s_frame_size);
         FAPI_INF("    o2s_out_count1             => %d ",  o2s_out_count1);
@@ -1818,7 +1818,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed.");
             break;
         }
-    
+
         e_rc  = data.insertFromRight(o2s_out_count2,00,6);
         e_rc |= data.insertFromRight(o2s_in_delay2 ,06,6);
         e_rc |= data.insertFromRight(o2s_in_count2 ,12,6);
@@ -1834,7 +1834,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
         FAPI_INF("    o2s_in_delay2              => %d ",  o2s_in_delay2 );
         FAPI_INF("    o2s_in_count2              => %d ",  o2s_in_count2 );
 
-	rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data );
+        rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG0B_0x00062051, data );
         if (rc)
         {
             FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0B_0x00062051) failed.");
@@ -1847,7 +1847,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG0B_0x00062041) failed.");
             break;
         }
-    
+
         //  ******************************************************************
         //     - set PMC_O2S_CTRL_REG1
         //  ******************************************************************
@@ -1872,17 +1872,17 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             rc.setEcmdError(e_rc);
             break;
         }
-    
+
         o2s_nr_of_frames++ ;
- 	FAPI_INF("  PMC_O2S_CTRL_REG1 / PMC_SPIV_CTRL_REG1 ");
- 	FAPI_INF("    o2s_bridge_enable           => %d ",  o2s_bridge_enable );
-         FAPI_INF("    o2s_clk_pol                 => %d ",  o2s_clk_pol    );
-         FAPI_INF("    o2s_clk_pha                 => %d ",  o2s_clk_pha    );
-         FAPI_INF("    o2s_clk_divider             => 0x%x", o2s_clk_divider);
-         FAPI_INF("    o2s_nr_of_frames            => %d ",  o2s_nr_of_frames);
-         FAPI_INF("    o2s_port_enable             => %d ",  o2s_port_enable);
-
-                
+        FAPI_INF("  PMC_O2S_CTRL_REG1 / PMC_SPIV_CTRL_REG1 ");
+        FAPI_INF("    o2s_bridge_enable           => %d ",  o2s_bridge_enable );
+        FAPI_INF("    o2s_clk_pol                 => %d ",  o2s_clk_pol    );
+        FAPI_INF("    o2s_clk_pha                 => %d ",  o2s_clk_pha    );
+        FAPI_INF("    o2s_clk_divider             => 0x%x", o2s_clk_divider);
+        FAPI_INF("    o2s_nr_of_frames            => %d ",  o2s_nr_of_frames);
+        FAPI_INF("    o2s_port_enable             => %d ",  o2s_port_enable);
+
+
         rc = fapiPutScom(i_target1, PMC_O2S_CTRL_REG1_0x00062052, data );
         if (rc)
         {
@@ -1896,7 +1896,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed.");
             break;
         }
-    
+
         //  ******************************************************************
         //     - set PMC_O2S_CTRL_REG2
         //  ******************************************************************
@@ -1915,7 +1915,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             rc.setEcmdError(e_rc);
             break;
         }
-    
+
 
         FAPI_INF("  PMC_O2S_CTRL_REG2_ / PMC_SPIV_CTRL_REG2Configuration");
         FAPI_INF("    o2s_inter_frame_delay       => %d ",  o2s_inter_frame_delay );
@@ -2071,6 +2071,39 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
         }
 
         //  ******************************************************************
+        //     - write PMC_RAIL_BOUNDS_0x00062003 to place open defaults into
+        //          the rail bounds as the hardware defaults to both being
+        //          00 --- which may be a turbo frequency.
+        //  ******************************************************************
+        //  Added for SW207759
+        rc = fapiGetScom(i_target1, PMC_RAIL_BOUNDS_0x00062003, data );
+        if (rc)
+        {
+            FAPI_ERR("fapiGetScom(PMC_RAIL_BOUNDS_0x00062003) failed.");
+            break;
+        }
+
+        e_rc |= data.setByte(0, -128);  // Pmin
+        e_rc |= data.setByte(1,  127);  // Pmax
+        if (e_rc)
+        {
+            FAPI_ERR("ecmdDataBufferBase error setting up PMC_RAIL_BOUNDS_0x00062003 on Master init");
+            rc.setEcmdError(e_rc);
+            break;
+        }
+
+        FAPI_INF("  PMC_RAIL_BOUNDS_0x00062003 Configuration");
+        FAPI_INF("    pmin_rail       => 0x%x ",  data.getByte(0));
+        FAPI_INF("    pmax_rail       => 0x%x ",  data.getByte(1));
+
+        rc = fapiPutScom(i_target1, PMC_RAIL_BOUNDS_0x00062003, data );
+        if (rc)
+        {
+            FAPI_ERR("fapiPutScom(PMC_RAIL_BOUNDS_0x00062003) failed.");
+            break;
+        }
+
+        //  ******************************************************************
         //     - write PMC_MODE_REG
         //  ******************************************************************
         rc = fapiGetScom(i_target1, PMC_MODE_REG_0x00062000, data );
@@ -2131,14 +2164,14 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
         {
             dcm = 0 ;
         }
-    
+
         if (dcm == 1)
         {
             if (is_master)
-            {            
+            {
                 FAPI_INF ("**** Setting up DCM Master ****");
             }
-            else 
+            else
             {
                 FAPI_INF ("**** Setting up DCM Slave ****");
             }
@@ -2187,7 +2220,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
                 FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed.");
                 break;
             }
-	
+
             // Force the port enables on the slave or else the SPIVID on the slave
             // chip will hang
             if (is_slave)
@@ -2219,7 +2252,7 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
                 FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG1_0x00062042) failed.");
                 break;
             }
-	
+
             //  ******************************************************************
             //     - write PMC_INTCHP_CTRL_REG1
             //  ******************************************************************
@@ -2278,23 +2311,21 @@ fapi::ReturnCode pmc_init_function(const fapi::Target& i_target1 )
             FAPI_DBG("    INTERCHIP_ECC_CHECK_EN                     =>   %d ",  one          );
             FAPI_DBG("    INTERCHIP_MSG_RCV_OVERFLOW_CHECK_EN        =>   %d ",  one          );
             FAPI_DBG("    INTERCHIP_ECC_UE_BLOCK_EN                  =>   %d ",  one          );
-	
+
             rc = fapiPutScom(i_target1, PMC_INTCHP_CTRL_REG4_0x00062012, data );
             if (rc)
             {
                 FAPI_ERR("fapiPutScom(PMC_INTCHP_CTRL_REG4_0x00062012) failed.");
                 break;
-	        }
-	FAPI_DBG(" before exiting pmc_init PMC_INTCHP_CTRL_REG4_0x00062012  =>0x%16llx", data.getDoubleWord(0));
+            }
+            FAPI_DBG(" before exiting pmc_init PMC_INTCHP_CTRL_REG4_0x00062012  =>0x%16llx", data.getDoubleWord(0));
         } // dcm
-    
-    } while(0);
 
+    } while(0);
 
 
     FAPI_INF ("Done with the init");
-    FAPI_INF ("Done with the init");
-    return rc; 
+    return rc;
 
 }
 
@@ -2330,15 +2361,15 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32
                 break;
             }
 
-	    if ( i_target2.getType() != TARGET_TYPE_NONE ) 
-	      {
-		rc = pmc_config_spivid_settings(i_target2);
-		if (rc)
-		  {
-		    FAPI_ERR("Error from pmc_config_spivid_settings for target2");
-		    break;
-		  }
-	      }
+            if ( i_target2.getType() != TARGET_TYPE_NONE )
+            {
+                rc = pmc_config_spivid_settings(i_target2);
+                if (rc)
+                {
+                    FAPI_ERR("Error from pmc_config_spivid_settings for target2");
+                    break;
+                }
+            }
         }
 
         // ------------------------------------------------
@@ -2348,27 +2379,22 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32
         {
             FAPI_INF("Executing p8_pmc_init for Target %s ...", i_target1.toEcmdString());
             rc = pmc_init_function(i_target1);
-	    //            FAPI_INF("Reacged here");
             if (rc)
             {
                 FAPI_ERR("Error from pmc_init_function for target1");
                 break;
             }
 
-
-
-	    if ( i_target2.getType() != TARGET_TYPE_NONE ) 
-	      {
-		FAPI_INF("Executing p8_pmc_init for target %s ...", i_target2.toEcmdString());
-		rc = pmc_init_function(i_target2);
-		if (rc)
-		  {
-		    FAPI_ERR("Error from pmc_init_function for target2");
-		    break;
-		  }
-	      }
-
-
+            if ( i_target2.getType() != TARGET_TYPE_NONE )
+            {
+                FAPI_INF("Executing p8_pmc_init for Target %s ...", i_target2.toEcmdString());
+                rc = pmc_init_function(i_target2);
+                if (rc)
+                {
+                  FAPI_ERR("Error from pmc_init_function for target2");
+                  break;
+                }
+            }
         }
 
         /// -------------------------------
@@ -2395,7 +2421,7 @@ p8_pmc_init(const fapi::Target& i_target1, const fapi::Target& i_target2, uint32
         }
 
     } while(0);
-    //    FAPI_INF("im here ");   
+    //    FAPI_INF("im here ");
     return rc;
 
 } // end p8_pmc_init
@@ -2408,6 +2434,15 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_pmc_init.C,v $
+Revision 1.35  2013/06/07 19:17:24  stillgs
+
+Fix swap of Pmin and PMax rail settings
+
+Revision 1.34  2013/06/05 21:09:03  stillgs
+
+Fix for SW207759:  Added setting of PMC Rail Bounds register to +127/-127
+to deal with hardware reset values being 0s --- the turbo value for P8 machines
+
 Revision 1.33  2013/05/24 10:53:38  pchatnah
 Assigning boolean variables to false by default