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| author | Christian Geddes <crgeddes@us.ibm.com> | 2017-09-08 16:22:35 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-09-13 10:27:50 -0400 |
| commit | aed2bbff258bf51b3f41464f5883742839cbdbc5 (patch) | |
| tree | 9e0a64ede93e38993eff6f9f8d7d588ef066cd2a /src | |
| parent | c6ca45b7a40844fd978355c52f817943e249b8e9 (diff) | |
| download | talos-hostboot-aed2bbff258bf51b3f41464f5883742839cbdbc5.tar.gz talos-hostboot-aed2bbff258bf51b3f41464f5883742839cbdbc5.zip | |
Fix RTC numbers for extra core state setup we do for MPIPL
There was a whole laundry list of scoms we were doing to the cores
to get the PM complex in the correct state for MPIPL. Many of these
workarounds have been removed but a few we could not. In order to move
forward I created new stories for the remaining workaround to remove
so we can close the previous story that contained all of the workaround
Change-Id: I66f02d867391afc22961a7de02b94293000607ae
RTC:171763
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45983
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/usr/isteps/istep06/host_discover_targets.C | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/usr/isteps/istep06/host_discover_targets.C b/src/usr/isteps/istep06/host_discover_targets.C index 518db6cd4..7929acde8 100644 --- a/src/usr/isteps/istep06/host_discover_targets.C +++ b/src/usr/isteps/istep06/host_discover_targets.C @@ -229,6 +229,7 @@ errlHndl_t clearInterruptReg() for(const auto & l_chip : l_procChips) { + //TODO 179645 Determine why we have to clear PERV_ATTN_INTERRUPT_REG during dump MPIPLs on DD2 l_err = deviceWrite(l_chip, &CLEAR_SCOM, MASK_SIZE, @@ -319,7 +320,7 @@ errlHndl_t powerDownSlaveQuads() TARGETING::TYPE_EX, true); - //TODO 171763 Core state setup for MPIPL should be done in a HWP + //TODO 171340 Need to rm clear of PM_EXIT bit in EX_0_CME_SCOM_SICR_SCOM1 reg during MPIPL for(const auto & l_ex_child : l_exChildren) { // Clear bits 4 & 5 of CME_SCOM_SICR which sets PM_EXIT for C0 and C1 respectively |
