diff options
| author | Thi Tran <thi@us.ibm.com> | 2015-09-02 10:57:41 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-09-14 21:06:59 -0500 |
| commit | a67ea7384ec6c326cfe553ee235b13eb434adee7 (patch) | |
| tree | 32bf3967437a39da28e75feb8717c0693ea2a479 /src | |
| parent | 66921b4bc0df457e3ea44b804c8450b3d120e3b7 (diff) | |
| download | talos-hostboot-a67ea7384ec6c326cfe553ee235b13eb434adee7.tar.gz talos-hostboot-a67ea7384ec6c326cfe553ee235b13eb434adee7.zip | |
SW309472: INITPROC: HWP: DDR4 updates and #DS updates for DRAM initialization
CQ:SW309472
Change-Id: Ifddb0ede213eec6583e10a129ed287a543456605
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19164
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19165
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
14 files changed, 6407 insertions, 1618 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile index 30863cdaf..fea2d0120 100644 --- a/src/usr/hwpf/hwp/dram_training/makefile +++ b/src/usr/hwpf/hwp/dram_training/makefile @@ -28,6 +28,7 @@ ROOTPATH = ../../../../.. MODULE = dram_training CFLAGS += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM) +CFLAGS += -DFAPI_DDR4 ## support for Targeting and fapi EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer @@ -79,6 +80,7 @@ OBJS += mss_mcbist_address.o OBJS += mss_lrdimm_funcs.o OBJS += cen_stopclocks.o OBJS += mss_ddr4_pda.o +OBJS += mss_ddr4_funcs.o OBJS += mss_mrs6_DDR4.o # diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H index 5c71873c9..327b8940e 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_ddr4_funcs.H,v 1.3 2013/10/10 20:28:25 bellows Exp $ +// $Id: mss_ddr4_funcs.H,v 1.5 2015/09/04 18:14:20 thi Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2013 @@ -44,6 +44,8 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // | | | +// 1.5 | 09/04/15 | thi | Fix Doxygen +// 1.4 | 03/14/14 | kcook | Added DDR4 Register function support. // 1.3 | 10/10/13 | bellows | Added required CVS Id comment // 1.2 | 10/09/13 | jdsloat | Fixed argument list in function call // 1.1 | 10/04/13 | jdsloat | First revision @@ -58,15 +60,50 @@ //-------------------------------------------------------------- -// mss_mrs_load_ddr4 -// Set MRS1 settings for Rank 0 and Rank 1 -// Target = centaur.mba +// @brief Set MRS1 settings for Rank 0 and Rank 1 +// +// @param[in] i_target Reference to MBA Target. +// @param[in] i_port_number MBA port number +// @param[in/out] io_ccs_inst_cnt CCS instruction count +// +// @return ReturnCode //-------------------------------------------------------------- fapi::ReturnCode mss_mrs_load_ddr4( fapi::Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt); +//-------------------------------------------------------------- +// @brief Writes MPR pattern for inverted address location for +// training with DDR4 RDIMMs. +// +// @param[in] i_target_mba Reference to MBA Target. +// +// @return ReturnCode +//-------------------------------------------------------------- +fapi::ReturnCode mss_ddr4_invert_mpr_write( fapi::Target& i_target_mba); +//-------------------------------------------------------------- +// @brief Writes RCD control words for DDR4 register. +// +// @param[in] i_target Reference to MBA Target. +// @param[in] i_port_number MBA port number +// @param[in/out] io_ccs_inst_cnt CCS instruction count +// +// @return ReturnCode +//-------------------------------------------------------------- +fapi::ReturnCode mss_rcd_load_ddr4( + fapi::Target& i_target, + uint32_t i_port_number, + uint32_t& io_ccs_inst_cnt); + +//-------------------------------------------------------------- +// @brief Creates RCD_CNTRL_WORD attribute for DDR4 register +// +// @param[in] i_target_mba Reference to MBA Target. +// +// @return ReturnCode +//-------------------------------------------------------------- +fapi::ReturnCode mss_create_rcd_ddr4( const fapi::Target& i_target_mba); #endif /* _MSS_DDR4_FUNCS_H */ diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C index 26cc02380..e95011aee 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -20,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit.C,v 1.66 2014/05/09 16:40:04 jdsloat Exp $ +// $Id: mss_draminit.C,v 1.70 2015/09/04 01:10:11 kmack Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +30,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.70 | kmack |01-Sep-15| Fixed more RCs and removed extraneous comments +// 1.69 | kmack |28-Aug-15| Fixed an RC +// 1.68 | kmack |10-Aug-15| Moved the mss_lrdimm_ddr4_db_load call to the be included or not included based on def FAPI_LRDIMM +// 1.67 | kmack |05-Aug-15| Commented out FAPI_DDR4 code // 1.66 | jdsloat |09-MAY-14| Added an explicit 500us delay before execution of MRS cmds. // 1.65 | jdsloat |09-APL-14| Fixed ifdef around #include mss_lrdimm_ddr4_funcs.H // 1.64 | jdsloat |01-APL-14| RAS review edits/changes @@ -40,7 +46,7 @@ // 1.57 | jdsloat | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow // 1.56 | bellows | 09/16/13| Hostboot compile fix // 1.55 | kcook | 09/13/13| Updated define FAPI_LRDIMM token. -// 1.54 | kcook | 08/27/13| Removed LRDIMM support to mss_lrdimm_funcs.C. +// 1.54 | kcook | 08/27/13| Removed LRDIMM support to mss_lrdimm_funcs.C. // | | | Added check for valid rank when flagging address mirroring. // 1.53 | kcook | 08/16/13| Added LRDIMM support. Use with mss_funcs.C v1.32. // 1.52 | jdsloat | 08/07/13| Added a single rc_num check and edited a debug/error message to make firmware happy. @@ -145,48 +151,57 @@ ReturnCode mss_lrdimm_mrs_load(Target& i_target, uint32_t i_port_number, uint32_ return rc; } -#endif - -#ifndef FAPI_DDR4 -using namespace fapi; -fapi::ReturnCode mss_mrs_load_ddr4(Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt) +fapi::ReturnCode mss_lrdimm_ddr4_db_load(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt) { ReturnCode rc; - FAPI_ERR("Invalid exec of mrs_load_ddr4 %s!", i_target.toEcmdString()); + FAPI_ERR("Invalid exec of lrdimm_ddr4_db_load %s!", i_target.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; } -fapi::ReturnCode mss_rcd_load_ddr4(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt) -{ - ReturnCode rc; +#endif + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - FAPI_ERR("Invalid exec of rcd_load_ddr4 %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; -} -fapi::ReturnCode mss_lrdimm_ddr4_db_load(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt) -{ - ReturnCode rc; - FAPI_ERR("Invalid exec of lrdimm_ddr4_db_load %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; -} -fapi::ReturnCode mss_ddr4_invert_mpr_write(Target& i_target) -{ - ReturnCode rc; - FAPI_ERR("Invalid exec of ddr4_invert_mpr_write %s!", i_target.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); - return rc; -} -#endif //---------------------------------------------------------------------- // Constants @@ -197,7 +212,7 @@ const uint8_t MAX_NUM_RANK_PAIR = 4; const uint8_t MAX_NUM_LR_RANKS = 8; const uint8_t MRS0_BA = 0; const uint8_t MRS1_BA = 1; -const uint8_t MRS2_BA = 2; +const uint8_t MRS2_BA = 2; const uint8_t MRS3_BA = 3; const uint8_t MRS4_BA = 4; const uint8_t MRS5_BA = 5; @@ -233,13 +248,13 @@ ReturnCode mss_draminit(Target& i_target) rc = mss_draminit_cloned(i_target); - // If mss_unmask_draminit_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_errors runs clean, - // it will just return the passed in rc. - rc = mss_unmask_draminit_errors(i_target, rc); + // If mss_unmask_draminit_errors gets it's own bad rc, + // it will commit the passed in rc (if non-zero), and return it's own bad rc. + // Else if mss_unmask_draminit_errors runs clean, + // it will just return the passed in rc. + rc = mss_unmask_draminit_errors(i_target, rc); - return rc; + return rc; } ReturnCode mss_draminit_cloned(Target& i_target) @@ -257,7 +272,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) uint8_t rank_pair_group = 0; uint8_t bit_position = 0; ecmdDataBufferBase data_buffer_64(64); - ecmdDataBufferBase mrs0(16); + ecmdDataBufferBase mrs0(16); ecmdDataBufferBase mrs1(16); ecmdDataBufferBase mrs2(16); ecmdDataBufferBase mrs3(16); @@ -338,172 +353,244 @@ ReturnCode mss_draminit_cloned(Target& i_target) // Check to see if any dimm needs address mirror mode. Set the approriate flag. if ( ( address_mirror_map[0][0] || - address_mirror_map[0][1] || - address_mirror_map[1][0] || - address_mirror_map[1][1] ) - && (is_sim == 0) ) + address_mirror_map[0][1] || + address_mirror_map[1][0] || + address_mirror_map[1][1] ) + && (is_sim == 0) ) { - FAPI_INF( "Setting Address Mirroring in the PHY on %s ", i_target.toEcmdString()); - - //Set the Address and BA bits affected by mirroring - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(62); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(62); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(61); - rc_num = rc_num | data_buffer_64.setBit(62); - rc_num = rc_num | data_buffer_64.setBit(63); + FAPI_INF( "Setting Address Mirroring in the PHY on %s ", i_target.toEcmdString()); + + //Set the Address and BA bits affected by mirroring + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(58); + rc_num = rc_num | data_buffer_64.setBit(59); + rc_num = rc_num | data_buffer_64.setBit(60); + rc_num = rc_num | data_buffer_64.setBit(62); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(58); - rc_num = rc_num | data_buffer_64.setBit(59); - rc_num = rc_num | data_buffer_64.setBit(60); - rc_num = rc_num | data_buffer_64.setBit(61); - rc_num = rc_num | data_buffer_64.setBit(62); - rc_num = rc_num | data_buffer_64.setBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - - for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) - { - for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) - { - - // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7 - pri_dimm = (primary_ranks_array[rank_pair_group][port_number]) / 4; - pri_dimm_rank = primary_ranks_array[rank_pair_group][port_number] - 4*pri_dimm; - sec_dimm = (secondary_ranks_array[rank_pair_group][port_number]) / 4; - sec_dimm_rank = secondary_ranks_array[rank_pair_group][port_number] - 4*sec_dimm; - ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number]) / 4; - ter_dimm_rank = tertiary_ranks_array[rank_pair_group][port_number] - 4*ter_dimm; - qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number]) / 4; - qua_dimm_rank = quaternary_ranks_array[rank_pair_group][port_number] - 4*qua_dimm; - // Set the rank pairs that will be affected. - if ( port_number == 0 ) - { + if(rc) return rc; + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(58); + rc_num = rc_num | data_buffer_64.setBit(59); + rc_num = rc_num | data_buffer_64.setBit(60); + rc_num = rc_num | data_buffer_64.setBit(62); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + } + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(58); + rc_num = rc_num | data_buffer_64.setBit(59); + rc_num = rc_num | data_buffer_64.setBit(60); + rc_num = rc_num | data_buffer_64.setBit(61); + rc_num = rc_num | data_buffer_64.setBit(62); + rc_num = rc_num | data_buffer_64.setBit(63); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(58); + rc_num = rc_num | data_buffer_64.setBit(59); + rc_num = rc_num | data_buffer_64.setBit(60); + rc_num = rc_num | data_buffer_64.setBit(61); + rc_num = rc_num | data_buffer_64.setBit(62); + rc_num = rc_num | data_buffer_64.setBit(63); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + } + + for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) + { + for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) + { + + // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7 + pri_dimm = (primary_ranks_array[rank_pair_group][port_number]) / 4; + pri_dimm_rank = primary_ranks_array[rank_pair_group][port_number] - 4*pri_dimm; + sec_dimm = (secondary_ranks_array[rank_pair_group][port_number]) / 4; + sec_dimm_rank = secondary_ranks_array[rank_pair_group][port_number] - 4*sec_dimm; + ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number]) / 4; + ter_dimm_rank = tertiary_ranks_array[rank_pair_group][port_number] - 4*ter_dimm; + qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number]) / 4; + qua_dimm_rank = quaternary_ranks_array[rank_pair_group][port_number] - 4*qua_dimm; + // Set the rank pairs that will be affected. + if ( port_number == 0 ) + { if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 48; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); - if(rc) return rc; - } - } - if ( port_number == 1 ) - { - if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 49; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) - { - FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 48; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - } - if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 48; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) { - FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); - bit_position = 2 * rank_pair_group + 49; - FAPI_INF( "Setting bit %d", bit_position); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.setBit(bit_position); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); - if(rc) return rc; - } - } - - } - } + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 49; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64); + if(rc) return rc; + } + } + if ( port_number == 1 ) + { + if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + { + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 48; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + { + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 49; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + { + FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 48; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); + if(rc) return rc; + } + if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) ) + { + FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]); + bit_position = 2 * rank_pair_group + 49; + FAPI_INF( "Setting bit %d", bit_position); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.setBit(bit_position); + if (rc_num) + { + FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64); + if(rc) return rc; + } + } + + } + } } //Commented because Master Attention Reg Check not written yet. @@ -529,7 +616,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) } rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode) - if(rc) return rc; + if(rc) return rc; rc = mss_assert_resetn(i_target, 1 ); // de-assert a reset if(rc) @@ -544,7 +631,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) if (!((dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM)||(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))) { // Step three: Load RCD Control Words - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) { rc = mss_rcd_load_ddr4(i_target, port_number, ccs_inst_cnt); if(rc) @@ -564,7 +651,7 @@ ReturnCode mss_draminit_cloned(Target& i_target) } } - else + else { rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt); if(rc) @@ -583,11 +670,21 @@ ReturnCode mss_draminit_cloned(Target& i_target) return rc; } } - } + } } } - rc = fapiDelay(DELAY_500US, DELAY_10000000SIMCYCLES); // wait 10000 simcycles (in sim mode) OR 500 uS (in hw mode) + rc = fapiDelay(DELAY_500US, DELAY_10000000SIMCYCLES); // wait 10000 simcycles (in sim mode) OR 500 uS (in hw mode) + + if(rc) + { + FAPI_ERR(" Delay Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); + return rc; + } + + + + // Cycle through Ports... // Ports 0-1 @@ -595,31 +692,31 @@ ReturnCode mss_draminit_cloned(Target& i_target) { // Step four: Load MRS Setting - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } - else - { - rc = mss_mrs_load_ddr4(i_target, port_number, ccs_inst_cnt); - if(rc) - { - FAPI_ERR(" mrs_load_ddr4 Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); - return rc; - } - } + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) + { + rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt); + if(rc) + { + FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); + return rc; + } + } + else + { + rc = mss_mrs_load_ddr4(i_target, port_number, ccs_inst_cnt); + if(rc) + { + FAPI_ERR(" mrs_load_ddr4 Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); + return rc; + } + } } // Execute the contents of CCS array if (ccs_inst_cnt > 0) { - // Set the End bit on the last CCS Instruction + // Set the End bit on the last CCS Instruction rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); if(rc) { @@ -646,466 +743,802 @@ ReturnCode mss_draminit_cloned(Target& i_target) for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++) { - for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) - { - //Check if rank group exists - if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID)) - { - - if (port_number == 0) - { - // Get contents of MRS Shadow Regs and Print it to output - if (rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); + for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++) + { + //Check if rank group exists + if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID)) + { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); + if (port_number == 0) + { + // Get contents of MRS Shadow Regs and Print it to output + if (rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); + } + else if (rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); + } + else if (rank_pair_group == 2) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); + } + else if (rank_pair_group == 3) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - } - else if (port_number == 1) - { - if (rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); + } + } + else if (port_number == 1) + { + if (rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 ); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); + } + else if (rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - - } - - } - else if (rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); + } + else if (rank_pair_group == 2) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - else if (rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); + } + else if (rank_pair_group == 3) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64); + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); - - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.reverse(); - rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); - } - - } - - } - } - } - } - - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3); + + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS4); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS5); + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.reverse(); + rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16); + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + if (rc_num) + { + FAPI_ERR( "mss_draminit: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS6); + } + + } + + } + } + } + } + + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { FAPI_INF("Performing B-side address inversion MPR write pattern"); @@ -1113,12 +1546,6 @@ ReturnCode mss_draminit_cloned(Target& i_target) if (rc) return rc; } - if (rc_num) - { - FAPI_ERR( "mss_draminit: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } // TODO: @@ -1230,7 +1657,7 @@ ReturnCode mss_rcd_load( uint8_t num_ranks_array[2][2]; //[port][dimm] uint64_t rcd_array[2][2]; //[port][dimm] uint8_t dimm_type; - + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); @@ -1280,7 +1707,7 @@ ReturnCode mss_rcd_load( else { FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number); - FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); + FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); if (rc_num) { @@ -1312,7 +1739,7 @@ ReturnCode mss_rcd_load( // Propogate through the 16, 4-bit control words for ( rcd_number = 0; rcd_number<= 15; rcd_number++) { - rc_num = rc_num | bank_3.clearBit(0, 3); + rc_num = rc_num | bank_3.clearBit(0, 3); rc_num = rc_num | address_16.clearBit(0, 16); rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]); @@ -1341,12 +1768,12 @@ ReturnCode mss_rcd_load( } - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, @@ -1374,12 +1801,6 @@ ReturnCode mss_rcd_load( if(rc) return rc; io_ccs_inst_cnt ++; - if (rc_num) - { - FAPI_ERR( "mss_rcd_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } } } } @@ -1507,7 +1928,7 @@ ReturnCode mss_mrs_load( if (dram_wr == 16) { - dram_wr = 0x00; + dram_wr = 0x00; } else if (dram_wr == 5) { @@ -1762,7 +2183,7 @@ ReturnCode mss_mrs_load( csn_8, odt_4, ddr_cal_type_4, - i_port_number); + i_port_number); if(rc) return rc; rc = mss_ccs_inst_arry_1( i_target, io_ccs_inst_cnt, @@ -1787,13 +2208,13 @@ ReturnCode mss_mrs_load( } else { - + if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode); if(rc) return rc; - if ( (lrdimm_rank_mult_mode == 4) && (num_ranks == 8) ) + if ( (lrdimm_rank_mult_mode == 4) && (num_ranks == 8) ) { num_ranks = 2; } @@ -1817,7 +2238,7 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs0.insert((uint8_t) dll_precharge, 12, 1); rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 13, 3); - rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); if ( lrdimm_rank_mult_mode != 0 ) { @@ -1849,8 +2270,8 @@ ReturnCode mss_mrs_load( } else { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number]; const uint32_t & PORT = i_port_number; const uint32_t & DIMM = dimm_number; @@ -1884,7 +2305,7 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3); - rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); if ( (lrdimm_rank_mult_mode != 0) && (rank_number > 1) ) @@ -1903,11 +2324,11 @@ ReturnCode mss_mrs_load( { dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; } - else - { + else + { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number]; const uint32_t & PORT = i_port_number; const uint32_t & DIMM = dimm_number; @@ -1926,16 +2347,16 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 5); - rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); rc_num = rc_num | mrs3.insert((uint8_t) mpr_loc, 0, 2); rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); rc_num = rc_num | mrs3.insert((uint16_t) 0x0000, 3, 13); - rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); - FAPI_INF( "MRS 0: 0x%04X", MRS0); - FAPI_INF( "MRS 1: 0x%04X", MRS1); - FAPI_INF( "MRS 2: 0x%04X", MRS2); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + FAPI_INF( "MRS 0: 0x%04X", MRS0); + FAPI_INF( "MRS 1: 0x%04X", MRS1); + FAPI_INF( "MRS 2: 0x%04X", MRS2); FAPI_INF( "MRS 3: 0x%04X", MRS3); if (rc_num) @@ -1958,28 +2379,28 @@ ReturnCode mss_mrs_load( if (mrs_number == 0) { rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); } else if ( mrs_number == 1) { rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); } else if ( mrs_number == 2) { rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); } else if ( mrs_number == 3) { rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); } @@ -1991,15 +2412,15 @@ ReturnCode mss_mrs_load( return rc_buff; } - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); if(rc) return rc; - } + } - if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) - { + if (dram_2n_mode == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) + { // Send out to the CCS array a "setup" cycle rc = mss_ccs_inst_arry_0( i_target, @@ -2029,7 +2450,7 @@ ReturnCode mss_mrs_load( io_ccs_inst_cnt ++; - } + } // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C new file mode 100644 index 000000000..9454c344d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C @@ -0,0 +1,2447 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: mss_ddr4_funcs.C,v 1.15 2015/08/28 18:15:08 sglancy Exp $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_ddr4_funcs.C +// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures +// *! OWNER NAME : jdsloat@us.ibm.com +// *! BACKUP NAME : sglancy@us.ibm.com +// #! ADDITIONAL COMMENTS : +// + +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// | | | +// 1.15 | 08/28/15 | sglancy | Added RCs - addressed FW comments +// 1.14 | 08/21/15 | sglancy | Fixed ODT initialization bug - ODT must be held low through ZQ cal +// 1.13 | 08/05/15 | kmack | Commented out FAPI_DDR4 code +// 1.12 | 07/31/15 | kmack | Mostly removed and changed comments. Reviewed some questions about the code. No real functional changes +// | | | Need new ATTRIBUTE, see comments with FIXME +// 1.11 | 07/15/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 LRDIMM +// 1.10 | 05/14/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 3DS +// 1.7 | 03/14/14 | kcook | Addeded DDR4 Register functions +// 1.6 | 01/10/14 | kcook | Updated Address mirroring swizzle (removed DIMM_TYPE_CDIMM) and +// | | | added DDR4 RDIMM support +// 1.5 | 12/03/13 | kcook | Updated VPD attributes. +// 1.4 | 11/27/13 | bellows | Added using namespace fapi +// 1.3 | 10/10/13 | bellows | Added required cvs id tag +// 1.2 | 10/09/13 | jdsloat | Added CONSTs +// 1.1 | 10/04/13 | jdsloat | First revision + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> +#include <mss_funcs.H> +#include <cen_scom_addresses.H> +#include <mss_ddr4_funcs.H> + +using namespace fapi; + +//#ifdef FAPI_DDR4 + +const uint8_t MAX_NUM_DIMMS = 2; +const uint8_t MRS0_BA = 0; +const uint8_t MRS1_BA = 1; +const uint8_t MRS2_BA = 2; +const uint8_t MRS3_BA = 3; +const uint8_t MRS4_BA = 4; +const uint8_t MRS5_BA = 5; +const uint8_t MRS6_BA = 6; + +const uint8_t PORT_SIZE = 2; + +ReturnCode mss_ddr4_invert_mpr_write( Target& i_target_mba) { + ReturnCode rc; + uint32_t rank_number; + + ReturnCode rc_buff; + uint32_t rc_num = 0; + + ecmdDataBufferBase address_16(16); + ecmdDataBufferBase bank_3(3); + ecmdDataBufferBase activate_1(1); + rc_num = rc_num | activate_1.setBit(0); + ecmdDataBufferBase rasn_1(1); + rc_num = rc_num | rasn_1.clearBit(0); + ecmdDataBufferBase casn_1(1); + rc_num = rc_num | casn_1.clearBit(0); + ecmdDataBufferBase wen_1(1); + rc_num = rc_num | wen_1.clearBit(0); + ecmdDataBufferBase cke_4(4); + rc_num = rc_num | cke_4.setBit(0,4); + ecmdDataBufferBase csn_8(8); + rc_num = rc_num | csn_8.setBit(0,8); + ecmdDataBufferBase odt_4(4); + rc_num = rc_num | odt_4.clearBit(0,4); + ecmdDataBufferBase ddr_cal_type_4(4); + + ecmdDataBufferBase num_idles_16(16); + ecmdDataBufferBase num_repeat_16(16); + ecmdDataBufferBase data_20(20); + ecmdDataBufferBase read_compare_1(1); + ecmdDataBufferBase rank_cal_4(4); + ecmdDataBufferBase ddr_cal_enable_1(1); + ecmdDataBufferBase ccs_end_1(1); + + ecmdDataBufferBase mrs3(16); + uint16_t MRS3 = 0; + uint8_t mpr_op; // MPR Op + + ecmdDataBufferBase data_buffer(64); + + uint32_t io_ccs_inst_cnt = 0; + + uint16_t num_ranks = 0; + uint8_t mpr_pattern = 0xAA; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + uint8_t num_ranks_array[2][2]; //[port][dimm] + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_array); + if(rc) return rc; + + uint8_t num_master_ranks_array[2][2]; //[port][dimm] + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, num_master_ranks_array); + if(rc) return rc; + + uint8_t is_sim = 0; + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); + if(rc) return rc; + + uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target_mba, address_mirror_map); + if(rc) return rc; + + uint8_t dram_stack[2][2]; + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, dram_stack); + if(rc) return rc; + + for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) { + // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | address_16.clearBit(0, 16); + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); + + FAPI_INF( "Stack Type in mss_ddr4_invert_mpr_write : %d\n", dram_stack[0][0]); + if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) + { + FAPI_INF( "============= Got in the 3DS stack loop =====================\n"); + rc_num = rc_num | csn_8.clearBit(2,2); + rc_num = rc_num | csn_8.clearBit(6,2); + // COMMENT IN LATER!!!!!! rc_num = rc_num | cke_4.clearBit(1); + } + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + rc = mss_ccs_inst_arry_0( i_target_mba, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + l_port); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target_mba, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) { + if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) + { + num_ranks = num_master_ranks_array[l_port][l_dimm]; + } + else { + num_ranks = num_ranks_array[l_port][l_dimm]; + } + + if (num_ranks == 0) + { + FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", l_port, l_dimm, num_ranks); + } + else + { + // Rank 0-3 + for ( rank_number = 0; rank_number < num_ranks; rank_number++) + { + + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | csn_8.clearBit(rank_number+4*l_dimm); + rc_num = rc_num | address_16.clearBit(0, 16); + + // MRS CMD to CMD spacing = 12 cycles + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + if (l_port == 0) { + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group??? + if(rc) return rc; + } + else if ( l_port == 1 ) { + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group??? + if(rc) return rc; + } + + rc_num = rc_num | data_buffer.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3); + + mpr_op = 0xff; + + rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); + + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3); + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + + rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + + // Indicate B-Side DRAMS BG1=1 + rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 + + rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 + rc_num = rc_num | address_16.flipBit(11); // Invert A11 + rc_num = rc_num | address_16.flipBit(13); // Invert A13 + rc_num = rc_num | address_16.flipBit(14); // Invert A17 + rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + + if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); + if(rc) return rc; + } + + // Send out to the CCS array + rc = mss_ccs_inst_arry_0( i_target_mba, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + l_port); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target_mba, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + + // Write pattern to MPR register + //Command structure setup + rc_num = rc_num | cke_4.flushTo1(); + rc_num = rc_num | rasn_1.setBit(0); + rc_num = rc_num | casn_1.clearBit(0); + rc_num = rc_num | wen_1.clearBit(0); + + + //Final setup + rc_num = rc_num | odt_4.flushTo0(); + rc_num = rc_num | ddr_cal_type_4.flushTo0(); + rc_num = rc_num | activate_1.setBit(0); + + + //CCS Array 1 Setup + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); + rc_num = rc_num | num_repeat_16.flushTo0(); + rc_num = rc_num | data_20.flushTo0(); + rc_num = rc_num | read_compare_1.flushTo0(); + rc_num = rc_num | rank_cal_4.flushTo0(); + rc_num = rc_num | ddr_cal_enable_1.flushTo0(); + rc_num = rc_num | ccs_end_1.flushTo0(); + + rc_num = rc_num | address_16.clearBit(0, 16); + rc_num = rc_num | address_16.insertFromRight(mpr_pattern,0, 8); + + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + + // Indicate B-Side DRAMS BG1=1 + rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 + + rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 + rc_num = rc_num | address_16.flipBit(11); // Invert A11 + rc_num = rc_num | address_16.flipBit(13); // Invert A13 + rc_num = rc_num | address_16.flipBit(14); // Invert A17 + rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + + if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); + if(rc) return rc; + } + + FAPI_INF( "Writing MPR register with 0101 pattern"); + // Send out to the CCS array + rc = mss_ccs_inst_arry_0( i_target_mba, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + l_port); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target_mba, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + // Restore MR3 to normal MPR operation + //Command structure setup + rc_num = rc_num | cke_4.flushTo1(); + rc_num = rc_num | rasn_1.clearBit(0); + rc_num = rc_num | casn_1.clearBit(0); + rc_num = rc_num | wen_1.clearBit(0); + + rc_num = rc_num | read_compare_1.clearBit(0); + + rc_num = rc_num | odt_4.flushTo0(); + rc_num = rc_num | ddr_cal_type_4.flushTo0(); + rc_num = rc_num | activate_1.setBit(0); + + rc_num = rc_num | num_repeat_16.flushTo0(); + rc_num = rc_num | data_20.flushTo0(); + rc_num = rc_num | read_compare_1.flushTo0(); + rc_num = rc_num | rank_cal_4.flushTo0(); + rc_num = rc_num | ddr_cal_enable_1.flushTo0(); + rc_num = rc_num | ccs_end_1.flushTo0(); + + rc_num = rc_num | address_16.clearBit(0, 16); + + // MRS CMD to CMD spacing = 12 cycles + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16); + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + if (l_port == 0) { + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group??? + if(rc) return rc; + } + else if ( l_port == 1 ) { + rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group??? + if(rc) return rc; + } + + rc_num = rc_num | data_buffer.reverse(); + rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0); + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3); + + mpr_op = 0x00; + + rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); + + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3); + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + + rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + + // Indicate B-Side DRAMS BG1=1 + rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 + + rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 + rc_num = rc_num | address_16.flipBit(11); // Invert A11 + rc_num = rc_num | address_16.flipBit(13); // Invert A13 + rc_num = rc_num | address_16.flipBit(14); // Invert A17 + rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 + + + if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3); + if(rc) return rc; + } + + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + // Send out to the CCS array + rc = mss_ccs_inst_arry_0( i_target_mba, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + l_port); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target_mba, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + } + } + } + } + + uint32_t NUM_POLL = 100; + rc = mss_execute_ccs_inst_array( i_target_mba, NUM_POLL, 60); + + return rc; +} + +ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) { + ReturnCode rc; + uint32_t rc_num = 0; + + uint8_t l_rcd_cntl_word_0_1; + uint8_t l_rcd_cntl_word_2; + uint8_t l_rcd_cntl_word_3; + uint8_t l_rcd_cntl_word_4; + uint8_t l_rcd_cntl_word_5; + uint8_t l_rcd_cntl_word_6_7; + uint8_t l_rcd_cntl_word_8_9; + uint8_t l_rcd_cntl_word_10; + uint8_t l_rcd_cntl_word_11; + uint8_t l_rcd_cntl_word_12; + uint8_t l_rcd_cntl_word_13; + uint8_t l_rcd_cntl_word_14; + uint8_t l_rcd_cntl_word_15; + uint64_t l_rcd_cntl_word_0_15; + uint8_t stack_type[PORT_SIZE][MAX_NUM_DIMMS]; + uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][MAX_NUM_DIMMS]; + uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS]; + uint8_t l_num_master_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS]; + uint8_t l_dimm_type_u8; + uint8_t l_dram_width_u8; + ecmdDataBufferBase data_buffer_8(8); + ecmdDataBufferBase data_buffer_64(64); + + + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM,&i_target_mba, l_num_master_ranks_per_dimm_u8array); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, stack_type); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc; + + uint64_t l_attr_eff_dimm_cntl_word_x; + + uint8_t l_rcd_cntl_word_1x; + uint8_t l_rcd_cntl_word_2x; + uint8_t l_rcd_cntl_word_3x; + uint8_t l_rcd_cntl_word_7x; + uint8_t l_rcd_cntl_word_8x; + uint8_t l_rcd_cntl_word_9x; + uint8_t l_rcd_cntl_word_Ax; + uint8_t l_rcd_cntl_word_Bx; + + //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) + rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc; + + fapi::Target l_target_centaur; + uint32_t l_mss_freq = 0; + uint32_t l_mss_volt = 0; + rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc; + + for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) { + for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) { + + // Global Features, Clock Driver Enable Control Words + l_rcd_cntl_word_0_1 = 0x00; + + // Timing and IBT Control Word + l_rcd_cntl_word_2 = 0; + + // CA and CS Signals Driver Characteristics Control Word + if (l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1) { + l_rcd_cntl_word_3 = 6; // QxCS0_n...QxCS3_n Outputs strong drive, Address/Command moderate drive + } else { + l_rcd_cntl_word_3 = 5; // QxCS0_n...QxCS3_n Outputs moderate drive, Address/Command moderate drive + } + + l_rcd_cntl_word_4 = 5; // QxODT0...QxODT1 and QxCKE0...QxCKE1 Output Drivers moderate drive + l_rcd_cntl_word_5 = 5; // Clock Y1_t, Y1_c, Y3_t, Y3_c and Y0_t, Y0_c, Y2_t, Y2_c Output Drivers moderate drive + + // Command Space Control Word + l_rcd_cntl_word_6_7 = 0xf0; // No op + // Input/Output Configuration, Power Saving Settings Control Words + if(stack_type[l_port][l_dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { + //no master ranks found, then program to disable all CIDs + //master ranks should always be found so this is a bit weird - might want to throw an error here + if(l_num_master_ranks_per_dimm_u8array[l_port][l_dimm] == 0) { + l_rcd_cntl_word_8_9 = 0x30; + } + //determine stack density - 2H, 4H, or 8H + else { + uint8_t stack_height = l_num_ranks_per_dimm_u8array[l_port][l_dimm] / l_num_master_ranks_per_dimm_u8array[l_port][l_dimm]; + FAPI_INF("3DS RCD set stack_height: %d",stack_height); + if(stack_height == 8) { + l_rcd_cntl_word_8_9 = 0x00; + } + else if(stack_height == 4) { + l_rcd_cntl_word_8_9 = 0x10; + } + else if(stack_height == 2) { + l_rcd_cntl_word_8_9 = 0x20; + } + //weird, we shouldn't have 1H stacks + else { + l_rcd_cntl_word_8_9 = 0x30; + } + } + } + + //LR DIMM and 4 ranks + else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4) { + FAPI_INF("Creating RCD value for F0rC08 - LRDDIMM and 4 ranks -> 0x10"); + l_rcd_cntl_word_8_9 = 0x10; + } + else { + l_rcd_cntl_word_8_9 = 0x30; + } + + // RDIMM Operating Speed Control Word + if ( l_mss_freq <= 1733 ) { // 1600 + l_rcd_cntl_word_10 = 0; + } else if ( l_mss_freq <= 2000 ) { // 1866 + l_rcd_cntl_word_10 = 1; + } else if ( l_mss_freq <= 2266 ) { // 2133 + l_rcd_cntl_word_10 = 2; + } else if ( l_mss_freq <= 2533 ) { // 2400 + l_rcd_cntl_word_10 = 3; + } else if ( l_mss_freq <= 2800 ) { // 2666 + l_rcd_cntl_word_10 = 4; + } else if ( l_mss_freq <= 3333 ) { // 3200 + l_rcd_cntl_word_10 = 5; + } else { + FAPI_ERR("Invalid LRDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + // Operating Voltage VDD and VREFCA Source Control Word + if ( l_mss_volt >= 1120 ) { // 1.2V + l_rcd_cntl_word_11 = 14; + } else if ( l_mss_volt >= 1020 ) { // 1.0xV + l_rcd_cntl_word_11 = 15; + } else { + FAPI_ERR("Invalid LRDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + // Training Control Word + l_rcd_cntl_word_12 = 0; + + // DIMM Configuration Control words + data_buffer_8.clearBit(0,8); + if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { + rc_num |= data_buffer_8.setBit(3); // Direct QuadCS mode + } + if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { + rc_num |= data_buffer_8.setBit(1); + } + if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { + rc_num |= data_buffer_8.setBit(0); // Address mirroring for MRS commands + } + + rc_num |= data_buffer_8.extractToRight( &l_rcd_cntl_word_13, 0, 4); + + // Parity Control Word + l_rcd_cntl_word_14 = 0; + + // Command Latency Adder Control Word + if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) { + l_rcd_cntl_word_15 = 4; // 0nCk latency adder + } + else { + l_rcd_cntl_word_15 = 0; // 1nCk latency adder with DB control bus + } + + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_0_1, 0 , 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2, 8 , 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3, 12, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_4, 16, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_5, 20, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_6_7, 24, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8_9, 32, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_10, 40, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_11, 44, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_12, 48, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_13, 52, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_14, 56, 4); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_15, 60, 4); + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + l_rcd_cntl_word_0_15 = data_buffer_64.getDoubleWord(0); if(rc) return rc; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_rcd_cntl_word_0_15; + + // Set RCD control word x + + // RC1x Internal VREF CW + l_rcd_cntl_word_1x = 0; + + // RC2x I2C Bus Control Word + l_rcd_cntl_word_2x = 0; + + // RC3x Fine Granularity RDIMM Operating Speed Control Word + if ( l_mss_freq > 1240 && l_mss_freq < 3200 ) { + l_rcd_cntl_word_3x = int ((l_mss_freq - 1250) / 20); + } else { + FAPI_ERR("Invalid DIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + // RC7x IBT Control Word + l_rcd_cntl_word_7x = 0; + + // RC8x ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word + l_rcd_cntl_word_8x = 0; + + // RC9x QxODT[1:0] Write Pattern CW + l_rcd_cntl_word_9x = 0; + + // RCAx QxODT[1:0] Read Pattern CW + l_rcd_cntl_word_Ax = 0; + + // RCBx IBT and MRS Snoop CW + if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { + l_rcd_cntl_word_Bx = 4; + } else { + l_rcd_cntl_word_Bx = 7; + } + + + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_1x, 0 , 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2x, 8 , 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3x, 16, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_7x, 24, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8x, 32, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_9x, 40, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Ax, 48, 8); + rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Bx, 56, 8); + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + l_attr_eff_dimm_cntl_word_x = data_buffer_64.getDoubleWord(0); if(rc) return rc; + FAPI_INF("from data buffer: rcd control word X %llX", l_attr_eff_dimm_cntl_word_x ); + + } // end dimm loop + } // end port loop + + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + + //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) + rc = FAPI_ATTR_SET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc; + + return rc; + +} + +ReturnCode mss_rcd_load_ddr4( + Target& i_target, + uint32_t i_port_number, + uint32_t& io_ccs_inst_cnt + ) { + + ReturnCode rc; + ReturnCode rc_buff; + uint32_t rc_num = 0; + uint32_t dimm_number; + uint32_t rcd_number; + + ecmdDataBufferBase rcd_cntl_wrd_4(8); + ecmdDataBufferBase rcd_cntl_wrd_8(8); + ecmdDataBufferBase rcd_cntl_wrd_64(64); + uint16_t num_ranks; + + ecmdDataBufferBase address_16(16); + ecmdDataBufferBase bank_3(3); + ecmdDataBufferBase activate_1(1); + ecmdDataBufferBase rasn_1(1); + rc_num = rc_num | rasn_1.setBit(0); + ecmdDataBufferBase casn_1(1); + rc_num = rc_num | casn_1.setBit(0); + ecmdDataBufferBase wen_1(1); + rc_num = rc_num | wen_1.setBit(0); + ecmdDataBufferBase cke_4(4); + rc_num = rc_num | cke_4.setBit(0,4); + ecmdDataBufferBase csn_8(8); + rc_num = rc_num | csn_8.setBit(0,8); + ecmdDataBufferBase odt_4(4); + rc_num = rc_num | odt_4.clearBit(0,4); + ecmdDataBufferBase ddr_cal_type_4(4); + + ecmdDataBufferBase num_idles_16(16); + ecmdDataBufferBase num_repeat_16(16); + ecmdDataBufferBase data_20(20); + ecmdDataBufferBase read_compare_1(1); + ecmdDataBufferBase rank_cal_4(4); + ecmdDataBufferBase ddr_cal_enable_1(1); + ecmdDataBufferBase ccs_end_1(1); + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + uint8_t num_ranks_array[2][2]; //[port][dimm] + uint64_t rcd_array[2][2]; //[port][dimm] + uint8_t dimm_type; + + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); + if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); + if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array); + if(rc) return rc; + + uint32_t cntlx_offset[]= {1,2,3,7,8,9,10,11}; + // Dummy attribute for addtitional cntl words + uint64_t rcdx_array; + // uint64_t rcdx_array[2][2]; + + //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change) + rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target, rcdx_array); + if(rc) return rc; + + // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles + rc_num = rc_num | address_16.clearBit(0, 16); + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number); + + for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) + { + num_ranks = num_ranks_array[i_port_number][dimm_number]; + + if (num_ranks == 0) + { + FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks); + } + else + { + FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number); + FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]); + //FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array[i_port_number][dimm_number]); + FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array); + + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + // ALL active CS lines at a time. + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | csn_8.clearBit(0); //DCS0_n is LOW + + // DBG1, DBG0, DBA1, DBA0 = 4`b0111 + rc_num = rc_num | bank_3.setBit(0, 3); + // DACT_n is HIGH + rc_num = rc_num | activate_1.setBit(0); + // RAS_n/CAS_n/WE_n are LOW + rc_num = rc_num | rasn_1.clearBit(0); + rc_num = rc_num | casn_1.clearBit(0); + rc_num = rc_num | wen_1.clearBit(0); + + // Propogate through the 16, 4-bit control words + for ( rcd_number = 0; rcd_number<= 15; rcd_number++) + { + //rc_num = rc_num | bank_3.clearBit(0, 3); + rc_num = rc_num | address_16.clearBit(0, 16); + + rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]); + rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*rcd_number, 4); + + //control word number code bits A[7:4] + rc_num = rc_num | address_16.insert(rcd_number, 7, 1, 28); + rc_num = rc_num | address_16.insert(rcd_number, 6, 1, 29); + rc_num = rc_num | address_16.insert(rcd_number, 5, 1, 30); + rc_num = rc_num | address_16.insert(rcd_number, 4, 1, 31); + + //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3 + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 0, 1, 3); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 1, 1, 2); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 2, 1, 1); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 0); + + // Send out to the CCS array + //if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && (rcd_number == 2 || rcd_number == 10) ) + if ( rcd_number == 2 || rcd_number == 10 ) + { + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words + } + else + { + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); + } + + + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + } + + // 8-bit Control words + for ( rcd_number = 0; rcd_number<= 7; rcd_number++) + { + //rc_num = rc_num | bank_3.clearBit(0, 3); + rc_num = rc_num | address_16.clearBit(0, 16); + + //rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array[i_port_number][dimm_number]); + rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array); + rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_8, 8*rcd_number, 8); + + //control word number code bits A[11:8] + rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 11, 1, 28); + rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 10, 1, 29); + rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 9, 1, 30); + rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 8, 1, 31); + + //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3, RCD4=A4, RCD5=A5, RCD6=A6, RCD7=A7 + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 0, 1, 7); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 1, 1, 6); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 2, 1, 5); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 3, 1, 4); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 4, 1, 3); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 5, 1, 2); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 6, 1, 1); + rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 7, 1, 0); + + // Send out to the CCS array + if ( rcd_number == 2 ) // CW RC3x + { + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words + } + else + { + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); + } + + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + if (rc_num) + { + FAPI_ERR( "mss_rcd_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + } + } + } + + rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1); + if(rc) + { + FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); + return rc; + } + io_ccs_inst_cnt = 0; + + rc = mss_execute_ccs_inst_array(i_target, 10, 10); + if(rc) + { + FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); + return rc; + } + + + return rc; +} + +ReturnCode mss_mrs_load_ddr4( + Target& i_target, + uint32_t i_port_number, + uint32_t& io_ccs_inst_cnt + ) +{ + + uint32_t dimm_number; + uint32_t rank_number; + uint32_t mrs_number; + ReturnCode rc; + ReturnCode rc_buff; + uint32_t rc_num = 0; + ecmdDataBufferBase data_buffer_64(64); + ecmdDataBufferBase address_16(16); + ecmdDataBufferBase bank_3(3); + ecmdDataBufferBase activate_1(1); + rc_num = rc_num | activate_1.setBit(0); + ecmdDataBufferBase rasn_1(1); + rc_num = rc_num | rasn_1.clearBit(0); + ecmdDataBufferBase casn_1(1); + rc_num = rc_num | casn_1.clearBit(0); + ecmdDataBufferBase wen_1(1); + rc_num = rc_num | wen_1.clearBit(0); + ecmdDataBufferBase cke_4(4); + rc_num = rc_num | cke_4.clearBit(0,4); + ecmdDataBufferBase csn_8(8); + rc_num = rc_num | csn_8.clearBit(0,8); + ecmdDataBufferBase odt_4(4); + rc_num = rc_num | odt_4.clearBit(0,4); + ecmdDataBufferBase ddr_cal_type_4(4); + + ecmdDataBufferBase num_idles_16(16); + ecmdDataBufferBase num_idles_16_vref_train(16); + rc_num = rc_num | num_idles_16_vref_train.insertFromRight((uint32_t) 160, 0, 16); + + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + ecmdDataBufferBase num_repeat_16(16); + ecmdDataBufferBase data_20(20); + ecmdDataBufferBase read_compare_1(1); + ecmdDataBufferBase rank_cal_4(4); + ecmdDataBufferBase ddr_cal_enable_1(1); + ecmdDataBufferBase ccs_end_1(1); + + ecmdDataBufferBase mrs0(16); + ecmdDataBufferBase mrs1(16); + ecmdDataBufferBase mrs2(16); + ecmdDataBufferBase mrs3(16); + ecmdDataBufferBase mrs4(16); + ecmdDataBufferBase mrs5(16); + ecmdDataBufferBase mrs6(16); + ecmdDataBufferBase mrs6_train_on(16); + uint16_t MRS0 = 0; + uint16_t MRS1 = 0; + uint16_t MRS2 = 0; + uint16_t MRS3 = 0; + uint16_t MRS4 = 0; + uint16_t MRS5 = 0; + uint16_t MRS6 = 0; + + ecmdDataBufferBase data_buffer(64); + + + uint16_t num_ranks = 0; + + FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number); + + uint8_t num_ranks_array[2][2]; //[port][dimm] + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); + if(rc) return rc; + + uint8_t num_master_ranks_array[2][2]; //[port][dimm] + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array); + if(rc) return rc; + + uint8_t dimm_type; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); + if(rc) return rc; + + uint8_t is_sim = 0; + rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim); + if(rc) return rc; + + uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm] + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map); + if(rc) return rc; + + + // WORKAROUNDS + rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); + if(rc) return rc; + //Setting up CCS mode + rc_num = rc_num | data_buffer.setBit(51); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); + if(rc) return rc; + + rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); + if(rc) return rc; + //Setting up CCS mode + rc_num = rc_num | data_buffer.clearBit(48); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); + if(rc) return rc; + + + uint8_t dram_stack[2][2]; + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack); + if(rc) return rc; + + FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); + if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) + { + FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!! =====================\n"); + rc_num = rc_num | csn_8.clearBit(2,2); + rc_num = rc_num | csn_8.clearBit(6,2); + // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + } + + //Lines commented out in the following section are waiting for xml attribute adds + //MRS0 + uint8_t dram_bl; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl); + if(rc) return rc; + uint8_t read_bt; //Read Burst Type + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt); + if(rc) return rc; + uint8_t dram_cl; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl); + if(rc) return rc; + uint8_t test_mode; //TEST MODE + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode); + if(rc) return rc; + uint8_t dll_reset; //DLL Reset + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset); + if(rc) return rc; + uint8_t dram_wr; //DRAM write recovery + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr); + if(rc) return rc; + uint8_t dram_rtp; //DRAM RTP - read to precharge + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_rtp); + if(rc) return rc; + uint8_t dll_precharge; //DLL Control For Precharge + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge); + if(rc) return rc; + + if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8) + { + dram_bl = 0x00; + } + else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF) + { + dram_bl = 0x80; + } + else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4) + { + dram_bl = 0x40; + } + + uint8_t dram_wr_rtp = 0x00; + if ( (dram_wr == 10) )//&& (dram_rtp == 5) ) + { + dram_wr_rtp = 0x00; + } + else if ( (dram_wr == 12) )//&& (dram_rtp == 6) ) + { + dram_wr_rtp = 0x80; + } + else if ( (dram_wr == 13) )//&& (dram_rtp == 7) ) + { + dram_wr_rtp = 0x40; + } + else if ( (dram_wr == 14) )//&& (dram_rtp == 8) ) + { + dram_wr_rtp = 0xC0; + } + else if ( (dram_wr == 18) )//&& (dram_rtp == 9) ) + { + dram_wr_rtp = 0x20; + } + else if ( (dram_wr == 20) )//&& (dram_rtp == 10) ) + { + dram_wr_rtp = 0xA0; + } + else if ( (dram_wr == 24) )//&& (dram_rtp == 12) ) + { + dram_wr_rtp = 0x60; + } + + if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) + { + read_bt = 0x00; + } + else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE) + { + read_bt = 0xFF; + } + + if ((dram_cl > 8)&&(dram_cl < 17)) + { + dram_cl = dram_cl - 9; + } + else if ((dram_cl > 17)&&(dram_cl < 25)) + { + dram_cl = (dram_cl >> 1) - 1; + } + dram_cl = mss_reverse_8bits(dram_cl); + + if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL) + { + test_mode = 0x00; + } + else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST) + { + test_mode = 0xFF; + } + + if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES) + { + dll_reset = 0xFF; + } + else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO) + { + dll_reset = 0x00; + } + + if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) + { + dll_precharge = 0x00; + } + else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT) + { + dll_precharge = 0xFF; + } + + //MRS1 + uint8_t dll_enable; //DLL Enable + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable); + if(rc) return rc; + uint8_t out_drv_imp_cntl[2][2]; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl); + if(rc) return rc; + uint8_t dram_rtt_nom[2][2][4]; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom); + if(rc) return rc; + uint8_t dram_al; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al); + if(rc) return rc; + uint8_t wr_lvl; //write leveling enable + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl); + if(rc) return rc; + uint8_t tdqs_enable; //TDQS Enable + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable); + if(rc) return rc; + uint8_t q_off; //Qoff - Output buffer Enable + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off); + if(rc) return rc; + + if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE) + { + dll_enable = 0x00; + } + else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE) + { + dll_enable = 0xFF; + } + + if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE) + { + dram_al = 0x00; + } + else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1) + { + dram_al = 0x80; + } + else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2) + { + dram_al = 0x40; + } + + if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE) + { + wr_lvl = 0x00; + } + else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE) + { + wr_lvl = 0xFF; + } + + if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE) + { + tdqs_enable = 0x00; + } + else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE) + { + tdqs_enable = 0xFF; + } + + if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE) + { + q_off = 0xFF; + } + else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE) + { + q_off = 0x00; + } + + //MRS2 + + uint8_t lpasr; // Low Power Auto Self-Refresh -- new not yet supported + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_LPASR, &i_target, lpasr); + if(rc) return rc; + uint8_t cwl; // CAS Write Latency + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl); + if(rc) return rc; + uint8_t dram_rtt_wr[2][2][4]; + rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr); + if(rc) return rc; + uint8_t write_crc; // CAS Write Latency + rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_CRC, &i_target, write_crc); + if(rc) return rc; + + if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL) + { + lpasr = 0x00; + } + else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED) + { + lpasr = 0x80; + } + else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED) + { + lpasr = 0x40; + } + else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR) + { + lpasr = 0xFF; + } + + if ((cwl > 8)&&(cwl < 13)) + { + cwl = cwl - 9; + } + else if ((cwl > 13)&&(cwl < 19)) + { + cwl = (cwl >> 1) - 3; + } + else + { + //no correcct value for CWL was found + FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing..."); + cwl = 0; + } + cwl = mss_reverse_8bits(cwl); + + if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE) + { + write_crc = 0xFF; + } + else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE) + { + write_crc = 0x00; + } + + //MRS3 + uint8_t mpr_op; // MPR Op + rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op); + if(rc) return rc; + uint8_t mpr_page; // MPR Page Selection - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page); + if(rc) return rc; + uint8_t geardown_mode; // Gear Down Mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode); + if(rc) return rc; + uint8_t dram_access; // per dram accessibility - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_PER_DRAM_ACCESS, &i_target, dram_access); + if(rc) return rc; + uint8_t temp_readout; // Temperature sensor readout - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout); + if(rc) return rc; + uint8_t fine_refresh; // fine refresh mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh); + if(rc) return rc; + uint8_t wr_latency; // write latency for CRC and DM - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency); + if(rc) return rc; + uint8_t read_format; // MPR READ FORMAT - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format); + if(rc) return rc; + + if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE) + { + mpr_op = 0xFF; + } + else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE) + { + mpr_op = 0x00; + } + + mpr_page = mss_reverse_8bits(mpr_page); + + if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_ENABLE) + { + dram_access = 0xFF; + } + else if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE) + { + dram_access = 0x00; + } + + if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF) + { + geardown_mode = 0x00; + } + else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER) + { + geardown_mode = 0xFF; + } + + if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE) + { + temp_readout = 0xFF; + } + else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE) + { + temp_readout = 0x00; + } + + if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL) + { + fine_refresh = 0x00; + } + else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X) + { + fine_refresh = 0x80; + } + else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X) + { + fine_refresh = 0x40; + } + else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X) + { + fine_refresh = 0xA0; + } + else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X) + { + fine_refresh = 0x60; + } + + if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK) + { + wr_latency = 0x00; + } + else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK) + { + wr_latency = 0x80; + } + else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK) + { + wr_latency = 0xC0; + } + + if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL) + { + read_format = 0x00; + } + else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL) + { + read_format = 0x80; + } + else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED) + { + read_format = 0x40; + } + else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP) + { + read_format = 0xC0; + } + + //MRS4 + uint8_t max_pd_mode; // Max Power down mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target, max_pd_mode); + if(rc) return rc; + uint8_t temp_ref_range; // Temp ref range - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_RANGE, &i_target, temp_ref_range); + if(rc) return rc; + uint8_t temp_ref_mode; // Temp controlled ref mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_MODE, &i_target, temp_ref_mode); + if(rc) return rc; + uint8_t vref_mon; // Internal Vref Monitor - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_INT_VREF_MON, &i_target, vref_mon); + if(rc) return rc; + uint8_t cs_cmd_latency; // CS to CMD/ADDR Latency - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CS_CMD_LATENCY, &i_target, cs_cmd_latency); + if(rc) return rc; + uint8_t ref_abort; // Self Refresh Abort - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_SELF_REF_ABORT, &i_target, ref_abort); + if(rc) return rc; + uint8_t rd_pre_train_mode; // Read Pre amble Training Mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target, rd_pre_train_mode); + if(rc) return rc; + uint8_t rd_preamble; // Read Pre amble - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE, &i_target, rd_preamble); + if(rc) return rc; + uint8_t wr_preamble; // Write Pre amble - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_WR_PREAMBLE, &i_target, wr_preamble); + if(rc) return rc; + + if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE) + { + max_pd_mode = 0xF0; + } + else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE) + { + max_pd_mode = 0x00; + } + + if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL) + { + temp_ref_range = 0x00; + } + else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND) + { + temp_ref_range = 0xFF; + } + + if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE) + { + temp_ref_mode = 0x80; + } + else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE) + { + temp_ref_mode = 0x00; + } + + if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE) + { + vref_mon = 0xFF; + } + else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE) + { + vref_mon = 0x00; + } + + + if ( cs_cmd_latency == 3) + { + cs_cmd_latency = 0x80; + } + else if (cs_cmd_latency == 4) + { + cs_cmd_latency = 0x40; + } + else if (cs_cmd_latency == 5) + { + cs_cmd_latency = 0xC0; + } + else if (cs_cmd_latency == 6) + { + cs_cmd_latency = 0x20; + } + else if (cs_cmd_latency == 8) + { + cs_cmd_latency = 0xA0; + } + + if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE) + { + ref_abort = 0xFF; + } + else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE) + { + ref_abort = 0x00; + } + + if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE) + { + rd_pre_train_mode = 0xFF; + } + else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE) + { + rd_pre_train_mode = 0x00; + } + + if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK) + { + rd_preamble = 0x00; + } + else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK) + { + rd_preamble = 0xFF; + } + + if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK) + { + wr_preamble = 0x00; + } + else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK) + { + wr_preamble = 0xFF; + } + + + //MRS5 + uint8_t ca_parity_latency; //C/A Parity Latency Mode - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_LATENCY , &i_target, ca_parity_latency); + if(rc) return rc; + uint8_t crc_error_clear; //CRC Error Clear - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CRC_ERROR_CLEAR , &i_target, crc_error_clear); + if(rc) return rc; + uint8_t ca_parity_error_status; //C/A Parity Error Status - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_ERROR_STATUS , &i_target, ca_parity_error_status); + if(rc) return rc; + uint8_t odt_input_buffer; //ODT Input Buffer during power down - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_ODT_INPUT_BUFF , &i_target, odt_input_buffer); + if(rc) return rc; + uint8_t rtt_park[2][2][4]; //RTT_Park value - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_RTT_PARK , &i_target, rtt_park); + if(rc) return rc; + uint8_t ca_parity; //CA Parity Persistance Error - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY , &i_target, ca_parity); + if(rc) return rc; + uint8_t data_mask; //Data Mask - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_DATA_MASK , &i_target, data_mask); + if(rc) return rc; + uint8_t write_dbi; //Write DBI - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_DBI , &i_target, write_dbi); + if(rc) return rc; + uint8_t read_dbi; //Read DBI - NEW + rc = FAPI_ATTR_GET(ATTR_EFF_READ_DBI , &i_target, read_dbi); + if(rc) return rc; + + + if (ca_parity_latency == 4) + { + ca_parity_latency = 0x80; + } + else if (ca_parity_latency == 5) + { + ca_parity_latency = 0x40; + } + else if (ca_parity_latency == 6) + { + ca_parity_latency = 0xC0; + } + else if (ca_parity_latency == 8) + { + ca_parity_latency = 0x20; + } + else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE) + { + ca_parity_latency = 0x00; + } + + if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR) + { + crc_error_clear = 0xFF; + } + else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR) + { + crc_error_clear = 0x00; + } + + if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR) + { + ca_parity_error_status = 0xFF; + } + else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR) + { + ca_parity_error_status = 0x00; + } + + if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED) + { + odt_input_buffer = 0x00; + } + else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED) + { + odt_input_buffer = 0xFF; + } + + + if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE) + { + ca_parity = 0xFF; + } + else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE) + { + ca_parity = 0x00; + } + + if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE) + { + data_mask = 0x00; + } + else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE) + { + data_mask = 0xFF; + } + + if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE) + { + write_dbi = 0x00; + } + else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE) + { + write_dbi = 0xFF; + } + + if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE) + { + read_dbi = 0x00; + } + else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE) + { + read_dbi = 0xFF; + } + + //MRS6 + uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value - NEW + rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value); + if(rc) return rc; + uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range - NEW + rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range); + if(rc) return rc; + uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable - NEW + rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable); + if(rc) return rc; + uint8_t tccd_l; //tccd_l - NEW + rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l); + if(rc) return rc; + if (tccd_l == 4) + { + tccd_l = 0x00; + } + else if (tccd_l == 5) + { + tccd_l = 0x80; + } + else if (tccd_l == 6) + { + tccd_l = 0x40; + } + else if (tccd_l == 7) + { + tccd_l = 0xC0; + } + else if (tccd_l == 8) + { + tccd_l = 0x20; + } + + // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles + rc_num = rc_num | cke_4.setBit(0,4); + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | address_16.clearBit(0, 16); + rc_num = rc_num | odt_4.clearBit(0,4); + rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + // Dimm 0-1 + for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++) + { + //if the dram stack type is a 3DS dimm + if(dram_stack[i_port_number][dimm_number] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { + FAPI_INF("DIMM is a 3DS type, using num_masetr_ranks_array"); + num_ranks = num_master_ranks_array[i_port_number][dimm_number]; + } + else { + num_ranks = num_ranks_array[i_port_number][dimm_number]; + } + + if (num_ranks == 0) + { + FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks); + } + else + { + // Rank 0-3 + for ( rank_number = 0; rank_number < num_ranks; rank_number++) + { + FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number); + + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | address_16.clearBit(0, 16); + + //For DDR4: + //Address 14 = Address 17, Address 15 = BG1 + rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0); + rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0); + rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0); + rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1); + rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1); + rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1); + rc_num = rc_num | mrs0.insert((uint8_t) dram_wr_rtp, 9, 3); + rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 12, 4); + + rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE) + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00; + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20; + FAPI_INF("DRAM RTT_NOM is configured for 240 OHM which is not supported."); + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0; + FAPI_INF("DRAM RTT_NOM is configured for 48 OHM which is not supported."); + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40) + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0; + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60) + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80; + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120) + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40; + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x60; + FAPI_INF("DRAM RTT_NOM is configured for 80 OHM which is not supported."); + } + else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported + { + dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xE0; + FAPI_INF("DRAM RTT_NOM is configured for 34 OHM which is not supported."); + } + + if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34) + { + out_drv_imp_cntl[i_port_number][dimm_number] = 0x00; + } + // Not currently supported + else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported + { + out_drv_imp_cntl[i_port_number][dimm_number] = 0x80; + FAPI_INF("DRAM RON is configured for 48 OHM which is not supported."); + } + + //For DDR4: + //Address 14 = Address 17, Address 15 = BG1 + rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0); + rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 2, 0); + rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0); + rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 5, 2); + rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0); + rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 8, 3, 0); + rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0); + rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); + rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3); + + + rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + + if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE) + { + dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00; + } + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120) + { + dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80; + } + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240) + { + dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40; + } + else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ) + { + dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0xFF; + } + + rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 0, 3); + rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3); + rc_num = rc_num | mrs2.insert((uint8_t) lpasr, 6, 2); + rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1); + rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); + rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 1); + rc_num = rc_num | mrs2.insert((uint8_t) write_crc, 12, 1); + rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 13, 2); + + rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2); + rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1); + rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1); + rc_num = rc_num | mrs3.insert((uint8_t) dram_access, 4, 1); + rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1); + rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3); + rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2); + rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2); + rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2); + + + rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 0, 1); + rc_num = rc_num | mrs4.insert((uint8_t) max_pd_mode, 1, 1); + rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_range, 2, 1); + rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_mode, 3, 1); + rc_num = rc_num | mrs4.insert((uint8_t) vref_mon, 4, 1); + rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 5, 1); + rc_num = rc_num | mrs4.insert((uint8_t) cs_cmd_latency, 6, 3); + rc_num = rc_num | mrs4.insert((uint8_t) ref_abort, 9, 1); + rc_num = rc_num | mrs4.insert((uint8_t) rd_pre_train_mode, 10, 1); + rc_num = rc_num | mrs4.insert((uint8_t) rd_preamble, 11, 1); + rc_num = rc_num | mrs4.insert((uint8_t) wr_preamble, 12, 1); + rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + + //MRS5 + if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_DISABLE) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0x00; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_60OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0x80; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_40OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0xC0; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_120OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0x40; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_240OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0x20; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_48OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0xA0; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_80OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0x60; + } + else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_34OHM) + { + rtt_park[i_port_number][dimm_number][rank_number] = 0xE0; + } + + rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_latency, 0, 2); + rc_num = rc_num | mrs5.insert((uint8_t) crc_error_clear, 3, 1); + rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_error_status, 4, 1); + rc_num = rc_num | mrs5.insert((uint8_t) odt_input_buffer, 5, 1); + rc_num = rc_num | mrs5.insert((uint8_t) rtt_park[i_port_number][dimm_number][rank_number], 6, 3); + rc_num = rc_num | mrs5.insert((uint8_t) ca_parity, 9, 1); + rc_num = rc_num | mrs5.insert((uint8_t) data_mask, 10, 1); + rc_num = rc_num | mrs5.insert((uint8_t) write_dbi, 11, 1); + rc_num = rc_num | mrs5.insert((uint8_t) read_dbi, 12, 1); + rc_num = rc_num | mrs5.insert((uint8_t) 0x00, 13, 2); + + + rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + //MRS6 + + vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); + + if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) + { + vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; + } + else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) + { + vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; + } + + if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) + { + vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xFF; + } + else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) + { + vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00; + } + + rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); + rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); + rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1); + rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2); + rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3); + rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2); + + rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); + rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); + rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0xff, 7, 1); + rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 8, 2); + rc_num = rc_num | mrs6_train_on.insert((uint8_t) tccd_l, 10, 3); + rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 13, 2); + + + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); + + FAPI_INF( "MRS 0: 0x%04X", MRS0); + FAPI_INF( "MRS 1: 0x%04X", MRS1); + FAPI_INF( "MRS 2: 0x%04X", MRS2); + FAPI_INF( "MRS 3: 0x%04X", MRS3); + FAPI_INF( "MRS 4: 0x%04X", MRS4); + FAPI_INF( "MRS 5: 0x%04X", MRS5); + FAPI_INF( "MRS 6: 0x%04X", MRS6); + + if (rc_num) + { + FAPI_ERR( "mss_mrs_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + // Only corresponding CS to rank + rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); + + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + + uint8_t dram_stack[2][2]; + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack); + if(rc) return rc; + + FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); + if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) + { + FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!=====================\n"); + rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2); + // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1); + if(rc_num) { + rc.setEcmdError(rc_num); + return rc; + } + } + + // Propogate through the 4 MRS cmds + for ( mrs_number = 0; mrs_number < 7; mrs_number++) + { + //mrs_number = 1; + // Copying the current MRS into address buffer matching the MRS_array order + // Setting the bank address + if (mrs_number == 0) + { + rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + } + else if ( mrs_number == 1) + { + + rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); + } + else if ( mrs_number == 2) + { + rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5); + } + else if ( mrs_number == 3) + { + rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5); + } + else if ( mrs_number == 4) + { + rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); + } + else if ( mrs_number == 5) + { + rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); + } + else if ( mrs_number == 6) + { + rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); + } + //mrs_number = 7; + + if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + if(rc) return rc; + } + + + if (rc_num) + { + FAPI_ERR( "mss_mrs_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + // Send out to the CCS array + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + + + } + + // Address inversion for RCD + if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + { + FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n"); + + + // Propogate through the 4 MRS cmds + for ( mrs_number = 0; mrs_number < 7; mrs_number++) + { + //mrs_number = 1; + // Copying the current MRS into address buffer matching the MRS_array order + // Setting the bank address + if (mrs_number == 0) + { + rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5); + } + else if ( mrs_number == 1) + { + + + rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); + } + else if ( mrs_number == 2) + { + rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5); + } + else if ( mrs_number == 3) + { + rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5); + } + else if ( mrs_number == 4) + { + rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5); + } + else if ( mrs_number == 5) + { + rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5); + } + else if ( mrs_number == 6) + { + rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6); + rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5); + } + + // Indicate B-Side DRAMS BG1=1 + rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 + + rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 + rc_num = rc_num | address_16.flipBit(11); // Invert A11 + rc_num = rc_num | address_16.flipBit(13); // Invert A13 + rc_num = rc_num | address_16.flipBit(14); // Invert A17 + rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 + + + if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + if(rc) return rc; + } + + + if (rc_num) + { + FAPI_ERR( " Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + // Send out to the CCS array + rc = mss_ccs_inst_arry_0( i_target, + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); + if(rc) return rc; + rc = mss_ccs_inst_arry_1( i_target, + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); + if(rc) return rc; + io_ccs_inst_cnt ++; + + } + } + + } + } + } + + return rc; +} + +//#endif + + + + + + diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C index b7e0e253c..36892a768 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv//mss_mrs6_DDR4.C $ */ +/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -22,14 +22,12 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_mrs6_DDR4.C,v 1.4 2015/08/05 15:06:03 sglancy Exp $ +// $Id: mss_mrs6_DDR4.C,v 1.6 2015/09/04 02:03:31 kmack Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2007 // *! All Rights Reserved -- Property of IBM -// *! *** *** - //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! @@ -38,6 +36,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.05 | 09/03/15 | kmack | RC updates // 1.04 | 08/05/15 | sglancy | Fixed FW compile error // 1.03 | 08/04/15 | sglancy | Changed to address FW comments // 1.02 | 05/07/15 | sglancy | Fixed enable disable bug and added 3DS support @@ -75,11 +74,11 @@ for ( port_number = 0; port_number < 2; port_number++) } } - + // Execute the contents of CCS array if (ccs_inst_cnt > 0) { - // Set the End bit on the last CCS Instruction + // Set the End bit on the last CCS Instruction rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1); if(rc) { @@ -95,9 +94,9 @@ for ( port_number = 0; port_number < 2; port_number++) } ccs_inst_cnt = 0; - } - - return rc; + } + + return rc; } @@ -133,7 +132,7 @@ fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase & //Buffer conversions from inputs l_ecmd_rc |= addr_16.reverse(); l_ecmd_rc |= bank_3.insertFromRight(bank, 0, 3); - l_ecmd_rc |= bank_3.reverse(); //Banks are 0:2 + l_ecmd_rc |= bank_3.reverse(); //Banks are 0:2 l_ecmd_rc |= csn_8.flushTo1(); l_ecmd_rc |= csn_8.clearBit(rank); @@ -142,7 +141,7 @@ fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase & l_ecmd_rc |= rasn_1.setBit(0); l_ecmd_rc |= casn_1.setBit(0); l_ecmd_rc |= wen_1.setBit(0); - + l_ecmd_rc |= read_compare_1.clearBit(0); //Final setup @@ -185,13 +184,13 @@ fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase & ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_t& io_ccs_inst_cnt) { - const uint8_t MRS6_BA = 6; + const uint8_t MRS6_BA = 6; uint32_t dimm_number; uint32_t rank_number; - ReturnCode rc; + ReturnCode rc; ReturnCode rc_buff; uint32_t rc_num = 0; - uint8_t tmod_delay = 12; + uint8_t tmod_delay = 12; ecmdDataBufferBase data_buffer_64(64); ecmdDataBufferBase address_16(16); ecmdDataBufferBase bank_3(3); @@ -210,7 +209,8 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ ecmdDataBufferBase odt_4(4); rc_num = rc_num | odt_4.clearBit(0,4); ecmdDataBufferBase ddr_cal_type_4(4); - uint32_t instruction_number; + + uint32_t instruction_number; ecmdDataBufferBase num_idles_16(16); ecmdDataBufferBase num_repeat_16(16); ecmdDataBufferBase data_20(20); @@ -218,18 +218,18 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ ecmdDataBufferBase rank_cal_4(4); ecmdDataBufferBase ddr_cal_enable_1(1); ecmdDataBufferBase ccs_end_1(1); - ecmdDataBufferBase mrs0(16); + ecmdDataBufferBase mrs0(16); ecmdDataBufferBase mrs1(16); ecmdDataBufferBase mrs2(16); ecmdDataBufferBase mrs3(16); ecmdDataBufferBase mrs4(16); ecmdDataBufferBase mrs5(16); ecmdDataBufferBase mrs6(16); - + uint16_t MRS6 = 0; ecmdDataBufferBase data_buffer(64); - instruction_number = 0; + instruction_number = 0; uint16_t num_ranks = 0; @@ -252,30 +252,49 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ if(rc) return rc; - // WORKAROUNDS + // WORKAROUNDS rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); if(rc) return rc; //Setting up CCS mode rc_num = rc_num | data_buffer.setBit(51); + if (rc_num) + { + FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer); if(rc) return rc; - if(i_port_number==0){ + if(i_port_number==0){ rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); if(rc) return rc; //Setting up CCS mode rc_num = rc_num | data_buffer.clearBit(48); + if (rc_num) + { + FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer); if(rc) return rc; - }else{ - - rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); + } + else{ + + rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); if(rc) return rc; //Setting up CCS mode rc_num = rc_num | data_buffer.clearBit(48); + if (rc_num) + { + FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer); if(rc) return rc; - } + } //Lines commented out in the following section are waiting for xml attribute adds @@ -284,8 +303,8 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ if(rc) return rc; FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]); - - + + //MRS6 uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value - NEW rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value); @@ -296,7 +315,7 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable - NEW rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable); if(rc) return rc; - + FAPI_INF("enable attribute %d",vrefdq_train_enable[0][0][0]); @@ -306,23 +325,23 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ if(rc) return rc; if (tccd_l == 4) { - tccd_l = 0x00; + tccd_l = 0x00; } else if (tccd_l == 5) { - tccd_l = 0x80; + tccd_l = 0x80; } else if (tccd_l == 6) { - tccd_l = 0x40; - } + tccd_l = 0x40; + } else if (tccd_l == 7) { - tccd_l = 0xC0; + tccd_l = 0xC0; } else if (tccd_l == 8) { - tccd_l = 0x20; + tccd_l = 0x20; } // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles @@ -331,6 +350,14 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ rc_num = rc_num | address_16.clearBit(0, 16); rc_num = rc_num | odt_4.clearBit(0,4); rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); + + if (rc_num) + { + FAPI_ERR( "mss_mr6_loader: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, address_16, @@ -343,7 +370,7 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ csn_8, odt_4, ddr_cal_type_4, - i_port_number); + i_port_number); if(rc) return rc; rc = mss_ccs_inst_arry_1( i_target, io_ccs_inst_cnt, @@ -353,7 +380,7 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ read_compare_1, rank_cal_4, ddr_cal_enable_1, - ccs_end_1); + ccs_end_1); if(rc) return rc; io_ccs_inst_cnt ++; @@ -376,38 +403,38 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | address_16.clearBit(0, 16); - //MRS6 + //MRS6 - vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); + vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]); - if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; - } - else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) - { - vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; - } + if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1) + { + vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00; + } + else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2) + { + vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF; + } - if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xff;FAPI_INF("ENABLE is enabled"); - } - else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) - { - vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;FAPI_INF("DISABLE is enabled"); - } + if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE) + { + vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xff;FAPI_INF("ENABLE is enabled"); + } + else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE) + { + vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;FAPI_INF("DISABLE is enabled"); + } rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6); rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1); rc_num = rc_num | mrs6.insertFromRight((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1); - - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2); + + rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2); rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3); - rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2); + rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2); + + rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0); - FAPI_INF( "MRS 6: 0x%04X", MRS6); if (rc_num) @@ -418,31 +445,24 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ } // Only corresponding CS to rank - rc_num = rc_num | csn_8.setBit(0,8); + rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number); - - if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) - { - FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!=====================\n"); + + if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) + { + FAPI_INF( "============= Got in the 3DS stack loop CKE !!!!=====================\n"); rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2); // I'm leaving this commented out - I need to double check it with Luke Mulkey to see which CS's are wired to which CKE's - // rc_num = rc_num | cke_4.clearBit(1); - } - + // rc_num = rc_num | cke_4.clearBit(1); + } + // Propogate through the 4 MRS cmds // Copying the current MRS into address buffer matching the MRS_array order - // Setting the bank address + // Setting the bank address rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } if (rc_num) { @@ -450,7 +470,14 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ rc_buff.setEcmdError(rc_num); return rc_buff; } - // Send out to the CCS array + + if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + if(rc) return rc; + } + + // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, address_16, @@ -476,9 +503,9 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ ccs_end_1); if(rc) return rc; io_ccs_inst_cnt ++; - - // Address inversion for RCD - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + + // Address inversion for RCD + if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n"); @@ -487,35 +514,34 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ // Copying the current MRS into address buffer matching the MRS_array order // Setting the bank address rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0); - rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); + rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7); rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6); rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5); - // Indicate B-Side DRAMS BG1=1 + // Indicate B-Side DRAMS BG1=1 rc_num = rc_num | address_16.setBit(15); // Set BG1 = 1 - + rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9 rc_num = rc_num | address_16.flipBit(11); // Invert A11 rc_num = rc_num | address_16.flipBit(13); // Invert A13 rc_num = rc_num | address_16.flipBit(14); // Invert A17 rc_num = rc_num | bank_3.flipBit(0,3); // Invert BA0,BA1,BG0 - - if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) - { - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); - if(rc) return rc; - } - - + if (rc_num) { FAPI_ERR( " Error setting up buffers"); rc_buff.setEcmdError(rc_num); return rc_buff; } - - // Send out to the CCS array + + if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0)) + { + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3); + if(rc) return rc; + } + + // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, address_16, @@ -542,7 +568,7 @@ ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_ if(rc) return rc; io_ccs_inst_cnt ++; - + } instruction_number = io_ccs_inst_cnt; @@ -550,11 +576,11 @@ rc = add_nop_to_ccs (i_target, address_16,instruction_number,rank_number,MRS6_BA io_ccs_inst_cnt = instruction_number; io_ccs_inst_cnt++; if (rc) return rc; - + } } } - + diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index fcd25952e..bf18b79f2 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.94 2015/01/27 23:23:40 jdsloat Exp $ +// $Id: mss_draminit_training.C,v 1.101 2015/07/14 17:42:00 sglancy Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -30,6 +30,13 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.101 | sglancy |14-JUL-15| Fixed compile issue +// 1.100 | sglancy |13-JUL-15| Fixed compile issue +// 1.99 | sglancy |13-JUL-15| Fixed LR DIMM order of operations and addressed FW comments +// 1.98 | sglancy |24-JUN-15| Added call to DQS offset function +// 1.97 | sglancy |10-JUN-15| Fixed BBM set code call - removed comment of code +// 1.96 | sglancy |27-MAY-15| Added changes for DDR4 3DS +// 1.95 | sglancy |12-MAY-15| Added DDR4 WR VREF set // 1.94 | jdsloat |27-JAN-14| Addressed FW concerns from gerrit. // 1.93 | jdsloat |22-JAN-14| Moved the initialization of rank_invalid within BYTE DISABLE WORKAROUND // 1.92 | jdsloat |20-JAN-14| Added new workaround for BYTE DISABLE and for WR LVL DISABLE. This affects RAS/BBM work. @@ -176,7 +183,7 @@ #include <mss_unmask_errors.H> #include <mss_lrdimm_funcs.H> #include "mss_access_delay_reg.H" - +#include <mss_mrs6_DDR4.H> #ifdef FAPI_LRDIMM #include <mss_lrdimm_ddr4_funcs.H> #endif @@ -221,7 +228,6 @@ fapi::ReturnCode mss_dram_write_leveling(Target& i_target, uint32_t port) } #endif - //------------End My Includes------------------------------------------- //---------------------------------------------------------------------- @@ -253,6 +259,10 @@ enum mss_draminit_training_result extern "C" { + +//Sets the DQS offset to be 16 instead of 8, recommended training settings +fapi::ReturnCode mss_setup_dqs_offset(Target &i_target); + using namespace fapi; ReturnCode mss_draminit_training(Target& i_target); @@ -488,7 +498,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) - if ( ( cal_steps_8.isBitSet(0) ) || ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && @@ -503,15 +512,6 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc = mss_execute_zq_cal(i_target, port); if(rc) return rc; - // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && - (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) - { - rc = mss_mrep_training(i_target, port); - if(rc) return rc; - rc = mss_mxd_training(i_target,port,0); - if(rc) return rc; - } } if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && @@ -523,7 +523,55 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc = mss_execute_lrdimm_mb_dram_training(i_target); if (rc) return rc; } + //executes the following to ensure that DRAMS have a good intial WR VREF DQ + //1) enter training mode w/ old value (nominal VREF DQ) + //2) set value in training mode (nominal VREF DQ) + //3) exit training mode (nominal VREF DQ) + else if(dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) { + FAPI_INF("For DDR4, setting VREFDQ to have an initial value!!!!"); + uint8_t train_enable[2][2][4]; + uint8_t train_enable_override_on[2][2][4] ={{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}},{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}}}; + + rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); + if(rc) return rc; + + rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable_override_on); + if(rc) return rc; + + //runs new values w/ train enable forces on + FAPI_INF("RUN MRS6 1ST"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + FAPI_INF("RUN MRS6 2ND"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + + //set old train enable value + rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); + if(rc) return rc; + + FAPI_INF("RUN MRS6 3RD"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + + //sets up the DQS offset to be 16 instead of 8 + rc = mss_setup_dqs_offset(i_target); + if(rc) return rc; + } + //have to do ZQ cal, then DDR4 training mode for initial VREF setup, then do LR training + for(port = 0; port < MAX_NUM_PORT; port++) + { + // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && + (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + { + rc = mss_mrep_training(i_target, port); + if(rc) return rc; + rc = mss_mxd_training(i_target,port,0); + if(rc) return rc; + } + } } for(port = 0; port < MAX_NUM_PORT; port++) @@ -7019,7 +7067,7 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, } // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); + rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); if (rc) { FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " @@ -7161,7 +7209,7 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); + rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); if (rc) { FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " @@ -7264,4 +7312,40 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, } //end setC4dq2reg +//Sets the DQS offset to be 16 instead of 8, recommended training settings +fapi::ReturnCode mss_setup_dqs_offset(Target &i_target) { + fapi::ReturnCode rc; + uint32_t rc_num = 0; + ecmdDataBufferBase buffer(64); + uint64_t scom_addr_array[10] = {DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_0x800110370301143F}; + + FAPI_INF("DDR4: setting up DQS offset to be 16"); + for(uint8_t scom_addr = 0; scom_addr < 10; ++scom_addr) { + rc = fapiGetScom(i_target, scom_addr_array[scom_addr], buffer); + if(rc) return rc; + //Setting up CCS mode + rc_num = rc_num | buffer.insertFromRight ((uint32_t)16, 49, 7); + if (rc_num) + { + FAPI_ERR( "mss_setup_dqs: Error setting up buffers"); + rc.setEcmdError(rc_num); + return rc; + } + rc = fapiPutScom(i_target, scom_addr_array[scom_addr], buffer); + if(rc) return rc; + } + + return rc; +} + + } //end extern C diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C index da6ea0f77..2c1accbf6 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C +++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,13 +22,12 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_funcs.C,v 1.38 2014/04/01 15:24:50 jdsloat Exp $ +// $Id: mss_funcs.C,v 1.43 2015/09/10 14:57:26 thi Exp $ /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2007 // *! All Rights Reserved -- Property of IBM -// *! *** *** //------------------------------------------------------------------------------ // *! TITLE : mss_funcs.C // *! DESCRIPTION : Tools for centaur procedures @@ -45,6 +44,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.43 | thi |10-SEP-15| Fixed more RC stuff +// 1.42 | kmack |03-SEP-15| Fixed up some RC stuff +// 1.41 | sglancy |21-AUG-15| Fixed ODT initialization bug - ODT must be held low through ZQ cal +// 1.40 | sglancy |09-JUL-15| Added fixes to ZQ cal bug +// 1.39 | sglancy |27-MAY-15| Added fixes to ZQ cal for 3DS DIMMs // 1.38 | jdsloat |01-APL-14| RAS review edits/changes // 1.37 | jdsloat |28-MAR-14| RAS review edits/changes // 1.36 | kcook | 03/12/14| Added check for DDR3 LRDIMM during mss_execut_zq_cal. @@ -66,12 +70,12 @@ // 1.20 | jdsloat | 2/16/12 | Initialize rc_num // 1.19 | 2/14/12 | jdsloat| MBA translation, elminate unnecesary RC returns, got rid of some port arguments // 1.18 | 2/08/12 | jdsloat| Target to Target&, Added Error reporting -// 1.17 | 2/02/12 | jdsloat| Initialized reg_address to 0 +// 1.17 | 2/02/12 | jdsloat| Initialized reg_address to 0 // 1.16 | 1/19/12 | jdsloat| tabs to 4 spaces - properly, cke fix in mss_ccs_inst_arry_0 // 1.15 | 1/16/12 | jdsloat| tabs to 4 spaces // 1.14 | 1/13/12 | jdsloat| Capatilization, curley brackets, "mss_" prefix, adding rc checks, argument prefixes, includes, RC checks // 1.13 | 1/6/12 | jdsloat| Got rid of Globals -// 1.12 | 12/23/11 | bellows | Printout poll count +// 1.12 | 12/23/11 | bellows | Printout poll count // 1.11 | 12/20/11 | bellows | Fixed up ODT default value of 00 for CCS // 1.10 | 12/16/11 | bellows | Bit number correction for ras,cas,wen and cal_type // 1.9 | 12/14/11 | bellows | Fixed Bank and Address bit reversals restored others @@ -132,12 +136,12 @@ ReturnCode mss_ccs_set_end_bit( i_instruction_number = i_instruction_number + 1; FAPI_INF( "Setting End Bit on instruction (NOP): %d.", i_instruction_number); - + // Single NOP with CKE raised high and the end bit set high rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | address_16.clearBit(0, 16); rc_num = rc_num | num_idles_16.clearBit(0, 16); - rc_num = rc_num | odt_4.setBit(0,4); + rc_num = rc_num | odt_4.clearBit(0,4); rc_num = rc_num | csn_8.setBit(0,8); rc_num = rc_num | cke_4.setBit(0,4); rc_num = rc_num | wen_1.clearBit(0); @@ -145,8 +149,12 @@ ReturnCode mss_ccs_set_end_bit( rc_num = rc_num | rasn_1.clearBit(0); rc_num = rc_num | ccs_end_1.setBit(0); - rc.setEcmdError(rc_num); - if(rc) return rc; + if (rc_num) + { + FAPI_ERR( "Error setting up buffers"); + rc.setEcmdError(rc_num); + return rc; + } rc = mss_ccs_inst_arry_0( i_target, i_instruction_number, @@ -160,7 +168,7 @@ ReturnCode mss_ccs_set_end_bit( csn_8, odt_4, ddr_cal_type_4, - l_port_number); + l_port_number); if(rc) return rc; rc = mss_ccs_inst_arry_1( i_target, i_instruction_number, @@ -180,8 +188,8 @@ ReturnCode mss_ccs_set_end_bit( ReturnCode mss_address_mirror_swizzle( Target& i_target, uint32_t i_port, - uint32_t i_dimm, - uint32_t i_rank, + uint32_t i_dimm, + uint32_t i_rank, ecmdDataBufferBase& io_address, ecmdDataBufferBase& io_bank ) @@ -198,77 +206,97 @@ ReturnCode mss_address_mirror_swizzle( rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); if(rc) return rc; - FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank); - - rc_num = rc_num | io_address.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | io_bank.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); - - //Initialize address and bank address as the same pre mirror mode swizzle - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0); - - if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - //Swap A3 and A4 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); - - //Swap A5 and A6 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); - - //Swap A7 and A8 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); - - //Swap BA0 and BA1 - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); - } - else if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) - { - //Swap A3 and A4 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); - - //Swap A5 and A6 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); - - //Swap A7 and A8 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); - - //Swap A11 and A13 - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 13, 1, 11); - rc_num = rc_num | address_post_swizzle_16.insert(io_address, 11, 1, 13); - - //Swap BA0 and BA1 - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); - rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); - - //Swap BG0 and BG1 (BA2 and ADDR 15) - rc_num = rc_num | bank_post_swizzle_3.insert(io_address, 2, 1, 15); - rc_num = rc_num | address_post_swizzle_16.insert(io_bank, 15, 1, 2); - } - - rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); - FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); - rc_num = rc_num | bank_post_swizzle_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); - FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); - - //copy address and bank address back to the IO variables - rc_num = rc_num | io_address.insert(address_post_swizzle_16, 0, 16, 0); - rc_num = rc_num | io_bank.insert(bank_post_swizzle_3, 0, 3, 0); + FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank); - if (rc_num) - { - FAPI_ERR( "Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } + rc_num = rc_num | io_address.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | io_bank.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + + //Initialize address and bank address as the same pre mirror mode swizzle + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0); + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0); + + if (rc_num) + { + FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) + { + //Swap A3 and A4 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); + + //Swap A5 and A6 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); + + //Swap A7 and A8 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); + + //Swap BA0 and BA1 + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); + + if (rc_num) + { + FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + } + else if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + { + //Swap A3 and A4 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4); + + //Swap A5 and A6 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6); + + //Swap A7 and A8 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8); + + //Swap A11 and A13 + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 13, 1, 11); + rc_num = rc_num | address_post_swizzle_16.insert(io_address, 11, 1, 13); + + //Swap BA0 and BA1 + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0); + rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1); + + //Swap BG0 and BG1 (BA2 and ADDR 15) + rc_num = rc_num | bank_post_swizzle_3.insert(io_address, 2, 1, 15); + rc_num = rc_num | address_post_swizzle_16.insert(io_bank, 15, 1, 2); + + if (rc_num) + { + FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + } + + rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0); + FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad); + rc_num = rc_num | bank_post_swizzle_3.extractPreserve(&mirror_mode_ba, 0, 3, 0); + FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba); + + //copy address and bank address back to the IO variables + rc_num = rc_num | io_address.insert(address_post_swizzle_16, 0, 16, 0); + rc_num = rc_num | io_bank.insert(bank_post_swizzle_3, 0, 3, 0); + + if (rc_num) + { + FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } return rc; } @@ -310,11 +338,12 @@ ReturnCode mss_ccs_inst_arry_0( if (i_port == 0xFFFFFFFF) { - i_port = 0; + i_port = 0; } reg_address = io_instruction_number + CCS_INST_ARRY0_AB_REG0_0x03010615; + rc_num = rc_num | data_buffer.flushTo0(); rc_num = rc_num | data_buffer.insert(i_cke, 24, 4, 0); rc_num = rc_num | data_buffer.insert(i_cke, 28, 4, 0); @@ -371,7 +400,7 @@ ReturnCode mss_ccs_inst_arry_1( //CCS_INST_ARRY_1( i_target, io_instruction_number, i_num_idles, i_num_repeat, i_data, i_read_compare, i_rank_cal, i_ddr_cal_enable, i_ccs_end); ReturnCode rc; ReturnCode rc_buff; - uint32_t rc_num = 0; + uint32_t rc_num = 0; uint32_t reg_address = 0; ecmdDataBufferBase goto_inst(5); @@ -418,7 +447,7 @@ ReturnCode mss_ccs_inst_arry_1( ReturnCode mss_ccs_load_data_pattern( Target& i_target, uint32_t io_instruction_number, - mss_ccs_data_pattern data_pattern) + mss_ccs_data_pattern data_pattern) { //Example Use: // @@ -426,19 +455,19 @@ ReturnCode mss_ccs_load_data_pattern( if (data_pattern == MSS_CCS_DATA_PATTERN_00) { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00000000); + rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00000000); } else if (data_pattern == MSS_CCS_DATA_PATTERN_0F) { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00055555); + rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00055555); } else if (data_pattern == MSS_CCS_DATA_PATTERN_F0) { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000aaaaa); + rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000aaaaa); } else if (data_pattern == MSS_CCS_DATA_PATTERN_FF) { - rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000fffff); + rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000fffff); } return rc; @@ -448,13 +477,13 @@ ReturnCode mss_ccs_load_data_pattern( ReturnCode mss_ccs_load_data_pattern( Target& i_target, uint32_t io_instruction_number, - uint32_t data_pattern) + uint32_t data_pattern) { //Example Use: // ReturnCode rc; ReturnCode rc_buff; - uint32_t rc_num = 0; + uint32_t rc_num = 0; uint32_t reg_address = 0; if (io_instruction_number > 31) @@ -469,16 +498,16 @@ ReturnCode mss_ccs_load_data_pattern( //read current array1 reg rc = fapiGetScom(i_target, reg_address, data_buffer); if(rc) return rc; - + //modify data bits for specified pattern rc_num = rc_num | data_buffer.insertFromRight(data_pattern, 32, 20); if (rc_num) - { + { FAPI_ERR( "mss_ccs_load_data_pattern: Error setting up buffers"); rc_buff.setEcmdError(rc_num); return rc_buff; - } - + } + //write array1 back out rc = fapiPutScom(i_target, reg_address, data_buffer); if(rc) return rc; @@ -595,7 +624,7 @@ ReturnCode mss_ccs_status_query( Target& i_target, mss_ccs_status_query_result& { io_status = MSS_STAT_QUERY_PASS; } - else + else { FAPI_INF("CCS Status Undetermined."); } @@ -614,27 +643,27 @@ ReturnCode mss_ccs_fail_type( if (data_buffer.getBit(3)) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; + const ecmdDataBufferBase & REG_CONTENTS = data_buffer; FAPI_ERR("CCS returned a FAIL condtion of \"Read Miscompare\" "); FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_READ_MISCOMPARE); - } + } else if (data_buffer.getBit(4)) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; + const ecmdDataBufferBase & REG_CONTENTS = data_buffer; FAPI_ERR("CCS returned a FAIL condition of \"UE or SUE Error\" "); FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_UE_SUE); } else if (data_buffer.getBit(5)) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; - const ecmdDataBufferBase & REG_CONTENTS = data_buffer; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; + const ecmdDataBufferBase & REG_CONTENTS = data_buffer; FAPI_ERR("CCS returned a FAIL condition of \"Calibration Operation Time Out\" "); FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_CAL_TIMEOUT); @@ -668,35 +697,35 @@ ReturnCode mss_execute_ccs_inst_array( if (status == MSS_STAT_QUERY_FAIL) { - FAPI_ERR("CCS FAILED"); + FAPI_ERR("CCS FAILED"); rc = mss_ccs_fail_type(i_target); if(rc) return rc; FAPI_ERR("CCS has returned a fail."); } else if (status == MSS_STAT_QUERY_IN_PROGRESS) - { + { FAPI_ERR("CCS Operation Hung"); FAPI_ERR("CCS has returned a IN_PROGRESS status and considered Hung."); rc = mss_ccs_fail_type(i_target); if(rc) - { - return rc; - } - else - { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + { + return rc; + } + else + { + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; FAPI_ERR("Returning a CCS HUNG RC Value."); - FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG); - return rc; - } + FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG); + return rc; + } } else if (status == MSS_STAT_QUERY_PASS) { FAPI_INF("CCS Executed Successfully."); } - else + else { FAPI_INF("CCS Status Undetermined."); } @@ -759,24 +788,24 @@ ReturnCode mss_rcd_parity_check( if (rcd_parity_fail) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; FAPI_ERR("Ports 0 and 1 has exceeded a maximum number of RCD Parity Errors."); FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_LIMIT); } else if ((port_0_error) && (i_port == 0)) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; FAPI_ERR("Port 0 has recorded an RCD Parity Error. "); FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT0); } else if ((port_1_error) && (i_port == 1)) { - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_target; + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_target; FAPI_ERR("Port 1 has recorded an RCD Parity Error. "); FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT1); @@ -805,23 +834,26 @@ ReturnCode mss_execute_zq_cal( uint32_t instruction_number = 0; ReturnCode rc; + ReturnCode rc_buff; uint32_t rc_num = 0; + //adds a NOP before ZQ cal ecmdDataBufferBase address_buffer_16(16); - rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0020); //Set A10 bit for ZQCal Long + rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0000); //Set A10 bit for ZQCal Long ecmdDataBufferBase bank_buffer_8(8); rc_num = rc_num | bank_buffer_8.flushTo0(); ecmdDataBufferBase activate_buffer_1(1); rc_num = rc_num | activate_buffer_1.flushTo1(); ecmdDataBufferBase rasn_buffer_1(1); - rc_num = rc_num | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0; + rc_num = rc_num | rasn_buffer_1.flushTo1(); //For NOP rasn = 1; casn = 1; wen = 1; ecmdDataBufferBase casn_buffer_1(1); rc_num = rc_num | casn_buffer_1.flushTo1(); ecmdDataBufferBase wen_buffer_1(1); - rc_num = rc_num | wen_buffer_1.flushTo0(); + rc_num = rc_num | wen_buffer_1.flushTo1(); ecmdDataBufferBase cke_buffer_8(8); rc_num = rc_num | cke_buffer_8.flushTo1(); ecmdDataBufferBase csn_buffer_8(8); + rc_num = rc_num | csn_buffer_8.flushTo1();; ecmdDataBufferBase odt_buffer_8(8); rc_num = rc_num | odt_buffer_8.flushTo0(); ecmdDataBufferBase test_buffer_4(4); @@ -840,7 +872,7 @@ ReturnCode mss_execute_zq_cal( ecmdDataBufferBase ddr_cal_enable_buffer_1(1); rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0(); ecmdDataBufferBase ccs_end_buffer_1(1); - rc_num = rc_num | ccs_end_buffer_1.flushTo1(); + rc_num = rc_num | ccs_end_buffer_1.flushTo0(); ecmdDataBufferBase stop_on_err_buffer_1(1); rc_num = rc_num | stop_on_err_buffer_1.flushTo0(); @@ -849,18 +881,79 @@ ReturnCode mss_execute_zq_cal( ecmdDataBufferBase data_buffer_64(64); rc_num = rc_num | data_buffer_64.flushTo0(); + if (rc_num) + { + FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + instruction_number = 1; + + //now sets up for ZQ CAL + rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0020); //Set A10 bit for ZQCal Long + rc_num = rc_num | bank_buffer_8.flushTo0(); + rc_num = rc_num | activate_buffer_1.flushTo1(); + rc_num = rc_num | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0; + rc_num = rc_num | casn_buffer_1.flushTo1(); + rc_num = rc_num | wen_buffer_1.flushTo0(); + rc_num = rc_num | cke_buffer_8.flushTo1(); + rc_num = rc_num | odt_buffer_8.flushTo0(); + rc_num = rc_num | test_buffer_4.flushTo0(); // 01XX:External ZQ calibration + rc_num = rc_num | test_buffer_4.setBit(1); + rc_num = rc_num | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal + rc_num = rc_num | num_repeat_buffer_16.flushTo0(); + rc_num = rc_num | data_buffer_20.flushTo0(); + rc_num = rc_num | read_compare_buffer_1.flushTo0(); + rc_num = rc_num | rank_cal_buffer_3.flushTo0(); + rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0(); + rc_num = rc_num | ccs_end_buffer_1.flushTo0(); + rc_num = rc_num | stop_on_err_buffer_1.flushTo0(); + rc_num = rc_num | resetn_buffer_1.setBit(0); + rc_num = rc_num | data_buffer_64.flushTo0(); + + if (rc_num) + { + FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; + } + + uint8_t current_rank = 0; uint8_t start_rank = 0; + uint8_t num_master_ranks_array[2][2]; uint8_t num_ranks_array[2][2]; //num_ranks_array[port][dimm] + uint8_t stack_type[2][2]; uint8_t dimm_type; uint8_t lrdimm_rank_mult_mode; uint8_t dram_gen = 0; + uint8_t rank_end = 0; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, stack_type); + if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array); + if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type); if(rc) return rc; @@ -882,18 +975,24 @@ ReturnCode mss_execute_zq_cal( { start_rank=(4 * dimm); - if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ) + if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ) { rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode); if(rc) return rc; - + if ( num_ranks_array[i_port][dimm] == 8 && lrdimm_rank_mult_mode == 4) { // For LRDIMM 8 Rank, RM=4, CS0 and CS1 to execute ZQ cal - num_ranks_array[i_port][dimm] = 2; + rank_end = 2; } } + else if(stack_type[i_port][dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) { + rank_end = num_master_ranks_array[i_port][dimm]; + } + else { + rank_end = num_ranks_array[i_port][dimm]; + } - for(current_rank = start_rank; current_rank < start_rank + num_ranks_array[i_port][dimm]; current_rank++) { + for(current_rank = start_rank; current_rank < start_rank + rank_end; current_rank++) { FAPI_INF( "+++++++++++++++ Sending zqcal to port: %d rank: %d +++++++++++++++", i_port, current_rank); rc_num = rc_num | csn_buffer_8.flushTo1(); rc_num = rc_num | csn_buffer_8.clearBit(current_rank); @@ -909,8 +1008,10 @@ ReturnCode mss_execute_zq_cal( if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + rc = mss_ccs_set_end_bit(i_target,instruction_number); + if(rc) return rc; rc = mss_execute_ccs_inst_array(i_target, NUM_POLL, 60); - instruction_number = 0; + instruction_number = 1; if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs } } diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml index ed1de555d..a0cb54bbd 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2013,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2013,2015 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,7 +22,7 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: memory_mss_eff_config.xml,v 1.3 2014/10/20 22:12:59 asaetow Exp $ --> +<!-- $Id: memory_mss_eff_config.xml,v 1.6 2015/08/04 21:30:25 asaetow Exp $ --> <!-- For file ../../ipl/fapi/mss_eff_config.C --> <!-- // *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com --> <!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> @@ -30,6 +30,42 @@ <!-- *********************************************************************** --> <hwpError> + <rc>RC_MSS_EFF_CONFIG_INVALID_DDR4_SPD_TB</rc> + <description>Invalid DDR4 MTB/FTB Timebase received from SPD attribute</description> + <FFDC>TARGET_DIMM</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_DIMM</target> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET_DIMM</target> + </deconfigure> + </hwpError> + +<!-- *********************************************************************** --> + <hwpError> + <rc>RC_MSS_EFF_CONFIG_INCOMPATABLE_SPD_DRAM_GEN</rc> + <description>Incompatable SPD DRAM generation</description> + <FFDC>TARGET_DIMM</FFDC> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET_DIMM</target> + <priority>LOW</priority> + </callout> + <deconfigure> + <target>TARGET_DIMM</target> + </deconfigure> + </hwpError> + +<!-- *********************************************************************** --> + <hwpError> <rc>RC_MSS_EFF_CONFIG_INVALID_RDIMM_FREQ</rc> <description>Invalid RDIMM ATTR_MSS_FREQ, freq is higher than 1600Mbps</description> <FFDC>TARGET_MBA</FFDC> @@ -39,17 +75,20 @@ <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>LOW</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -63,17 +102,20 @@ <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>LOW</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -90,17 +132,20 @@ <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>LOW</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -117,17 +162,20 @@ <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>LOW</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -169,27 +217,29 @@ <description>Plug rule violation, one position is empty but other are present </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -198,28 +248,30 @@ <description>Plug rule violation, sides do not match </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> @@ -229,28 +281,30 @@ <description>Plug rule violation, top and bottom do not match </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -259,28 +313,30 @@ <description>Incompatable DRAM generation </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>DRAM_DEVICE_TYPE_0_0</ffdc> - <ffdc>DRAM_DEVICE_TYPE_0_1</ffdc> - <ffdc>DRAM_DEVICE_TYPE_1_0</ffdc> - <ffdc>DRAM_DEVICE_TYPE_1_1</ffdc> + <ffdc>DRAM_DEVICE_TYPE_0_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_0_1</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -289,28 +345,30 @@ <description>Incompatable DIMM type </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>MODULE_TYPE_0_0</ffdc> - <ffdc>MODULE_TYPE_0_1</ffdc> - <ffdc>MODULE_TYPE_1_0</ffdc> - <ffdc>MODULE_TYPE_1_1</ffdc> + <ffdc>MODULE_TYPE_0_0</ffdc> + <ffdc>MODULE_TYPE_0_1</ffdc> + <ffdc>MODULE_TYPE_1_0</ffdc> + <ffdc>MODULE_TYPE_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -319,28 +377,30 @@ <description>Incompatable DIMM ranks </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>NUM_RANKS_0_0</ffdc> - <ffdc>NUM_RANKS_0_1</ffdc> - <ffdc>NUM_RANKS_1_0</ffdc> - <ffdc>NUM_RANKS_1_1</ffdc> + <ffdc>NUM_RANKS_0_0</ffdc> + <ffdc>NUM_RANKS_0_1</ffdc> + <ffdc>NUM_RANKS_1_0</ffdc> + <ffdc>NUM_RANKS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -349,28 +409,30 @@ <description>Incompatable DIMM banks </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_BANKS_0_0</ffdc> - <ffdc>SDRAM_BANKS_0_1</ffdc> - <ffdc>SDRAM_BANKS_1_0</ffdc> - <ffdc>SDRAM_BANKS_1_1</ffdc> + <ffdc>SDRAM_BANKS_0_0</ffdc> + <ffdc>SDRAM_BANKS_0_1</ffdc> + <ffdc>SDRAM_BANKS_1_0</ffdc> + <ffdc>SDRAM_BANKS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -379,28 +441,30 @@ <description>Incompatable DIMM rows </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_ROWS_0_0</ffdc> - <ffdc>SDRAM_ROWS_0_1</ffdc> - <ffdc>SDRAM_ROWS_1_0</ffdc> - <ffdc>SDRAM_ROWS_1_1</ffdc> + <ffdc>SDRAM_ROWS_0_0</ffdc> + <ffdc>SDRAM_ROWS_0_1</ffdc> + <ffdc>SDRAM_ROWS_1_0</ffdc> + <ffdc>SDRAM_ROWS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -409,28 +473,30 @@ <description>Incompatable DIMM columns </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_COLS_0_0</ffdc> - <ffdc>SDRAM_COLS_0_1</ffdc> - <ffdc>SDRAM_COLS_1_0</ffdc> - <ffdc>SDRAM_COLS_1_1</ffdc> + <ffdc>SDRAM_COLS_0_0</ffdc> + <ffdc>SDRAM_COLS_0_1</ffdc> + <ffdc>SDRAM_COLS_1_0</ffdc> + <ffdc>SDRAM_COLS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -439,28 +505,30 @@ <description>Incompatable DRAM primary bus width </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>BUS_WIDTH_0_0</ffdc> - <ffdc>BUS_WIDTH_0_1</ffdc> - <ffdc>BUS_WIDTH_1_0</ffdc> - <ffdc>BUS_WIDTH_1_1</ffdc> + <ffdc>BUS_WIDTH_0_0</ffdc> + <ffdc>BUS_WIDTH_0_1</ffdc> + <ffdc>BUS_WIDTH_1_0</ffdc> + <ffdc>BUS_WIDTH_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> @@ -476,17 +544,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> @@ -496,28 +566,30 @@ <description>Incompatable DRAM width </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>DRAM_WIDTH_0_0</ffdc> - <ffdc>DRAM_WIDTH_0_1</ffdc> - <ffdc>DRAM_WIDTH_1_0</ffdc> - <ffdc>DRAM_WIDTH_1_1</ffdc> + <ffdc>DRAM_WIDTH_0_0</ffdc> + <ffdc>DRAM_WIDTH_0_1</ffdc> + <ffdc>DRAM_WIDTH_1_0</ffdc> + <ffdc>DRAM_WIDTH_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -532,18 +604,20 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -558,18 +632,20 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -584,17 +660,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -609,17 +687,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -634,17 +714,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -659,17 +741,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -684,17 +768,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -709,17 +795,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -734,17 +822,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -759,17 +849,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -784,17 +876,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -809,17 +903,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -834,17 +930,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> <!-- *********************************************************************** --> @@ -859,17 +957,19 @@ <priority>LOW</priority> </callout> <callout> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET_MBA</target> + <childTargets> + <parent>TARGET_MBA</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> - <gard> - <target>TARGET_MBA</target> - <priority>HIGH</priority> - </gard> </hwpError> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml index 204694a9f..bb8a0ac61 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml @@ -5,7 +5,9 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> +<!-- Contributors Listed Below - COPYRIGHT 2013,2015 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> <!-- you may not use this file except in compliance with the License. --> @@ -21,7 +23,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- $Id: memory_mss_eff_grouping.xml,v 1.3 2014/04/10 18:51:55 jdsloat Exp $ --> +<!-- $Id: memory_mss_eff_grouping.xml,v 1.6 2015/07/15 21:41:12 asaetow Exp $ --> <!-- For file ../../ipl/fapi/mss_eff_grouping.C --> <hwpError> @@ -95,8 +97,18 @@ <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <callout> + <childTargets> + <parent>MEMBUF</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> + <priority>LOW</priority> + </callout> <deconfigure> - <target>MEMBUF</target> + <childTargets> + <parent>MEMBUF</parent> + <childType>TARGET_TYPE_DIMM</childType> + </childTargets> </deconfigure> </hwpError> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C index 525ef5d9a..ef02bd407 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config.C,v 1.51 2015/03/13 19:13:44 asaetow Exp $ +// $Id: mss_eff_config.C,v 1.54 2015/08/13 15:08:17 asaetow Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ // centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ //------------------------------------------------------------------------------ @@ -32,7 +32,7 @@ // *! TITLE : mss_eff_config // *! DESCRIPTION : see additional comments below // *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! BACKUP NAME : Briana Foxworth Email: beforwor@us.ibm.com // *! ADDITIONAL COMMENTS : // // The purpose of this procedure is to setup attributes used in other mss @@ -45,6 +45,16 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.54 | asaetow |13-AUG-15| Added ATTR_SPD_SDRAM_ROWS=R17 and ATTR_SPD_SDRAM_ROWS=R18 for DDR4. +// 1.53 | asaetow |31-JUL-15| Changed code based on FW code review. +// | | | Added RC_MSS_EFF_CONFIG_INVALID_DDR4_SPD_TB and RC_MSS_EFF_CONFIG_INCOMPATABLE_SPD_DRAM_GEN. +// | | | Fixed attribute naming convension from ATTR_TCCD_L to ATTR_EFF_DRAM_TCCD_L and ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS to ATTR_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS. +// | | | NOTE: DO NOT pickup w/o memory_attributes.xml v1.153 or newer +// | | | NOTE: DO NOT pickup w/o memory_mss_eff_config.xml v1.6 or newer +// 1.52 | asaetow |10-MAY-15| Added initial official DDR4 support to mainline. +// | | | NOTE: Merge of mss_eff_config_ddr4.C v1.1 from Menlo. +// | | | NOTE: LRDIMM and TSV not fully supported in this version. +// | | | Changed backup owner. // 1.51 | asaetow |13-MAR-15| Changed DRAM_AL to be CL-2 in 2N/2T mode and CL-1 in 1N/1T mode. // 1.50 | jdsloat |03-DEC-14| Removed string data types that are not supported. // 1.49 | asaetow |01-DEC-14| Added RDIMM SPD/VPD support for ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15 to take in SPD bits69:76 thru new VPD attribute ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15. @@ -197,9 +207,6 @@ #include <mss_lrdimm_funcs.H> #endif -#ifdef FAPI_DDR4 -#include <mss_eff_config_ddr4.H> -#endif //------------------------------------------------------------------------------ @@ -245,17 +252,6 @@ fapi::ReturnCode mss_eff_config_termination( const Target& i_target_mba) } #endif -#ifndef FAPI_DDR4 -fapi::ReturnCode mss_eff_config_ddr4( const Target& i_target_mba) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of DDR4 function on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DDR4_INVALID_EXEC); - return rc; - -} -#endif //------------------------------------------------------------------------------ @@ -285,6 +281,9 @@ struct mss_eff_config_data uint8_t dram_trtp; uint8_t dram_twtr; uint8_t dram_wr; + uint8_t dram_trrdl; + uint8_t dram_tccdl; + uint8_t dram_twtrl; }; //------------------------------------------------------------------------------ @@ -315,15 +314,25 @@ struct mss_eff_config_spd_data //uint8_t taamin[PORT_SIZE][DIMM_SIZE]; uint8_t twrmin[PORT_SIZE][DIMM_SIZE]; uint8_t trcdmin[PORT_SIZE][DIMM_SIZE]; - uint8_t trrdmin[PORT_SIZE][DIMM_SIZE]; + uint8_t trrdmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only uint8_t trpmin[PORT_SIZE][DIMM_SIZE]; uint32_t trasmin[PORT_SIZE][DIMM_SIZE]; uint32_t trcmin[PORT_SIZE][DIMM_SIZE]; - uint32_t trfcmin[PORT_SIZE][DIMM_SIZE]; - uint8_t twtrmin[PORT_SIZE][DIMM_SIZE]; + uint32_t trfcmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only + uint8_t twtrmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only uint8_t trtpmin[PORT_SIZE][DIMM_SIZE]; uint32_t tfawmin[PORT_SIZE][DIMM_SIZE]; + // DDR4 only + uint8_t trrdsmin[PORT_SIZE][DIMM_SIZE]; + uint8_t trrdlmin[PORT_SIZE][DIMM_SIZE]; + uint8_t tccdlmin[PORT_SIZE][DIMM_SIZE]; + uint32_t trfc1min[PORT_SIZE][DIMM_SIZE]; + uint32_t trfc2min[PORT_SIZE][DIMM_SIZE]; + uint32_t trfc4min[PORT_SIZE][DIMM_SIZE]; + uint8_t twtrsmin[PORT_SIZE][DIMM_SIZE]; + uint8_t twtrlmin[PORT_SIZE][DIMM_SIZE]; + // Not needed for GA1 CDIMM, will need to enable check for ISDIMM. //uint8_t sdram_optional_features[PORT_SIZE][DIMM_SIZE]; //uint8_t sdram_thermal_and_refresh_options[PORT_SIZE][DIMM_SIZE]; @@ -369,6 +378,7 @@ struct mss_eff_config_atts uint8_t eff_dimm_ranks_configed[PORT_SIZE][DIMM_SIZE]; // Using SPD byte68,69:76, enabled in GA2 for full RDIMM support uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE]; + uint64_t eff_lrdimm_additional_cntl_words[PORT_SIZE][DIMM_SIZE]; // LRDIMMs only uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE]; uint8_t eff_dimm_type; uint8_t eff_custom_dimm; @@ -415,14 +425,14 @@ struct mss_eff_config_atts uint8_t eff_mpr_loc; uint8_t eff_mpr_mode; - // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0, removed for GA1 - //uint8_t eff_num_dies_per_package[PORT_SIZE][DIMM_SIZE]; + // AST HERE: Needs SPD DDR3 byte33[6:4], DDR4 byte6[6:4] currently hard coded to 0 + uint8_t eff_num_dies_per_package[PORT_SIZE][DIMM_SIZE]; uint8_t eff_num_drops_per_port; uint8_t eff_num_master_ranks_per_dimm[PORT_SIZE][DIMM_SIZE]; - // AST HERE: Needs source data, currently hard coded to 0, removed for GA1 - //uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE]; + // AST HERE: Needs source data, currently hard coded to 0 + uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE]; uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE]; uint8_t eff_schmoo_mode; @@ -453,7 +463,9 @@ struct mss_eff_config_atts uint8_t dimm_functional_vector; uint8_t mss_cal_step_enable; // Always run all cal steps uint32_t eff_vpd_version; - + uint8_t eff_dram_trrdl; + uint8_t eff_dram_tccdl; + uint8_t eff_dram_twtrl; }; //------------------------------------------------------------------------------ @@ -549,6 +561,7 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, uint8_t i_port, uint8_t i_dimm) { fapi::ReturnCode rc; + const fapi::Target& TARGET_DIMM = i_target_dimm; // Grab DIMM/SPD data. do { @@ -591,18 +604,6 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, &i_target_dimm, p_o_spd_data->module_memory_bus_width[i_port][i_dimm]); if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &i_target_dimm, - p_o_spd_data->ftb_dividend[i_port][i_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &i_target_dimm, - p_o_spd_data->ftb_divisor[i_port][i_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVIDEND, &i_target_dimm, - p_o_spd_data->mtb_dividend[i_port][i_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVISOR, &i_target_dimm, - p_o_spd_data->mtb_divisor[i_port][i_dimm]); - if(rc) break; // See mss_freq.C //rc = FAPI_ATTR_GET(ATTR_SPD_TCKMIN, &i_target_dimm, @@ -614,16 +615,150 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, //rc = FAPI_ATTR_GET(ATTR_SPD_TAAMIN, &i_target_dimm, //p_o_spd_data->taamin[i_port][i_dimm]); //if(rc) break; + + if (p_o_spd_data->dram_device_type[i_port][i_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { + // DDR3 only + rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &i_target_dimm, + p_o_spd_data->ftb_dividend[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &i_target_dimm, + p_o_spd_data->ftb_divisor[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVIDEND, &i_target_dimm, + p_o_spd_data->mtb_dividend[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVISOR, &i_target_dimm, + p_o_spd_data->mtb_divisor[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TRRDMIN, &i_target_dimm, + p_o_spd_data->trrdmin[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TRFCMIN, &i_target_dimm, + p_o_spd_data->trfcmin[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TWTRMIN, &i_target_dimm, + p_o_spd_data->twtrmin[i_port][i_dimm]); + if(rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_TWRMIN, &i_target_dimm, + p_o_spd_data->twrmin[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TRTPMIN, &i_target_dimm, + p_o_spd_data->trtpmin[i_port][i_dimm]); + if(rc) break; + + } else if (p_o_spd_data->dram_device_type[i_port][i_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + // DDR4 only + uint8_t l_spd_tb_mtb_ddr4, l_spd_tb_ftb_ddr4; + rc = FAPI_ATTR_GET(ATTR_SPD_TIMEBASE_MTB_DDR4, &i_target_dimm, + l_spd_tb_mtb_ddr4); + if (rc) break; + + rc = FAPI_ATTR_GET(ATTR_SPD_TIMEBASE_FTB_DDR4, &i_target_dimm, + l_spd_tb_ftb_ddr4); + if (rc) break; + + if ( (l_spd_tb_mtb_ddr4 != 0)||(l_spd_tb_ftb_ddr4 != 0) ) + { + FAPI_ERR("Invalid DDR4 MTB/FTB Timebase received from SPD attribute on %s!", i_target_dimm.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_DDR4_SPD_TB); + break; + } + // AST HERE: !If DDR4 spec changes to include other values, this section needs to be updated! + // for 1000fs = 1ps = 1000 * 1 / 1 + p_o_spd_data->ftb_dividend[i_port][i_dimm] = 1; + p_o_spd_data->ftb_divisor[i_port][i_dimm] = 1; + // for 125ps = 1000 * 1 / 8 + p_o_spd_data->mtb_dividend[i_port][i_dimm] = 1; + p_o_spd_data->mtb_divisor[i_port][i_dimm] = 8; + + // not available in ddr4 spd, these are replacements. need to double check + // 15 ns for all speeds + p_o_spd_data->twrmin[i_port][i_dimm] = 15000 / ( + (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) / + p_o_spd_data->mtb_divisor[i_port][i_dimm]); + + // 7.5ns = 7500ps; work backwards to figure out value. no FTB + p_o_spd_data->trtpmin[i_port][i_dimm] = 7500 / ( + (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) / + p_o_spd_data->mtb_divisor[i_port][i_dimm]); + + // 3 trfc values, 1x, 2x, 4x + rc = FAPI_ATTR_GET(ATTR_SPD_TRFC1MIN_DDR4, &i_target_dimm, + p_o_spd_data->trfc1min[i_port][i_dimm]); + if(rc) break; + +// FW is reading out and giving the data in big endian format for some reason. +// need to fix this... XML is documented correctly. +/* // if (p_o_spd_data->trfc1min[i_port][i_dimm] > 0xFFF) { + p_o_spd_data->trfc1min[i_port][i_dimm] |= + (p_o_spd_data->trfc1min[i_port][i_dimm] & 0xFF) << 16; + p_o_spd_data->trfc1min[i_port][i_dimm] = + p_o_spd_data->trfc1min[i_port][i_dimm] >> 8; +// } +*/ +// need to look at this more sometimes the bytes are swapped in SPD... + switch(p_o_spd_data->trfc1min[i_port][i_dimm]) + { + case 0x0005: + p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0500; + break; + case 0x2008: + p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0820; + break; + case 0xF00A: + p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0AF0; + break; + } + + rc = FAPI_ATTR_GET(ATTR_SPD_TRFC2MIN_DDR4, &i_target_dimm, + p_o_spd_data->trfc2min[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TRFC4MIN_DDR4, &i_target_dimm, + p_o_spd_data->trfc4min[i_port][i_dimm]); + if(rc) break; + + // ddr4 has 's' (short; different bank group) and + // 'l' (long; same bank group) values + // tRRD needs to be used by Yuen's mba initfile... + rc = FAPI_ATTR_GET(ATTR_SPD_TRRDSMIN_DDR4, &i_target_dimm, + p_o_spd_data->trrdsmin[i_port][i_dimm]); + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TRRDLMIN_DDR4, &i_target_dimm, + p_o_spd_data->trrdlmin[i_port][i_dimm]); + if(rc) break; + + // tccdl + rc = FAPI_ATTR_GET(ATTR_SPD_TCCDLMIN_DDR4, &i_target_dimm, + p_o_spd_data->tccdlmin[i_port][i_dimm]); + if(rc) break; + + // should be constant based on MTB and FTB after calculations + // where is this used?? +/* SPD attributes not available yet + rc = FAPI_ATTR_GET(ATTR_SPD_TWTRSMIN_DDR4, &i_target_dimm, + p_o_spd_data->twtrsmin[i_port][i_dimm]); // 2.5ns + if(rc) break; + rc = FAPI_ATTR_GET(ATTR_SPD_TWTRLMIN_DDR4, &i_target_dimm, + p_o_spd_data->twtrlmin[i_port][i_dimm]); // 7.5ns + if(rc) break; +*/ + p_o_spd_data->twtrsmin[i_port][i_dimm] = 2500 / ( // 2.5 ns + (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) / + p_o_spd_data->mtb_divisor[i_port][i_dimm]); + p_o_spd_data->twtrlmin[i_port][i_dimm] = 7500 / ( // 7.5 ns + (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) / + p_o_spd_data->mtb_divisor[i_port][i_dimm]); + } else { + FAPI_ERR("Incompatable SPD DRAM generation on %s!", i_target_dimm.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_SPD_DRAM_GEN); + return rc; + } - rc = FAPI_ATTR_GET(ATTR_SPD_TWRMIN, &i_target_dimm, - p_o_spd_data->twrmin[i_port][i_dimm]); - if(rc) break; + // Common for DDR3 and DDR4 rc = FAPI_ATTR_GET(ATTR_SPD_TRCDMIN, &i_target_dimm, p_o_spd_data->trcdmin[i_port][i_dimm]); if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_TRRDMIN, &i_target_dimm, - p_o_spd_data->trrdmin[i_port][i_dimm]); - if(rc) break; rc = FAPI_ATTR_GET(ATTR_SPD_TRPMIN, &i_target_dimm, p_o_spd_data->trpmin[i_port][i_dimm]); if(rc) break; @@ -633,15 +768,6 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm, rc = FAPI_ATTR_GET(ATTR_SPD_TRCMIN, &i_target_dimm, p_o_spd_data->trcmin[i_port][i_dimm]); if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_TRFCMIN, &i_target_dimm, - p_o_spd_data->trfcmin[i_port][i_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_TWTRMIN, &i_target_dimm, - p_o_spd_data->twtrmin[i_port][i_dimm]); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_SPD_TRTPMIN, &i_target_dimm, - p_o_spd_data->trtpmin[i_port][i_dimm]); - if(rc) break; rc = FAPI_ATTR_GET(ATTR_SPD_TFAWMIN, &i_target_dimm, p_o_spd_data->tfawmin[i_port][i_dimm]); if(rc) break; @@ -1331,6 +1457,9 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( //------------------------------------------------------------------------------ switch(p_i_data->sdram_banks[0][0]) { + case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B4: + p_o_atts->eff_dram_banks = 4; // DDR4 only + break; case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8: p_o_atts->eff_dram_banks = 8; break; @@ -1367,6 +1496,12 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R16: p_o_atts->eff_dram_rows = 16; break; + case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R17: + p_o_atts->eff_dram_rows = 17; + break; + case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R18: + p_o_atts->eff_dram_rows = 18; + break; default: FAPI_ERR("Unknown DRAM rows on %s!", i_target_mba.toEcmdString()); uint8_t& SDRAM_ROWS= p_i_data->sdram_rows[0][0]; @@ -1555,6 +1690,8 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_i_mss_eff_config_data->dram_trcd; } //------------------------------------------------------------------------------ + if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { + // DDR3 p_i_mss_eff_config_data->dram_trrd = calc_timing_in_clk ( p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] @@ -1572,6 +1709,165 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_trrd = p_i_mss_eff_config_data->dram_trrd; } + } else if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + // DDR4 + FAPI_INF("DDR4 Check: spd tRRDs=0x%x, tRRDl=0x%x, mtb=%i, ftb=%i, width=%i", + p_i_data->trrdsmin[l_cur_mba_port][l_cur_mba_dimm], + p_i_data->trrdlmin[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_o_atts->eff_dram_width); + const uint8_t min_delay_clocks = 4; + uint32_t max_delay; // in ps + // bool is_2K_page = 0; + + // get the spd min trrd in clocks + p_i_mss_eff_config_data->dram_trrd = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_data->trrdsmin[l_cur_mba_port][l_cur_mba_dimm], + 0, // need to put in the trrdsmin_ftb here... + p_i_mss_eff_config_data->mss_freq + ); + + // trrdsmin from SPD is absolute min of DIMM. + // need to know page size, then use 6ns for (2k page) otherwise 5ns + + FAPI_INF("DDR4 Check: p_i_tRRD_s(nCK) = %i", p_i_mss_eff_config_data->dram_trrd); + FAPI_INF("Attribute p_o_eff_dram_trrd = %i", p_o_atts->eff_dram_trrd); + // need a table here for other speeds/page sizes + + // trrd_s = 2K page @ 1600, max(4nCK,6ns) since min nCK=1.25ns, const 6ns + // 1/2 or 1K page @ 1600, max(4nCK, 5ns) + + // 1600 1866 2133 2400 (data rate) + // 6, 5.3, 5.3, 5.3 ns for 2k page size (x16) + // 5, 4.2, 3.7, 3.3 ns for 0.5k or 1k page size (x8) + // !! NOTE !! NOT supporting 2k page size (with check for width above should cause error out). + + if (p_i_mss_eff_config_data->mss_freq < 1733) // 1600 + { + max_delay = 5000; // in ps + } + else if (p_i_mss_eff_config_data->mss_freq < 2000) // 1866 + { + max_delay = 4200; // in ps + } + else if (p_i_mss_eff_config_data->mss_freq < 2267) // 2133 + { + max_delay = 3700; // in ps + } + else // if (p_i_mss_eff_config_data->mss_freq < 2533) // 2400 + { + max_delay = 3300; // in ps + } +/* else if (p_i_mss_eff_config_data->mss_freq < 2933) // 2666 + { + max_delay = ??00; // in ps + } + else // if (p_i_mss_eff_config_data->mss_freq < ????) // 3200 + { + max_delay = ??00; // in ps + } + +*/ + uint8_t max_delay_clocks = calc_timing_in_clk + (1, 0, max_delay, 0, p_i_mss_eff_config_data->mss_freq); + + // find max between min_delay_clocks, max_delay_clocks and dev_min + + if (min_delay_clocks > max_delay_clocks) + max_delay_clocks = min_delay_clocks; + + if (p_i_mss_eff_config_data->dram_trrd > max_delay_clocks) + max_delay_clocks = p_i_mss_eff_config_data->dram_trrd; + + if (max_delay_clocks > p_o_atts->eff_dram_trrd) + p_o_atts->eff_dram_trrd = max_delay_clocks; + +//--------------------------------------------------------------------------------------- +// trrd_l = max(4nCK,7.5ns) + // 1600 1866 2133 2400 (data rate) + // 7.5 6.4, 6.4, 6.4 ns for 2k page size (x16) + // 6, 5.3, 5.3, 4.9 ns for 0.5k or 1k page size (x8) + // !! NOTE !! NOT supporting 2k page size (with check for width above should cause error out). + p_i_mss_eff_config_data->dram_trrdl = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_data->trrdlmin[l_cur_mba_port][l_cur_mba_dimm], + 0, // need to put in the trrdlmin_ftb here... + p_i_mss_eff_config_data->mss_freq + ); + + // condense this later with the if/else above... + if (p_i_mss_eff_config_data->mss_freq < 1733) // 1600 + { + max_delay = 6000; // in ps + } + else if (p_i_mss_eff_config_data->mss_freq < 2000) // 1866 + { + max_delay = 5300; // in ps + } + else if (p_i_mss_eff_config_data->mss_freq < 2267) // 2133 + { + max_delay = 5300; // in ps + } + else // if (p_i_mss_eff_config_data->mss_freq < 2533) // 2400 + { + max_delay = 4900; // in ps + } +/* else if (p_i_mss_eff_config_data->mss_freq < 2933) // 2666 + { + max_delay = ??00; // in ps + } + else // if (p_i_mss_eff_config_data->mss_freq < ????) // 3200 + { + max_delay = ??00; // in ps + } + +*/ + max_delay_clocks = calc_timing_in_clk + (1, 0, max_delay, 0, p_i_mss_eff_config_data->mss_freq); + if (max_delay_clocks > p_o_atts->eff_dram_trrdl) + { + p_o_atts->eff_dram_trrdl = max_delay_clocks; + } + else if (p_i_mss_eff_config_data->dram_trrdl > p_o_atts->eff_dram_trrdl) + { + p_o_atts->eff_dram_trrdl = p_i_mss_eff_config_data->dram_trrdl; + } + FAPI_INF("DDR4 tRRDs = %i, tRRDl = %i", p_o_atts->eff_dram_trrd, p_o_atts->eff_dram_trrdl); + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } +//------------------------------------------------------------------------------ + if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + p_i_mss_eff_config_data->dram_tccdl = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_data->tccdlmin[l_cur_mba_port] + [l_cur_mba_dimm], + 0, + p_i_mss_eff_config_data->mss_freq + ); + if (p_i_mss_eff_config_data->dram_tccdl > + p_o_atts->eff_dram_tccdl) + { + p_o_atts->eff_dram_tccdl = + p_i_mss_eff_config_data->dram_tccdl; + } + } //------------------------------------------------------------------------------ p_i_mss_eff_config_data->dram_trp = calc_timing_in_clk ( @@ -1590,6 +1886,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_trp = p_i_mss_eff_config_data->dram_trp; } //------------------------------------------------------------------------------ + if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { p_i_mss_eff_config_data->dram_twtr = calc_timing_in_clk ( p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] @@ -1601,12 +1898,55 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( 0, p_i_mss_eff_config_data->mss_freq ); - if (p_i_mss_eff_config_data->dram_twtr > - p_o_atts->eff_dram_twtr) + if (p_i_mss_eff_config_data->dram_twtr > p_o_atts->eff_dram_twtr) { - p_o_atts->eff_dram_twtr = - p_i_mss_eff_config_data->dram_twtr; + p_o_atts->eff_dram_twtr = p_i_mss_eff_config_data->dram_twtr; + } + } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + p_i_mss_eff_config_data->dram_twtr = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_data->twtrsmin[l_cur_mba_port] + [l_cur_mba_dimm], + 0, + p_i_mss_eff_config_data->mss_freq + ); + // twtr_s = max(2nCK,2.5ns) since min nCK=1.25ns, const 2.5ns + //FAPI_INF("DDR4 Check: tWTR in CLKS = %i (2.5ns)", p_i_mss_eff_config_data->dram_twtr); + //FAPI_INF("Attribute eff_dram_twtr = %i", p_o_atts->eff_dram_twtr); + p_o_atts->eff_dram_twtr = p_i_mss_eff_config_data->dram_twtr; + + // twtr_l = max(4nCK,7.5ns) + p_i_mss_eff_config_data->dram_twtrl = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_data->twtrlmin[l_cur_mba_port] + [l_cur_mba_dimm], + 0, + p_i_mss_eff_config_data->mss_freq + ); + + if (p_i_mss_eff_config_data->dram_twtrl < 4) { + p_o_atts->eff_dram_twtrl = 4; + } else { + p_o_atts->eff_dram_twtrl = p_i_mss_eff_config_data->dram_twtrl; } + FAPI_INF("DDR4 twtrs = %i, twtrl = %i", p_o_atts->eff_dram_twtr, p_o_atts->eff_dram_twtrl); + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } //------------------------------------------------------------------------------ p_i_mss_eff_config_data->dram_trtp = calc_timing_in_clk ( @@ -1619,12 +1959,30 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( 0, p_i_mss_eff_config_data->mss_freq ); - if (p_i_mss_eff_config_data->dram_trtp > - p_o_atts->eff_dram_trtp) + if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { + if (p_i_mss_eff_config_data->dram_trtp > p_o_atts->eff_dram_trtp) { + p_o_atts->eff_dram_trtp = p_i_mss_eff_config_data->dram_trtp; + } + } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + // max (4nCK, 7.5ns), 7.5ns= + //FAPI_INF("DDR4 Check: tRTP in CLKS = %i (should be 6)", p_i_mss_eff_config_data->dram_trtp); + //FAPI_INF("Attribute eff_dram_trtp= %i", p_o_atts->eff_dram_trtp); + if (p_i_mss_eff_config_data->dram_trtp < 4) { - p_o_atts->eff_dram_trtp = - p_i_mss_eff_config_data->dram_trtp; + p_o_atts->eff_dram_trtp = 4; + } else { + p_o_atts->eff_dram_trtp = p_i_mss_eff_config_data->dram_trtp; } + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } + //------------------------------------------------------------------------------ p_i_mss_eff_config_data->dram_tras = calc_timing_in_clk ( @@ -1663,6 +2021,7 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_i_mss_eff_config_data->dram_trc; } //------------------------------------------------------------------------------ + if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { p_i_mss_eff_config_data->dram_trfc = calc_timing_in_clk ( p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] @@ -1680,7 +2039,42 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_trfc = p_i_mss_eff_config_data->dram_trfc; } + } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + p_i_mss_eff_config_data->dram_trfc = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port] + [l_cur_mba_dimm], + p_i_data->trfc1min[l_cur_mba_port] + [l_cur_mba_dimm], + 0, + p_i_mss_eff_config_data->mss_freq + ); + FAPI_INF("DDR4 Check: spd trfc = 0x%x (%i clks), o_attr=0x%x", + p_i_data->trfc1min[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->dram_trfc, + p_o_atts->eff_dram_trfc + ); + if (p_i_mss_eff_config_data->dram_trfc > + p_o_atts->eff_dram_trfc) + { + p_o_atts->eff_dram_trfc = + p_i_mss_eff_config_data->dram_trfc; + } + // AST HERE: Need DDR4 attributes for other refresh rates, 2x, 4x + + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } //------------------------------------------------------------------------------ + if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { p_i_mss_eff_config_data->dram_tfaw = calc_timing_in_clk ( p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port] @@ -1698,49 +2092,181 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( p_o_atts->eff_dram_tfaw_u32 = p_i_mss_eff_config_data->dram_tfaw; } + } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + p_i_mss_eff_config_data->dram_tfaw = calc_timing_in_clk + ( + p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm], + p_i_data->tfawmin[l_cur_mba_port][l_cur_mba_dimm], + 0, + p_i_mss_eff_config_data->mss_freq + ); +FAPI_DBG("DDR4 Check: SPD=0x%x, p_i_tFAWmin (nCK) = %i", + p_i_data->tfawmin[l_cur_mba_port][l_cur_mba_dimm], p_i_mss_eff_config_data->dram_tfaw); + + // example x8, 1600, min= 25ns => 25/1.25 = 20 clocks + const uint8_t min_clks [][6] = { // width, data rate + // NOTE: 2666 and 3200 are TBD, using guess values + // 1600 1866 2133 2400 2666 3200 + { 16, 16, 16, 16, 16, 16}, // x4 (page size = 1/2K) + { 20, 22, 23, 26, 29, 32} // x8 (page size = 1K) + //{ xx, xx, xx, xx, TBD, TBD}, // x16(page size = 2K) + }; + + uint8_t speed_idx; + uint8_t width_idx; + + if (p_i_data->dram_width[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4) + { + width_idx = 0; + } + else //(p_i_data->dram_width[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W8) + { + width_idx = 1; + } + //else (p_i_data->dram_width == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16) + + + if (p_i_mss_eff_config_data->mss_freq < 1733) // 1600 + { + speed_idx = 0; // 1.25ns + } + else if (p_i_mss_eff_config_data->mss_freq < 2000) // 1866 + { + speed_idx = 1; // 1.0718ns + } + else if (p_i_mss_eff_config_data->mss_freq < 2267) // 2133 + { + speed_idx = 2; // 0.9376ns + } + else // if (p_i_mss_eff_config_data->mss_freq < 2533) // 2400 + { + speed_idx = 3; // 0.8333ns + } + // else if (p_i_mss_eff_config_data->mss_freq < 2933) // 2666 + // { + // speed_idx = 4; // 0.7502ns + // } + // else // if (p_i_mss_eff_config_data->mss_freq < ????) // 3200 + // { + // speed_idx = 5; // 0.625ns + // } + + if (p_o_atts->eff_dram_tfaw_u32 < min_clks[width_idx][speed_idx]) + { + p_o_atts->eff_dram_tfaw_u32 = min_clks[width_idx][speed_idx]; + } +/* + fapi::Target l_target_centaur; + rc = fapiGetParentChip(i_target_mba, l_target_centaur); + if(rc) break; + uint8_t ec_tfaw_16_problem; + // need ATTRIBUTE for this.... + rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &i_target_centaur, ec_tfaw_16_problem); + if(rc) break; +*/ + if (p_o_atts->eff_dram_tfaw_u32 == 16) // due to logic bug above + { + p_o_atts->eff_dram_tfaw_u32 = 15; + FAPI_INF("setting tFAW to 15 due to bug"); + } + FAPI_DBG("Attribute p_o_eff_dram_tfaw = %i", p_o_atts->eff_dram_tfaw_u32); + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } //------------------------------------------------------------------------------ } // inner for loop } // outter for loop // Calculate CWL - if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 2500) - { - p_o_atts->eff_dram_cwl = 5; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1875) - { - p_o_atts->eff_dram_cwl = 6; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1500) - { - p_o_atts->eff_dram_cwl = 7; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1250) - { - p_o_atts->eff_dram_cwl = 8; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1070) - { - p_o_atts->eff_dram_cwl = 9; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 935) - { - p_o_atts->eff_dram_cwl = 10; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 833) - { - p_o_atts->eff_dram_cwl = 11; - } - else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 750) - { - p_o_atts->eff_dram_cwl = 12; - } - else - { - const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq); - FAPI_ERR("Error calculating CWL"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR); - return rc; + if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { + if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 2500) + { + p_o_atts->eff_dram_cwl = 5; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1875) + { + p_o_atts->eff_dram_cwl = 6; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1500) + { + p_o_atts->eff_dram_cwl = 7; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1250) + { + p_o_atts->eff_dram_cwl = 8; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1070) + { + p_o_atts->eff_dram_cwl = 9; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 935) + { + p_o_atts->eff_dram_cwl = 10; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 833) + { + p_o_atts->eff_dram_cwl = 11; + } + else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 750) + { + p_o_atts->eff_dram_cwl = 12; + } + else + { + const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq); + FAPI_ERR("Error calculating CWL"); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR); + return rc; + } + } else if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + // 1st set only + // need to look at this again... + if (p_i_mss_eff_config_data->mss_freq <= (1600 * 1.05)) // 1600 + { + p_o_atts->eff_dram_cwl = 9; + } + else if (p_i_mss_eff_config_data->mss_freq <= (1866 * 1.05)) // 1866 + { + p_o_atts->eff_dram_cwl = 10; + } + else if (p_i_mss_eff_config_data->mss_freq <= (2133 * 1.05)) // 2133 + { + p_o_atts->eff_dram_cwl = 11; + } + else if (p_i_mss_eff_config_data->mss_freq <= (2400 * 1.05)) // 2400 + { + p_o_atts->eff_dram_cwl = 12; + } + else if (p_i_mss_eff_config_data->mss_freq <= (2666 * 1.05)) // 2666 + { + p_o_atts->eff_dram_cwl = 14; + } + else if (p_i_mss_eff_config_data->mss_freq <= (3200 * 1.05)) // 2666 + { + p_o_atts->eff_dram_cwl = 16; + } + else + { + const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq); + FAPI_ERR("Error calculating CWL"); + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR); + return rc; + } + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; } //------------------------------------------------------------------------------ // Calculate ZQCAL Interval based on the following equation from Ken: @@ -1849,8 +2375,23 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts( FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_UDIMM_UNSUPPORTED_TYPE); return rc; } } else if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { - FAPI_INF("Will set LR atts after orig eff_config functions"); - + if (p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { + FAPI_INF("Will set LR atts after orig eff_config functions"); + } else if (p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) { // need to update this later... + if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4) { + p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C; + } else { + FAPI_INF("Will set LR atts after orig eff_config functions"); + } + } else { + FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString()); + uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0]; + uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1]; + uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0]; + uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1]; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN); + return rc; + } } else { p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED; FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString()); @@ -2057,6 +2598,12 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, p_i_atts->eff_dimm_ranks_configed); if(rc) break; + rc = FAPI_ATTR_SET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba, + p_i_atts->eff_lrdimm_additional_cntl_words); + if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba, + p_i_atts->eff_lrdimm_additional_cntl_words); + if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, p_i_atts->eff_dimm_rcd_cntl_word_0_15); if(rc) break; @@ -2153,12 +2700,31 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD, &i_target_mba, p_i_atts->eff_dram_trrd); if(rc) break; + // DDR4 only + // AST HERE: Need ATTR added + //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD_L, &i_target_mba, + // p_i_atts->eff_dram_trrd); + //if(rc) break; + // DDR4 only + rc = FAPI_ATTR_SET(ATTR_TCCD_L, &i_target_mba, + p_i_atts->eff_dram_tccdl); + if(rc) break; + + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TCCD_L, &i_target_mba, + p_i_atts->eff_dram_tccdl); + if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRTP, &i_target_mba, p_i_atts->eff_dram_trtp); if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTR, &i_target_mba, p_i_atts->eff_dram_twtr); if(rc) break; + // DDR4 only + // AST HERE: Need ATTR added + //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTRL, &i_target_mba, + //p_i_atts->eff_dram_twtrl); + //if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, p_i_atts->eff_dram_width); if(rc) break; @@ -2182,9 +2748,9 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( if(rc) break; // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0, removed for GA1 - //rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DIES_PER_PACKAGE, &i_target_mba, - // p_i_atts->eff_num_dies_per_package); - //if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DIES_PER_PACKAGE, &i_target_mba, + p_i_atts->eff_num_dies_per_package); + if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, p_i_atts->eff_num_drops_per_port); @@ -2194,9 +2760,9 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( if(rc) break; // AST HERE: Needs source data, currently hard coded to 0, removed for GA1 - //rc = FAPI_ATTR_SET(ATTR_EFF_NUM_PACKAGES_PER_RANK, &i_target_mba, - // p_i_atts->eff_num_packages_per_rank); - //if(rc) break; + rc = FAPI_ATTR_SET(ATTR_EFF_NUM_PACKAGES_PER_RANK, &i_target_mba, + p_i_atts->eff_num_packages_per_rank); + if(rc) break; rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, p_i_atts->eff_num_ranks_per_dimm); @@ -2305,16 +2871,6 @@ fapi::ReturnCode mss_eff_config_write_eff_atts( //------------------------------------------------------------------------------ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { -#ifdef FAPI_DDR4 - fapi::ReturnCode rc; - rc = mss_eff_config_ddr4(i_target_mba); - if(rc) - { - FAPI_ERR("Error from mss_eff_config_ddr4()"); - return rc; - } -#endif -#ifndef FAPI_DDR4 /* Initialize Variables */ const fapi::Target& TARGET_MBA = i_target_mba; fapi::ReturnCode rc; @@ -2492,7 +3048,7 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) delete p_l_mss_eff_config_data; delete p_l_spd_data; delete p_l_atts; -#endif + return rc; } // end mss_eff_config() } // extern "C" diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C index e49f80968..fa71f0490 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_eff_config_termination.C,v 1.48 2014/10/01 22:32:38 asaetow Exp $ +// $Id: mss_eff_config_termination.C,v 1.51 2015/09/04 18:16:24 thi Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,13 +44,15 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.50 | sglancy |28-Aug-15| Added RC checks - addressed FW comments +// 1.49 | kmack |05-Aug-15| Commented out FAPI_DDR4 code // 1.48 | asaetow |01-OCT-14| Added setting for single-drop 4G1Rx8 and 16G2Rx4 from Ken/Anil for habanero at 1333Mbps under "rdimm_habanero_1333_r10_mba0", "rdimm_habanero_1333_r10_mba1", "rdimm_habanero_1333_r20_mba0", and "rdimm_habanero_1333_r20_mba1". // | | | Added place holder setting for dual-drop 4G1Rx8 and 16G2Rx4 for habanero at 1333Mbps under "rdimm_habanero_1333_r11_mba0", "rdimm_habanero_1333_r11_mba1", "rdimm_habanero_1333_r22_mba0", and "rdimm_habanero_1333_r22_mba1". // 1.47 | dcadiga |07-APR-14| FFDC Updates // 1.46 | kcook |14-MAR-14| Fixed create_db_ddr4 stub function definition // 1.45 | kcook |14-MAR-14| Added DDR4 support // 1.44 | mjjones |07-MAR-14| Only compile if FAPI_MSSLABONLY defined -// 1.43 | dcadiga |04-MAR-14| Added in ISDimm support for KG +// 1.43 | dcadiga |04-MAR-14| Added in ISDimm support for KG // 1.42 | asaetow |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.H v1.2 // 1.41 | dcadiga |13-JAN-14| Removed checking of dimm type attribute for CDIMM, replaced with custom dimm type attribute // 1.40 | bellows |02-JAN-14| VPD attribute removal @@ -61,8 +63,8 @@ // 1.35 | bellows |16-SEP-13| Hostboot compile update. // 1.34 | kcook |13-SEP-13| Updated define FAPI_LRDIMM token. // 1.33 | bellows |12-SEP-13| set_vpd_dimm_spare function added before AM keyword shows up -// 1.32 | kcook |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C. -// 1.31 | kcook |16-AUG-13| Added LRDIMM support. +// 1.32 | kcook |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C. +// 1.31 | kcook |16-AUG-13| Added LRDIMM support. // 1.30 | dcadiga |07-AUG-13| Fixed hostboot compile issue // 1.29 | dcadiga |05-AUG-13| KG3 allowed, ifdef removed for lab card uint declaration, added 4R support to 1600, changed 4Rx4 / 4Rx8 RCD Drive Settings // 1.28 | asaetow |05-AUG-13| Added temp workaround for incorrect byte33 SPD data in early lab OLD 16G/32G CDIMMs. @@ -77,7 +79,7 @@ // 1.20 | dcadiga |30-APR-13| Fixed Hostboot Compile Error LN 972 // 1.19 | dcadiga |19-APR-13| Added Cdimm RCB/RCC, changed RDIMM settings for MBA0 so that a 1R card will work and a 4R card will work // 1.18 | dcadiga |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift -// 1.17 | asaetow |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. +// 1.17 | asaetow |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333. // 1.16 | dcadiga |25-MAR-13| Added in 2N Addressing Mode. // 1.15 | dcadiga |14-MAR-13| Fixed simulation issue. // 1.14 | dcadiga |12-MAR-13| Code re-write for new dimms. Confirmed working on all systems @@ -90,11 +92,11 @@ // | | | Fixed (l_attr_is_simulation || 1) to (l_attr_is_simulation != 0) from v1.8 and v1.9. // 1.9 | bellows |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks // 1.8 | bellows |06-DEC-12| Added sim leg for rotator values -// 1.7 | asaetow |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. +// 1.7 | asaetow |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. // 1.6 | asaetow |17-NOV-12| Fixed uint8_t attr_eff_odt_wr for 4R RDIMMs. // 1.5 | asaetow |17-NOV-12| Added PR settings. // | | | Fixed RCD settings for RDIMM. -// 1.4 | asaetow |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. +// 1.4 | asaetow |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. // 1.3 | asaetow |05-NOV-12| Added Paul's SI value for pre-machine parsable workbook. // | | | NOTE: DO NOT pick-up without memory_attributes.xml v1.45 or newer. // 1.2 | asaetow |05-SEP-12| Added ATTR_MSS_CAL_STEP_ENABLE. @@ -128,16 +130,16 @@ fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba, uint32_t *var_array_p_array[5]) { ReturnCode rc; - + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_REWRITE_INVALID_EXEC); return rc; } -ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) +ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) { ReturnCode rc; - + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString()); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_TERM_INVALID_EXEC); @@ -146,38 +148,6 @@ ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba) } #endif -#ifndef FAPI_DDR4 -fapi::ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) -{ - ReturnCode rc; - - FAPI_ERR("Invalid exec of mss_create_rcd_ddr4 on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_RCD_DDR4_INVALID_EXEC); - return rc; - -} -fapi::ReturnCode mss_create_db_ddr4(const Target& i_target_mba) -{ - ReturnCode rc; - - - FAPI_ERR("Invalid exec of mss_create_db_ddr4 on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_CREATE_DB_DDR4_INVALID_EXEC); - return rc; - -} -fapi::ReturnCode mss_lrdimm_ddr4_term_atts(const Target& i_target_mba) -{ - ReturnCode rc; - - - FAPI_ERR("Invalid exec of mss_lrdimm_ddr4_term_atts on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_TERM_ATTS_INVALID_EXEC); - return rc; - -} -#endif - //---------------------------------------------------------------------- // ENUMs and CONSTs //---------------------------------------------------------------------- @@ -277,7 +247,7 @@ uint8_t attr_vpd_cen_phase_rot_m1_cntl_odt1[PORT_SIZE]; //Declare the different dimms here: //Cdimm rc_A -uint32_t cdimm_default[STORE_ARRAY_SIZE] = +uint32_t cdimm_default[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; @@ -285,7 +255,7 @@ uint32_t cdimm_rca_1r_1333_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = +uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; @@ -308,100 +278,100 @@ uint32_t cdimm_rcb4_2r_1600_mba1[210] = /* //RDIMM A/B Ports MBA0 Glacier -uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; //RDIMM C/D Ports MBA1 Glacier -uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; -uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = +uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; //UDIMM TEMP FOR JAKE ICICLE -uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = +uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = +uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF }; -//KG3 +//KG3 uint32_t rdimm_kg3_1333_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON }; @@ -456,99 +426,99 @@ uint32_t rdimm_kg3_1600_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RC //RDIMM A/B Ports MBA0 Glacier -uint32_t rdimm_glacier_1600_r10_mba0[210] = +uint32_t rdimm_glacier_1600_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20e_mba0[210] = +uint32_t rdimm_glacier_1333_r20e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20e_mba0[210] = +uint32_t rdimm_glacier_1600_r20e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20b_mba0[210] = +uint32_t rdimm_glacier_1333_r20b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20b_mba0[210] = +uint32_t rdimm_glacier_1600_r20b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r40_mba0[210] = +uint32_t rdimm_glacier_1333_r40_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; //RDIMM C/D Ports MBA1 Glacier -uint32_t rdimm_glacier_1333_r10_mba1[210] = +uint32_t rdimm_glacier_1333_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r10_mba1[210] = +uint32_t rdimm_glacier_1600_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20e_mba1[210] = +uint32_t rdimm_glacier_1333_r20e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20e_mba1[210] = +uint32_t rdimm_glacier_1600_r20e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r20b_mba1[210] = +uint32_t rdimm_glacier_1333_r20b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r20b_mba1[210] = +uint32_t rdimm_glacier_1600_r20b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1066_r40_mba1[210] = +uint32_t rdimm_glacier_1066_r40_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r11_mba1[210] = +uint32_t rdimm_glacier_1333_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r11_mba1[210] = +uint32_t rdimm_glacier_1600_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r22e_mba1[210] = +uint32_t rdimm_glacier_1333_r22e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r22e_mba1[210] = +uint32_t rdimm_glacier_1600_r22e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1333_r22b_mba1[210] = +uint32_t rdimm_glacier_1333_r22b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1600_r22b_mba1[210] = +uint32_t rdimm_glacier_1600_r22b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t rdimm_glacier_1066_r44_mba1[210] = +uint32_t rdimm_glacier_1066_r44_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; //UDIMM TEMP FOR JAKE ICICLE -uint32_t udimm_glacier_1600_r10_mba0[210] = +uint32_t udimm_glacier_1600_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -uint32_t udimm_glacier_1600_r10_mba1[210] = +uint32_t udimm_glacier_1600_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; -//KG3 +//KG3 uint32_t rdimm_kg3_1333_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE }; @@ -636,7 +606,7 @@ uint32_t rdimm_habanero_1333_r20_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_I uint32_t rdimm_habanero_1333_r20_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; // habanero_1333 dual-drop -uint32_t rdimm_habanero_1333_r11_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; +uint32_t rdimm_habanero_1333_r11_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; uint32_t rdimm_habanero_1333_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE}; @@ -669,7 +639,7 @@ extern "C" { uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; uint8_t l_stack_type_u8array[PORT_SIZE][DIMM_SIZE]; uint8_t l_dimm_size_u8array[PORT_SIZE][DIMM_SIZE]; - // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, + // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, uint8_t l_dram_gen_u8; // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, uint8_t l_dimm_type_u8; @@ -728,7 +698,7 @@ extern "C" { if ((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (l_stack_type_u8array[cur_port][cur_dimm] == fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP) && (l_dram_width_u8 == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (l_dimm_size_u8array[cur_port][cur_dimm] == 4)) { FAPI_INF("WARNING: Wrong Byte33 SPD detected for OLD 16G/32G CDIMM on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm); FAPI_INF("WARNING: Implimenting workaround on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm); - l_stack_type_modified = 1; + l_stack_type_modified = 1; l_stack_type_u8array[cur_port][cur_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE; } } @@ -765,12 +735,12 @@ extern "C" { } else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t)); } else{ FAPI_ERR("Invalid Dimm SIM This Should Never Happen!\n"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DIMM_USE_ERROR); return rc; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DIMM_USE_ERROR); return rc; } @@ -784,7 +754,7 @@ extern "C" { //FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; if( l_target_mba_pos == 0){ if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333! memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -808,15 +778,15 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps); return rc; + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 - memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); + memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); } else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){ @@ -841,18 +811,18 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps); return rc; + } - }//1600 + }//1600 }//MBA0 else{ if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4, memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0) && (l_dram_width_u8 == 4)){ memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,210*sizeof(uint32_t)); FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -872,13 +842,13 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps_MBA1); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps_MBA1); return rc; + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { + if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { //Removed Width Check, use settings for either x8 or x4 memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t)); FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); @@ -905,10 +875,10 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps_MBA1); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps_MBA1); return rc; + } - }//1600 + }//1600 }//MBA1 } #endif @@ -944,8 +914,8 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1333Mbps); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1333Mbps); return rc; } // memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t)); // FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n"); @@ -980,15 +950,15 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1600Mbps); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1600Mbps); return rc; } }//1600 }//MBA1 } - else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ + else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) { //This is a CDIMM! @@ -1013,8 +983,8 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_B4_1600Mbps); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_B4_1600Mbps); return rc; } } }//CDIMM RCB4 @@ -1033,15 +1003,15 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; } } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc; } } else{ @@ -1052,15 +1022,15 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; } } else{ FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc; } } @@ -1093,8 +1063,8 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1333Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1333Mbps); return rc; + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps @@ -1121,52 +1091,52 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1600Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1600Mbps); return rc; + } - }//1600 + }//1600 }//MBA0 else{ if ( l_mss_freq <= 1200 ) { // 1066Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1066Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1066Mbps); return rc; + } } else if ( l_mss_freq <= 1466 ) { // 1333Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t)); + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 settings for CD only! memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); @@ -1176,36 +1146,36 @@ extern "C" { else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1333Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1333Mbps); return rc; + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps - if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ - memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); + if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ + memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ - memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){ + memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){ memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,210*sizeof(uint32_t)); - FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ - memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); + FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){ + memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } - else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ - memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t)); + } + else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){ + memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t)); FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString()); - } + } else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){ //Use 4R MBA0 1333 settings for CD only! memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t)); @@ -1213,8 +1183,8 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1600Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1600Mbps); return rc; + } }//1600 }//MBA1 @@ -1246,8 +1216,8 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d HERE MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1333Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1333Mbps); return rc; + } } else if ( l_mss_freq <= 1733 ) { // 1600Mbps @@ -1261,8 +1231,8 @@ extern "C" { } else{ FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA1\n",l_mss_freq); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1600Mbps); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1600Mbps); return rc; + } } }//MBA1 @@ -1279,7 +1249,7 @@ extern "C" { uint32_t *p_b_var_array = &base_var_array[0]; - uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array, + uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array, p_1600_x4_mba1_array, p_1600_x8_mba1_array}; rc = mss_lrdimm_rewrite_odt(i_target_mba, p_b_var_array, var_array_p_array); @@ -1287,15 +1257,15 @@ extern "C" { if(rc) { FAPI_ERR("FAILED LRDIMM rewrite ODT_RD"); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_ODT_RD); return rc; + + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_ODT_RD); return rc; } } } // LRDIMM else{ FAPI_ERR("Invalid Dimm Type of %d", l_dimm_type_u8); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_TYPE); return rc; - + } // Now Set All The Attributes @@ -1303,14 +1273,14 @@ extern "C" { attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++]; // keep 0 attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++]; // keep 1 attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++]; // keep 2 - attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; // keep 3 + attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++]; // keep 3 attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++]; // keep 4 attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++]; // keep 5 attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++]; // keep 6 attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++]; // keep 7 - //Fix for VPD Mode for lab rdimm + //Fix for VPD Mode for lab rdimm if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){ FAPI_INF("RON i %d SHOULD NOT BE HERE\n",i); attr_vpd_dram_ron[0][0] = base_var_array[i++]; @@ -1740,11 +1710,17 @@ extern "C" { //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination - if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && - ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || + if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && + ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) { rc = mss_create_rcd_ddr4(i_target_mba); + + if (rc) + { + FAPI_ERR("Setting DDR4 RCD words failed \n"); + return rc; + } if (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { rc = mss_create_db_ddr4(i_target_mba); @@ -1753,8 +1729,7 @@ extern "C" { if (rc) { FAPI_ERR("Setting DDR4 RCD words failed \n"); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DDR4_RCD); return rc; + return rc; } } @@ -1769,7 +1744,7 @@ extern "C" { if(l_dram_width_u8 == 4){ l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005050080210000LL; } - else { + else { l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550080210000LL; } @@ -1780,10 +1755,10 @@ extern "C" { } else { l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0000000000000000LL; } - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; if ( l_mss_freq <= 933 ) { // 800Mbps l_mss_freq_mask = 0x0000000000000000LL; } else if ( l_mss_freq <= 1200 ) { // 1066Mbps @@ -1794,17 +1769,17 @@ extern "C" { l_mss_freq_mask = 0x0000000000300000LL; } else { // 1866Mbps FAPI_ERR("Invalid RDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_FREQ); return rc; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_FREQ); return rc; } if ( l_mss_volt >= 1420 ) { // 1.5V l_mss_volt_mask = 0x0000000000000000LL; } else if ( l_mss_volt >= 1270 ) { // 1.35V l_mss_volt_mask = 0x0000000000010000LL; - } else { // 1.2V + } else { // 1.2V FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_VOLT); return rc; - - } + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_VOLT); return rc; + + } if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) { l_rcd_ibt_mask = 0x0000000070000000LL; } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) { @@ -1817,8 +1792,8 @@ extern "C" { l_rcd_ibt_mask = 0x0000000040000000LL; } else { FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_IBT); return rc; - + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_IBT); return rc; + } if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) { l_rcd_mirror_mode_mask = 0x0000000000000000LL; @@ -1826,47 +1801,47 @@ extern "C" { l_rcd_mirror_mode_mask = 0x0000000080000000LL; } else { FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString()); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_MIRROR_MODE); return rc; - - - } - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; - l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; + FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_MIRROR_MODE); return rc; + + + } + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; + l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; } } } // For DDR4 - uint8_t l_attr_eff_dram_lpasr = ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL; // 0 - uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_DISABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_mpr_page = 0; // 0; maybe add ENUMS: PG0=0, PG1=1, PG2=2, PG3=3 for more readability? - uint8_t l_attr_eff_geardown_mode = ENUM_ATTR_EFF_GEARDOWN_MODE_HALF; // 0 - uint8_t l_attr_eff_per_dram_access = ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 - uint8_t l_attr_eff_temp_readout = ENUM_ATTR_EFF_TEMP_READOUT_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 - uint8_t l_attr_eff_fine_refresh_mode = ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL; // 4; maybe change ENUMS: NORMAL=0; FIXED_2X=1, FIXED_4X=2, FLY_2X=5, FLY_4X=6 to align with spec better - uint8_t l_attr_eff_crc_wr_latency = ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK; // 0; change ENUMS: 4NCK=4, 5NCK=5, 6NCK=6 following convention - uint8_t l_attr_eff_mpr_rd_format = ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL; // 0 - uint8_t l_attr_eff_max_powerdown_mode = ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_temp_ref_range = ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL; // 0 - uint8_t l_attr_eff_temp_ref_mode = ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_int_vref_mon = ENUM_ATTR_EFF_INT_VREF_MON_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_cs_cmd_latency = 0; // 0; maybe add ENUMS: DISABLE=0, 3CYC=3, 4CYC=4, 5CYC=5, 6CYC=6, 8CYC=8 for better readability - uint8_t l_attr_eff_self_ref_abort = ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_rd_preamble_train = ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 - uint8_t l_attr_eff_rd_preamble = ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention - uint8_t l_attr_eff_wr_preamble = ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention - uint8_t l_attr_eff_ca_parity_latency = ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE; // 0; add ENUMS: PL4=4, PL5=5, PL6=6, PL8=8, for better readability - uint8_t l_attr_eff_crc_error_clear = ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec. - uint8_t l_attr_eff_ca_parity_error_status = ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec - uint8_t l_attr_eff_odt_input_buff = ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; // 0; change ENUMS: DEACTIVATED=0, ACTIVATED=1 - uint8_t l_attr_eff_ca_parity = ENUM_ATTR_EFF_CA_PARITY_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 to match spec - uint8_t l_attr_eff_data_mask = ENUM_ATTR_EFF_DATA_MASK_DISABLE; // 0 - uint8_t l_attr_eff_write_dbi = ENUM_ATTR_EFF_WRITE_DBI_DISABLE; // 0 - uint8_t l_attr_eff_read_dbi = ENUM_ATTR_EFF_READ_DBI_DISABLE; // 0 -// uint8_t l_attr_tccd_l = ENUM_ATTR_TCCD_L_5NCK; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability + uint8_t l_attr_eff_dram_lpasr = ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL; // 0 + uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_DISABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_mpr_page = 0; // 0; maybe add ENUMS: PG0=0, PG1=1, PG2=2, PG3=3 for more readability? + uint8_t l_attr_eff_geardown_mode = ENUM_ATTR_EFF_GEARDOWN_MODE_HALF; // 0 + uint8_t l_attr_eff_per_dram_access = ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 + uint8_t l_attr_eff_temp_readout = ENUM_ATTR_EFF_TEMP_READOUT_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1 + uint8_t l_attr_eff_fine_refresh_mode = ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL; // 4; maybe change ENUMS: NORMAL=0; FIXED_2X=1, FIXED_4X=2, FLY_2X=5, FLY_4X=6 to align with spec better + uint8_t l_attr_eff_crc_wr_latency = ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK; // 0; change ENUMS: 4NCK=4, 5NCK=5, 6NCK=6 following convention + uint8_t l_attr_eff_mpr_rd_format = ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL; // 0 + uint8_t l_attr_eff_max_powerdown_mode = ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_temp_ref_range = ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL; // 0 + uint8_t l_attr_eff_temp_ref_mode = ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE; // 0; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_int_vref_mon = ENUM_ATTR_EFF_INT_VREF_MON_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_cs_cmd_latency = 0; // 0; maybe add ENUMS: DISABLE=0, 3CYC=3, 4CYC=4, 5CYC=5, 6CYC=6, 8CYC=8 for better readability + uint8_t l_attr_eff_self_ref_abort = ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_rd_preamble_train = ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE; // 1; change ENUMS: DISABLE=0, ENABLE=1 + uint8_t l_attr_eff_rd_preamble = ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention + uint8_t l_attr_eff_wr_preamble = ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK; // 0; change ENUMS: 1NCK=1, 2NCK=2 following convention + uint8_t l_attr_eff_ca_parity_latency = ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE; // 0; add ENUMS: PL4=4, PL5=5, PL6=6, PL8=8, for better readability + uint8_t l_attr_eff_crc_error_clear = ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec. + uint8_t l_attr_eff_ca_parity_error_status = ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR; // 0; change ENUMS: CLEAR=0, ERROR=1 to match spec + uint8_t l_attr_eff_odt_input_buff = ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; // 0; change ENUMS: DEACTIVATED=0, ACTIVATED=1 + uint8_t l_attr_eff_ca_parity = ENUM_ATTR_EFF_CA_PARITY_DISABLE; // change to disable; change ENUMS: DISABLE=0, ENABLE=1 to match spec + uint8_t l_attr_eff_data_mask = ENUM_ATTR_EFF_DATA_MASK_DISABLE; // 0 + uint8_t l_attr_eff_write_dbi = ENUM_ATTR_EFF_WRITE_DBI_DISABLE; // 0 + uint8_t l_attr_eff_read_dbi = ENUM_ATTR_EFF_READ_DBI_DISABLE; // 0 +// uint8_t l_attr_tccd_l = ENUM_ATTR_TCCD_L_5NCK; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability // uint8_t l_attr_tccd_l = 5; // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability /* @@ -1948,7 +1923,7 @@ extern "C" { attr_eff_wlo[1] = (uint8_t)0; attr_eff_gpo[0] = (uint8_t)5; attr_eff_gpo[1] = (uint8_t)5; -*/ +*/ if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) { // Set for CDIMM B4 attr_eff_rlo[0] = (uint8_t)0; @@ -1978,13 +1953,13 @@ extern "C" { attr_eff_rlo[0] = (uint8_t)5; attr_eff_rlo[1] = (uint8_t)5; attr_eff_wlo[0] = (uint8_t)1; - attr_eff_wlo[1] = (uint8_t)1; - } + attr_eff_wlo[1] = (uint8_t)1; + } else { attr_eff_rlo[0] = (uint8_t)6; attr_eff_rlo[1] = (uint8_t)6; attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement - attr_eff_wlo[1] = (uint8_t)255; + attr_eff_wlo[1] = (uint8_t)255; } attr_eff_gpo[0] = (uint8_t)7; attr_eff_gpo[1] = (uint8_t)7; @@ -1993,9 +1968,9 @@ extern "C" { else{ FAPI_ERR("Invalid Card Type RLO Settings \n"); FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_CARD_TYPE_RLO); return rc; - - } + + } @@ -2037,9 +2012,9 @@ extern "C" { // Set attributes rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - } + } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc; rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc; @@ -2076,7 +2051,7 @@ extern "C" { || (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ){ FAPI_INF("IN RDIMM ATTR SETTING\n"); rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc; - if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD + if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; } rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc; @@ -2236,12 +2211,12 @@ extern "C" { if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) - { + { if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { + { rc = mss_lrdimm_term_atts(i_target_mba); } - else + else { rc = mss_lrdimm_ddr4_term_atts(i_target_mba); } @@ -2249,18 +2224,10 @@ extern "C" { if (rc) { FAPI_ERR("Setting LR term atts failed \n"); - - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_SETTING_LRDIMM_TERM_ATTRS); return rc; + return rc; } } - - - - - - - FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); return rc; @@ -2284,9 +2251,7 @@ extern "C" { if(rc) { FAPI_ERR("Error retrieving assodiated dimms"); - FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_ERROR_RETRIEVING_DIMMS); return rc; - - break; + return rc; } //------------------------------------------------------------------------------ for (uint8_t l_dimm_index = 0; l_dimm_index < diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 80fa1fb8f..b4059a2ea 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -23,7 +23,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.154 2015/08/26 03:14:17 eliner Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.159 2015/09/09 18:10:53 thi Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -99,7 +99,7 @@ Set by: PLL settings written by Dave Cadigan</description> <id>ATTR_MSS_VREF_CAL_CNTL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level; - Default Value = 0x01; + Default Value = 0x01; </description> <valueType>uint8</valueType> <platInit/> @@ -108,7 +108,7 @@ Set by: PLL settings written by Dave Cadigan</description> <odmChangeable/> <persistRuntime/> </attribute> - + <attribute> <id>ATTR_MSS_DIMM_MFG_ID_CODE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -1174,6 +1174,401 @@ firmware notes: none</description> </attribute> <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC00</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output inversion can be disabled. +When disabled, register tPDM is not guaranteed to be met. NOTE: Default value - 0x00. Values Range from 0-8. +00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on. +No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC01</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode. + Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC02</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC03</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC04</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC05</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC06_07</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC06: Command Space Control Word definition; Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC08</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC08: Input/Output Configuration Control Word; Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; 00 = Stack height_8; 01 = Stack height_4; + 02 = Stack height_2; +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC09</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC09: Power Saving Settings Control Word; Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC10</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RDIMM Operating Speed; Read from ATTR_MSS_FREQ; Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC11</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC12</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0C - Training Control Word; Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC13</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0D - DIMM Configuration Control Word; Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC14</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC15</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_1x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_2x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC2x: I2C Bus Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_3x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC3x - Fine Granularity RDIMM Operating Speed; Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_4x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC4x: CW Source Selection Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_5x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_6x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC6x: CW Data Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_7x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_8x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_9x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RCBx: IBT and MRS Snoop Control Word; Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> <id>ATTR_EFF_DIMM_RCD_IBT</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. @@ -2478,7 +2873,7 @@ Firmware shares some code with the processor, so the attribute is named so they <writeable/> <odmVisable/> <odmChangeable/> - <array> 2 2</array> + <array> 2 2</array> </attribute> <attribute> @@ -2906,18 +3301,15 @@ Will be set at an MBA level with one policy to be used</description> <odmVisable/> </attribute> -<!-- TODO Thi <attribute> <id>ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Option to control MCS prefetch retry threshold, for performance optimization. This attribute controls the number of retries in the prefetch engine. Retry threshold available ranges from 16 to 30. Note: Values outside those ranges will default to 30. In MRW.</description> <valueType>uint8</valueType> <platInit/> - <writeable/> <odmVisable/> <odmChangeable/> </attribute> ---> <attribute> <id>ATTR_MRW_POWER_CONTROL_REQUESTED</id> diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index bd2f53d36..22467eaf3 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -8410,7 +8410,7 @@ firmware notes: Used as override attribute for pstate procedure <attribute> <id>MSS_POWER_INT2</id> - <description>DIMM Power intercept value. Initialized and used by HWPs.</description> + <description>Supplier Power intercept value for dimm</description> <simpleType> <uint32_t> </uint32_t> @@ -8426,6 +8426,74 @@ firmware notes: Used as override attribute for pstate procedure </attribute> <attribute> + <id>MSS_TOTAL_POWER_SLOPE</id> + <description>Master Total Power slope value for dimm</description> + <simpleType> + <uint32_t> + </uint32_t> + <array>2,2</array><!-- [drop][port] --> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_TOTAL_POWER_SLOPE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_TOTAL_POWER_SLOPE2</id> + <description>Supplier Total Power slope value for dimm</description> + <simpleType> + <uint32_t> + </uint32_t> + <array>2,2</array><!-- [drop][port] --> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_TOTAL_POWER_SLOPE2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_TOTAL_POWER_INT</id> + <description>Master Total Power intercept value for dimm</description> + <simpleType> + <uint32_t> + </uint32_t> + <array>2,2</array><!-- [drop][port] --> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_TOTAL_POWER_INT</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>MSS_TOTAL_POWER_INT2</id> + <description>Supplier Total Power intercept value for dimm</description> + <simpleType> + <uint32_t> + </uint32_t> + <array>2,2</array><!-- [drop][port] --> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_MSS_TOTAL_POWER_INT2</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> <id>MSS_DIMM_MAXBANDWIDTH_GBS</id> <description>DIMM Max Bandwidth in GBs. Initialized and used by HWPs.</description> <simpleType> @@ -15799,16 +15867,17 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>MSS_VREF_CAL_CNTL</id> - <description> - Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; - 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; - 0x03=PORT Level Training; 0x0 4=MBA Level; 0x05=CENTAUR level; - Default Value = 0x01; + <description>Training Control over IPL + - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; + 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level; + Default Value = 0x01; </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>0x01</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>volatile</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> @@ -15819,17 +15888,15 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>EFF_DIMM_RCD_CNTL_WORD_X</id> - <description> - Additional RCD Control Word for DDR4. Used in mss_dram_init and is computed - in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or - odm_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none + <description>Additional RCD Control Word for DDR4. Used in mss_dram_init and is computed in mss_eff_cnfg. + Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none </description> <simpleType> <uint64_t></uint64_t> - <array>2, 2</array> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> @@ -15841,76 +15908,615 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </attribute> <attribute> - <id>MSS_TOTAL_POWER_SLOPE</id> - <description>Master Total Power slope value for dimm</description> + <id>EFF_DIMM_DDR4_RC00</id> + <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output + inversion can be disabled. When disabled, register tPDM is not guaranteed to be met. + NOTE: Default value - 0x00. Values Range from 0-8. + 00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on. + No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> <simpleType> - <uint32_t></uint32_t> - <array>2, 2</array> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_SLOPE</id> + <id>ATTR_EFF_DIMM_DDR4_RC00</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_TOTAL_POWER_SLOPE2</id> - <description>Supplier Total Power slope value for dimm</description> + <id>EFF_DIMM_DDR4_RC01</id> + <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. + The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked + on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode. + Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> <simpleType> - <uint32_t></uint32_t> - <array>2, 2</array> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_SLOPE2</id> + <id>ATTR_EFF_DIMM_DDR4_RC01</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_TOTAL_POWER_INT</id> - <description>Master total power intercept value for dimm</description> + <id>EFF_DIMM_DDR4_RC02</id> + <description>F0RC02: Timing and IBT Control Word; + Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> <simpleType> - <uint32_t></uint32_t> - <array>2, 2</array> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_INT</id> + <id>ATTR_EFF_DIMM_DDR4_RC02</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_TOTAL_POWER_INT2</id> - <description>Supplier total power intercept value for dimm</description> + <id>EFF_DIMM_DDR4_RC03</id> + <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> <simpleType> - <uint32_t></uint32_t> - <array>2, 2</array> + <uint8_t> + <default>5</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC03</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC04</id> + <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>5</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC04</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC05</id> + <description>F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>5</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC05</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC06_07</id> + <description>F0RC06: Command Space Control Word definition; + Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0xF0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC06_07</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC08</id> + <description>F0RC08: Command Space Control Word definition; + Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; + 00 = Stack height_8; 01 = Stack height_4; 02 = Stack height_2; + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0x03</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC08</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC09</id> + <description>F0RC09: Command Space Control Word definition; + Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0xF0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC09</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC10</id> + <description>RDIMM Operating Speed; Read from ATTR_MSS_FREQ; + Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_INT2</id> + <id>ATTR_EFF_DIMM_DDR4_RC10</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC11</id> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT. + Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>14</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC11</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC12</id> + <description>F0RC0C - Training Control Word; + Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC12</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC13</id> + <description>F0RC0D - DIMM Configuration Control Word; + Default value - 0x0B. Values Range from 00 to 15 decimal. + Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0x0B</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC13</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC14</id> + <description>F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC14</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC15</id> + <description>F0RC0F - Command Latency Adder Control Word; + Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0x04</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC15</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + + +<attribute> + <id>EFF_DIMM_DDR4_RC_1x</id> + <description>F0RC1x - Internal VrefCA Control Word; + Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_1x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_2x</id> + <description>F0RC2x: I2C Bus Control Word; + Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_2x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_3x</id> + <description>F0RC3x - Fine Granularity RDIMM Operating Speed; + Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_3x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_4x</id> + <description>F0RC4x: CW Source Selection Control Word; + Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_4x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_5x</id> + <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; + Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_5x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_6x</id> + <description>F0RC6x: CW Data Control Word; + Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_6x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_7x</id> + <description>F0RC7x: IBT Control Word; + Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_7x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_8x</id> + <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; + Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_8x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_9x</id> + <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; + Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_9x</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_Ax</id> + <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; + Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> + +<attribute> + <id>EFF_DIMM_DDR4_RC_Bx</id> + <description>F0RCBx: IBT and MRS Snoop Control Word; Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + </description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + <array>2,2</array> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> <id>EFF_DRAM_TCCD_L</id> - <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. - Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none + <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none </description> <simpleType> <uint8_t></uint8_t> @@ -15926,12 +16532,10 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>EFF_LRDIMM_WORD_X</id> - <description> - Additional buffer control word for LRDIMM building of the BCW - </description> + <description>Additional buffer control word for LRDIMM building of the BCW</description> <simpleType> <uint64_t></uint64_t> - <array>2, 2</array> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> @@ -15944,16 +16548,15 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <description> - LRDIMM additional RCD control words as set by DIMM SPD: - F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, - F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,F[1]RC8, F[3]RC9, F[3]RC8, - F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. - Eff config should set this up + <description>LRDIMM additional RCD control words as set by DIMM SPD: + F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, + F[7,8]RC11, F[9,10]RC10, F[9,10]RC11, F[1]RC8, F[3]RC9, + F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. + Eff config should set this up. </description> <simpleType> <uint64_t></uint64_t> - <array>2, 2</array> + <array>2,2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> @@ -15966,10 +16569,7 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript <attribute> <id>MCBIST_DDR4_PDA_ENABLE</id> - <description> - Controls PDA train enable or PBA. 00 - Disable; - 01 - PDA; 02 - PBA(Lrdimm) - </description> + <description>Controls PDA train enable or PBA. 00 - Disable; 01 - PDA; 02 - PBA(Lrdimm)</description> <simpleType> <uint8_t></uint8_t> </simpleType> @@ -15982,6 +16582,23 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript </hwpfToHbAttrMap> </attribute> -</attributes> - +<attribute> + <id>MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> + <description> + Option to control MCS prefetch retry threshold, for performance + optimization. This attribute controls the number of retries in the + prefetch engine. Retry threshold available ranges from 16 to 30. Note: + Values outside those ranges will default to 30. In MRW. + </description> + <simpleType> + <uint8_t></uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> +</attribute> +</attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index 1884c63ad..0b45bb055 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -308,6 +308,7 @@ <attribute><id>SBE_MASTER_INTR_SERVICE_DELAY_CYCLES</id></attribute> <attribute><id>SBE_MASTER_INTR_SERVICE_DELAY_US</id></attribute> <attribute><id>CLEAR_DIMM_SPD_ENABLE</id></attribute> + <attribute><id>MRW_MCS_PREFETCH_RETRY_THRESHOLD</id></attribute> </targetType> <targetType> @@ -1181,6 +1182,10 @@ <attribute><id>MSS_POWER_SLOPE2</id></attribute> <attribute><id>MSS_POWER_INT</id></attribute> <attribute><id>MSS_POWER_INT2</id></attribute> + <attribute><id>MSS_TOTAL_POWER_SLOPE</id></attribute> + <attribute><id>MSS_TOTAL_POWER_SLOPE2</id></attribute> + <attribute><id>MSS_TOTAL_POWER_INT</id></attribute> + <attribute><id>MSS_TOTAL_POWER_INT2</id></attribute> <attribute><id>MSS_DIMM_MAXBANDWIDTH_GBS</id></attribute> <attribute><id>MSS_DIMM_MAXBANDWIDTH_MRS</id></attribute> <attribute><id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id></attribute> @@ -1330,10 +1335,32 @@ <attribute><id>MSS_EFF_VPD_VERSION</id></attribute> <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> <attribute><id>EFF_DIMM_RCD_CNTL_WORD_X</id></attribute> - <attribute><id>MSS_TOTAL_POWER_SLOPE</id></attribute> - <attribute><id>MSS_TOTAL_POWER_SLOPE2</id></attribute> - <attribute><id>MSS_TOTAL_POWER_INT</id></attribute> - <attribute><id>MSS_TOTAL_POWER_INT2</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC00</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC01</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC02</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC03</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC04</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC05</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC06_07</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC08</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC09</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC10</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC11</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC12</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC13</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC14</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC15</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_1x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_2x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_3x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_4x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_5x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_6x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_7x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_8x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_9x</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_Ax</id></attribute> + <attribute><id>EFF_DIMM_DDR4_RC_Bx</id></attribute> <attribute><id>EFF_DRAM_TCCD_L</id></attribute> <attribute><id>EFF_LRDIMM_WORD_X</id></attribute> <attribute><id>EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id></attribute> @@ -1517,7 +1544,9 @@ </attribute> <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> <attribute><id>FRU_ID</id></attribute> + <attribute><id>MSS_VREF_CAL_CNTL</id></attribute> + </targetType> <!-- Centaur L4 --> |
