PM: Change FFDC for SGPE and PGPE based on failure error log debug

- Switched the following:
    PU_GPEx_GPEXIXSR_SCOM  -> PU_GPEx_PPE_XIDBGPRO
    PU_GPEx_GPEXIIAR_SCOM  -> PU_GPEx_PPE_XIRAMDBG
    PU_GPEx_GPEXIIR_SCOMM  -> PU_GPEx_PPE_XIRAMEDR
- Added PBA_FFDC_BASIC register definition and added to respective TIMEOUT
  errors

Change-Id: I13de9bfdcccbef45a3a527ea9d623c26bf99e064
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45414
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45429
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 60 insertions, 14 deletions

diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml
index 4afc2d06a..3201fe251 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml
@@ -52,12 +52,19 @@
     <ffdc>CHIP</ffdc>
     <ffdc>PGPE_BASE_ADDRESS</ffdc>
     <ffdc>PGPE_STATE_MODE</ffdc>
+
     <collectRegisterFfdc>
       <id>PGPE_FFDC_REGISTERS</id>
       <target>CHIP</target>
       <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     </collectRegisterFfdc>
 
+    <collectRegisterFfdc>
+      <id>PBA_FFDC_BASIC_REGISTERS</id>
+      <target>CHIP</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    </collectRegisterFfdc>
+
      <collectFfdc>p9_collect_ppe_state, CHIP, PGPE_STATE_MODE, PGPE_BASE_ADDRESS</collectFfdc>
     <callout>
       <target>CHIP</target>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
index f6df0e6d1..022f44d1d 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_registers.xml
@@ -71,9 +71,9 @@
   <registerFfdc>
     <id>SGPE_FFDC_REGISTERS</id>
     <scomRegister>PU_OCB_OCI_OCCFLG_SCOM</scomRegister>
-    <scomRegister>PU_GPE3_GPEXIXSR_SCOM</scomRegister>
-    <scomRegister>PU_GPE3_GPEXIIAR_SCOM</scomRegister>
-    <scomRegister>PU_GPE3_GPEXIIR_SCOM</scomRegister>
+    <scomRegister>PU_GPE3_PPE_XIDBGPRO</scomRegister>
+    <scomRegister>PU_GPE3_PPE_XIRAMDBG</scomRegister>
+    <scomRegister>PU_GPE3_PPE_XIRAMEDR</scomRegister>
     <scomRegister>PU_GPE3_GPETSEL_SCOM</scomRegister>
     <scomRegister>PU_GPE3_GPEIVPR_SCOM</scomRegister>
     <scomRegister>PU_GPE3_GPESTR_SCOM</scomRegister>
@@ -85,9 +85,9 @@
   <!-- ******************************************************************** -->
   <registerFfdc>
     <id>OCCGPE0_FFDC_REGISTERS</id>
-    <scomRegister>PU_GPE0_GPEXIXSR_SCOM</scomRegister>
-    <scomRegister>PU_GPE0_GPEXIIAR_SCOM</scomRegister>
-    <scomRegister>PU_GPE0_GPEXIIR_SCOM</scomRegister>
+    <scomRegister>PU_GPE0_PPE_XIDBGPRO</scomRegister>
+    <scomRegister>PU_GPE0_PPE_XIRAMDBG</scomRegister>
+    <scomRegister>PU_GPE0_PPE_XIRAMEDR</scomRegister>
     <scomRegister>PU_GPE0_GPETSEL_SCOM</scomRegister>
     <scomRegister>PU_GPE0_GPEIVPR_SCOM</scomRegister>
     <scomRegister>PU_GPE0_GPESTR_SCOM</scomRegister>
@@ -99,9 +99,9 @@
   <!-- ******************************************************************** -->
   <registerFfdc>
     <id>OCCGPE1_FFDC_REGISTERS</id>
-    <scomRegister>PU_GPE1_GPEXIXSR_SCOM</scomRegister>
-    <scomRegister>PU_GPE1_GPEXIIAR_SCOM</scomRegister>
-    <scomRegister>PU_GPE1_GPEXIIR_SCOM</scomRegister>
+    <scomRegister>PU_GPE1_PPE_XIDBGPRO</scomRegister>
+    <scomRegister>PU_GPE1_PPE_XIRAMDBG</scomRegister>
+    <scomRegister>PU_GPE1_PPE_XIRAMEDR</scomRegister>
     <scomRegister>PU_GPE1_GPETSEL_SCOM</scomRegister>
     <scomRegister>PU_GPE1_GPEIVPR_SCOM</scomRegister>
     <scomRegister>PU_GPE1_GPESTR_SCOM</scomRegister>
@@ -114,9 +114,42 @@
   <registerFfdc>
     <id>PGPE_FFDC_REGISTERS</id>
     <scomRegister>PU_OCB_OCI_OCCS2_SCOM</scomRegister>
-    <scomRegister>PU_GPE2_GPEXIXSR_SCOM</scomRegister>
-    <scomRegister>PU_GPE2_GPEXIIAR_SCOM</scomRegister>
-    <scomRegister>PU_GPE2_GPEXIIR_SCOM</scomRegister>
+    <scomRegister>PU_GPE2_PPE_XIDBGPRO</scomRegister>
+    <scomRegister>PU_GPE2_PPE_XIRAMDBG</scomRegister>
+    <scomRegister>PU_GPE2_PPE_XIRAMEDR</scomRegister>
+    <scomRegister>PU_GPE2_GPETSEL_SCOM</scomRegister>
+    <scomRegister>PU_GPE2_GPEIVPR_SCOM</scomRegister>
+    <scomRegister>PU_GPE2_GPESTR_SCOM</scomRegister>
+    <scomRegister>PU_GPE2_GPEMACR_SCOM</scomRegister>
+    <scomRegister>PU_GPE2_MIB_XISGB</scomRegister>
+    <scomRegister>PU_GPE2_MIB_XIICAC</scomRegister>
+    <scomRegister>PU_GPE2_MIB_XIDCAC_SCOM</scomRegister>
+  </registerFfdc>
+  <!-- ******************************************************************** -->
+  <registerFfdc>
+    <id>PBA_FFDC_BASIC_REGISTERS</id>
+    <scomRegister>PU_PBASLVCTL0_SCOM</scomRegister>
+    <scomRegister>PU_PBASLVCTL1_SCOM</scomRegister>
+    <scomRegister>PU_PBASLVCTL2_SCOM</scomRegister>
+    <scomRegister>PU_PBASLVCTL3_SCOM</scomRegister>
+    <scomRegister>PU_PBASLVRST_SCOM</scomRegister>
+    <scomRegister>PU_PBAMODE_SCOM</scomRegister>
+    <scomRegister>PU_PBAFIR</scomRegister>
+    <scomRegister>PU_PBAFIRACT0</scomRegister>
+    <scomRegister>PU_PBAFIRACT1</scomRegister>
+    <scomRegister>PU_PBAFIRMASK</scomRegister>
+    <scomRegister>PU_PBACFG</scomRegister>
+    <scomRegister>PU_PBAERRRPT0</scomRegister>
+    <scomRegister>PU_PBAERRRPT1</scomRegister>
+    <scomRegister>PU_PBAERRRPT2</scomRegister>
+    <scomRegister>PU_PBABAR0</scomRegister>
+    <scomRegister>PU_PBABAR1</scomRegister>
+    <scomRegister>PU_PBABAR2</scomRegister>
+    <scomRegister>PU_PBABAR3</scomRegister>
+    <scomRegister>PU_PBABARMSK0</scomRegister>
+    <scomRegister>PU_PBABARMSK1</scomRegister>
+    <scomRegister>PU_PBABARMSK2</scomRegister>
+    <scomRegister>PU_PBABARMSK3</scomRegister>
   </registerFfdc>
   <!-- ******************************************************************** -->
   <registerFfdc>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
index 278e5b56a..755e28312 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_stop_gpe_init_errors.xml
@@ -80,13 +80,19 @@
     <ffdc>XSR_REG_VAL</ffdc>
 
     <collectFfdc>p9_collect_ppe_state, CHIP, PPE_STATE_MODE, PPE_BASE_ADDRESS_LIST</collectFfdc>
-  
+
     <collectRegisterFfdc>
       <id>SGPE_FFDC_REGISTERS</id>
       <target>CHIP</target>
       <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     </collectRegisterFfdc>
 
+    <collectRegisterFfdc>
+      <id>PBA_FFDC_BASIC_REGISTERS</id>
+      <target>CHIP</target>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    </collectRegisterFfdc>
+
     <callout>
       <procedure>CODE</procedure>
       <priority>HIGH</priority>
@@ -111,7 +117,7 @@
     </collectRegisterFfdc>
 
     <collectFfdc>p9_collect_ppe_state, CHIP, PPE_STATE_MODE, PPE_BASE_ADDRESS_LIST</collectFfdc>
-    
+
     <callout>
       <procedure>CODE</procedure>
       <priority>LOW</priority>