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| author | Santosh Balasubramanian <sbalasub@in.ibm.com> | 2017-04-04 04:40:56 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-04-07 14:21:32 -0400 |
| commit | 996a0d23bd5f94e017fcba2d9d053455159f7b12 (patch) | |
| tree | 9da7fd9c5a2636496fe2e8bae492f7f9701f29a2 /src | |
| parent | d65fbf80c4dc69bf2af026984c7eee8feadfcc17 (diff) | |
| download | talos-hostboot-996a0d23bd5f94e017fcba2d9d053455159f7b12.tar.gz talos-hostboot-996a0d23bd5f94e017fcba2d9d053455159f7b12.zip | |
Fix for read modify write.
Change-Id: Ia180eb6a0f5a5ee31ad4684ffa13d37e62bfaf06
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38771
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38775
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_update_security_ctrl.C | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_update_security_ctrl.C b/src/import/chips/p9/procedures/hwp/perv/p9_update_security_ctrl.C index a2f22062c..fac0e638e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_update_security_ctrl.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_update_security_ctrl.C @@ -69,6 +69,10 @@ fapi2::ReturnCode p9_update_security_ctrl(const fapi2::Target<fapi2::TARGET_TYPE if ((l_in_secure_mode == 1) || (i_force_security)) //Chip in Secure mode or override with i_force_security parameter { + //SECURITY_SWITCH_REGISTER is SET only register - hence clearing '0' before setting specific bits + //To Avoid the issue of a read modified write + l_data64.flush<0>(); + //Set bit 4 to set SUL l_data64.setBit<PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK>(); |
