Add mss_ddr_phy_reset procedure to HB code base

Update from review comments

Change-Id: I300b5b855aa61cd4a73d3e6ac5959071904b96fb
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/782
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

7 files changed, 763 insertions, 196 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index c765f52a4..046a0de54 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -58,6 +58,10 @@
 #include    <fapi.H>
 #include    <fapiPlatHwpInvoker.H>
 
+#include <targeting/util.H>
+const uint8_t UNLIMITED_RUN = 0xFF;
+const uint8_t VPO_NUM_OF_MBAS_TO_RUN = 1;
+const uint8_t VPO_NUM_OF_MEMBUF_TO_RUN = 1;
 
 //  --  prototype   includes    --
 //  Add any customized routines that you don't want overwritten into
@@ -66,13 +70,13 @@
 
 #include    "dram_training.H"
 
-//  Uncomment these files as they become available:
+//  Un-comment these files as they become available:
 // #include    "host_disable_vddr/host_disable_vddr.H"
 // #include    "mc_pll_setup/mc_pll_setup.H"
 // #include    "mba_startclocks/mba_startclocks.H"
 // #include    "host_enable_vddr/host_enable_vddr.H"
 // #include    "mss_initf/mss_initf.H"
-// #include    "mss_ddr_phy_reset/mss_ddr_phy_reset.H"
+#include    "mss_ddr_phy_reset/mss_ddr_phy_reset.H"
 #include    "mss_draminit/mss_draminit.H"
 // #include    "mss_restore_dram_repair/mss_restore_dram_repair.H"
 #include    "mss_draminit_training/mss_draminit_training.H"
@@ -85,8 +89,6 @@ namespace   DRAM_TRAINING
 using   namespace   TARGETING;
 using   namespace   fapi;
 
-
-
 //
 //  Wrapper function to call 13.1 : host_disable_vddr
 //
@@ -115,6 +117,7 @@ void    call_host_disable_vddr( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -180,6 +183,7 @@ void    call_mc_pll_setup( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -245,6 +249,7 @@ void    call_mba_startclocks( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -310,6 +315,7 @@ void    call_host_enable_vddr( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -375,6 +381,7 @@ void    call_mss_initf( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -410,63 +417,72 @@ void    call_mss_initf( void *io_pArgs )
     task_end();
 }
 
-
-
 //
 //  Wrapper function to call 13.6 : mss_ddr_phy_reset
 //
-void    call_mss_ddr_phy_reset( void *io_pArgs )
+void  call_mss_ddr_phy_reset( void *io_pArgs )
 {
     //  @todo   remove when join() merged
     INITSERVICE::TaskArgs *pTaskArgs =
             static_cast<INITSERVICE::TaskArgs *>( io_pArgs );
-    fapi::ReturnCode    l_fapirc;
+    errlHndl_t l_err = NULL;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset entry" );
 
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
-
-    //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "=====  mss_ddr_phy_reset HWP(? ? ? )",
-                    ?
-                    ?
-                    ? );
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
-
-    // cast OUR type of target to a FAPI type of target.
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-
-    //  call the HWP with each fapi::Target
-    l_fapirc  =   mss_ddr_phy_reset( ? , ?, ? );
+    // Get all MBA targets
+    //  Use PredicateIsFunctional to filter only functional chips
+    TARGETING::PredicateIsFunctional    l_isFunctional;
+    //  find all the MBA's in the system
+    TARGETING::PredicateCTM             l_mbaFilter(CLASS_UNIT, TYPE_MBA);
+    // declare a postfix expression widget
+    TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter;
+    //  is-a-membuf-chip  is-functional   AND
+    l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And();
+    // loop through all the targets, applying the filter,  and put the results in l_pMemBufs
+    TARGETING::TargetRangeFilter    l_pMbas(
+            TARGETING::targetService().begin(),
+            TARGETING::targetService().end(),
+            &l_functionalAndMbaFilter );
 
-    //  process return code.
-    if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+    // Limit the number of MBAs to run in VPO environment to save time.
+    uint8_t l_mbaLimit = UNLIMITED_RUN;
+    if (TARGETING::is_vpo() )
     {
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "SUCCESS :  mss_ddr_phy_reset HWP(? ? ? )" );
+           l_mbaLimit = VPO_NUM_OF_MBAS_TO_RUN;
     }
-    else
+
+    for (   uint8_t l_mbaNum=0 ;
+            (l_mbaNum < l_mbaLimit) && l_pMbas ;
+            l_mbaNum++, ++l_pMbas    )
     {
-        /**
-         * @todo fapi error - just print out for now...
-         */
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR %d:  mss_ddr_phy_reset HWP(? ? ?) ",
-                static_cast<uint32_t>(l_fapirc) );
+        //  make a local copy of the target for ease of use
+        const TARGETING::Target*  l_mba_target = *l_pMbas;
+
+        // Dump current run on target
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running call_mss_ddr_phy_reset HWP on..." );
+        EntityPath l_path;
+        l_path  =   l_mba_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        // Cast to a FAPI type of target.
+        const fapi::Target l_fapi_mba_target(
+                TARGET_TYPE_MEMBUF_CHIP,
+                reinterpret_cast<void *>
+        (const_cast<TARGETING::Target*>(l_mba_target)) );
+
+        //  call the HWP with each fapi::Target
+        FAPI_INVOKE_HWP(l_err, mss_ddr_phy_reset, l_fapi_mba_target);
+
+        if (l_err)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : mss_ddr_phy_reset HWP returns error");
+            errlCommit(l_err, HWPF_COMP_ID);
+        }
+        else
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  call_mss_ddr_phy_reset HWP( )" );
+        }
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-#endif
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset exit" );
 
@@ -482,15 +498,14 @@ void    call_mss_ddr_phy_reset( void *io_pArgs )
 //
 void    call_mss_draminit( void *io_pArgs )
 {
-    //  @todo   remove when join() merged
+
     INITSERVICE::TaskArgs *pTaskArgs =
             static_cast<INITSERVICE::TaskArgs *>( io_pArgs );
-    fapi::ReturnCode    l_fapirc;
+    errlHndl_t l_err = NULL;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit entry" );
 
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-    //  mss_draminit wants centaur.mba's
+    // Get all MBA targets
     //  Use PredicateIsFunctional to filter only functional chips
     TARGETING::PredicateIsFunctional    l_isFunctional;
     //  find all the MBA's in the system
@@ -505,48 +520,46 @@ void    call_mss_draminit( void *io_pArgs )
             TARGETING::targetService().end(),
             &l_functionalAndMbaFilter );
 
+    // Limit the number of MBAs to run in VPO environment to save time.
+    uint8_t l_mbaLimit = UNLIMITED_RUN;
+    if (TARGETING::is_vpo() )
+    {
+           l_mbaLimit = VPO_NUM_OF_MBAS_TO_RUN;
+    }
+
     for (   uint8_t l_mbaNum=0 ;
-            l_pMbas ;
-            l_mbaNum++, ++l_pMbas
-    )
+            (l_mbaNum < l_mbaLimit) && l_pMbas ;
+            l_mbaNum++, ++l_pMbas    )
     {
-        //  make a local copy of the target for ease of use
+        // Make a local copy of the target for ease of use
         const TARGETING::Target*  l_mba_target = *l_pMbas;
 
-        //  print call to hwp and dump physical path of the target(s)
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "=====  mss_draminit HWP(  )" );
-        //  dump physical path to targets
+        // Dump current run on target
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit HWP on...");
         EntityPath l_path;
         l_path  =   l_mba_target->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
-        // cast OUR type of target to a FAPI type of target.
+        // Cast to a FAPI type of target.
         const fapi::Target l_fapi_mba_target(
                 TARGET_TYPE_MBA_CHIPLET,
                 reinterpret_cast<void *>
-        (const_cast<TARGETING::Target*>(l_mba_target)) );
+                (const_cast<TARGETING::Target*>(l_mba_target)) );
 
         //  call the HWP with each fapi::Target
-        l_fapirc  =   mss_draminit( l_fapi_mba_target );
+        FAPI_INVOKE_HWP(l_err, mss_draminit, l_fapi_mba_target);
 
-        //  process return code.
-        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        if (l_err)
         {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  mss_draminit HWP(? ? ? )" );
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : mss_draminit HWP returns error");
+            errlCommit(l_err, HWPF_COMP_ID);
         }
         else
         {
-            /**
-             * @todo fapi error - just print out for now...
-             */
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "ERROR %d:  mss_draminit HWP( ) ",
-                    static_cast<uint32_t>(l_fapirc) );
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  mss_draminit HWP( )" );
         }
+
     }   // endfor   mba's
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit exit" );
 
@@ -555,8 +568,6 @@ void    call_mss_draminit( void *io_pArgs )
     task_end();
 }
 
-
-
 //
 //  Wrapper function to call 13.8 : mss_restore_dram_repair
 //
@@ -585,6 +596,7 @@ void    call_mss_restore_dram_repair( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -627,15 +639,15 @@ void    call_mss_restore_dram_repair( void *io_pArgs )
 //
 void    call_mss_draminit_training( void *io_pArgs )
 {
+
     //  @todo   remove when join() merged
     INITSERVICE::TaskArgs *pTaskArgs =
             static_cast<INITSERVICE::TaskArgs *>( io_pArgs );
-    fapi::ReturnCode    l_fapirc;
+    errlHndl_t l_err = NULL;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training entry" );
 
-
-    // @@@@@    CUSTOM BLOCK:   @@@@@
+    // Get all MBA targets
     //  Use PredicateIsFunctional to filter only functional chips
     TARGETING::PredicateIsFunctional    l_isFunctional;
     //  find all the MBA's in the system
@@ -650,49 +662,47 @@ void    call_mss_draminit_training( void *io_pArgs )
             TARGETING::targetService().end(),
             &l_functionalAndMbaFilter );
 
+    // Limit the number of MBAs to run in VPO environment to save time.
+    uint8_t l_mbaLimit = UNLIMITED_RUN;
+    if (TARGETING::is_vpo() )
+    {
+           l_mbaLimit = VPO_NUM_OF_MBAS_TO_RUN;
+    }
+
     for (   uint8_t l_mbaNum=0 ;
-            l_pMbas ;
-            l_mbaNum++, ++l_pMbas
-    )
+            (l_mbaNum < l_mbaLimit) && l_pMbas ;
+            l_mbaNum++, ++l_pMbas    )
     {
         //  make a local copy of the target for ease of use
         const TARGETING::Target*  l_mba_target = *l_pMbas;
 
-        //  print call to hwp and dump physical path of the target(s)
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "=====  mss_draminit_training HWP( )" );
-        //  dump physical path to targets
+        // Dump current run on target
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit_training HWP on..." );
         EntityPath l_path;
         l_path  =   l_mba_target->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
-        // cast OUR type of target to a FAPI type of target.
+        // Cast to a FAPI type of target.
         const fapi::Target l_fapi_mba_target(
-                TARGET_TYPE_MBA_CHIPLET,
+                TARGET_TYPE_MEMBUF_CHIP,
                 reinterpret_cast<void *>
         (const_cast<TARGETING::Target*>(l_mba_target)) );
 
+
         //  call the HWP with each fapi::Target
-        l_fapirc  =   mss_draminit_training( l_fapi_mba_target );
+        FAPI_INVOKE_HWP(l_err, mss_draminit_training, l_fapi_mba_target);
 
-        //  process return code.
-        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        if (l_err)
         {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  mss_draminit_training HWP( )" );
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : mss_draminit_training HWP returns error");
+            errlCommit(l_err, HWPF_COMP_ID);
         }
         else
         {
-            /**
-             * @todo fapi error - just print out for now...
-             */
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "ERROR %d:  mss_draminit_training HWP( ) ",
-                    static_cast<uint32_t>(l_fapirc) );
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  mss_draminit_training HWP( )" );
         }
-    }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
+    }
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training exit" );
 
@@ -701,8 +711,6 @@ void    call_mss_draminit_training( void *io_pArgs )
     task_end();
 }
 
-
-
 //
 //  Wrapper function to call 13.10 : mss_draminit_trainadv
 //
@@ -731,6 +739,7 @@ void    call_mss_draminit_trainadv( void *io_pArgs )
     EntityPath l_path;
     l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
     l_path.dump();
+    TRACFCOMP( g_trac_mc_init, "===== " );
 
     // cast OUR type of target to a FAPI type of target.
     const fapi::Target l_fapi_@targetN_target(
@@ -766,80 +775,74 @@ void    call_mss_draminit_trainadv( void *io_pArgs )
     task_end();
 }
 
-
-
 //
 //  Wrapper function to call 13.11 : mss_draminit_mc
 //
 void    call_mss_draminit_mc( void *io_pArgs )
 {
+
     //  @todo   remove when join() merged
     INITSERVICE::TaskArgs *pTaskArgs =
             static_cast<INITSERVICE::TaskArgs *>( io_pArgs );
-    fapi::ReturnCode    l_fapirc;
+    errlHndl_t l_err = NULL;
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc entry" );
 
-    // @@@@@    CUSTOM BLOCK:   @@@@@
+    // Get all centaur targets
     //  Use PredicateIsFunctional to filter only functional chips
-    TARGETING::PredicateIsFunctional    l_isFunctional;
-    //  find all the Centaurs in the system
-    TARGETING::PredicateCTM             l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF);
+    TARGETING::PredicateIsFunctional             l_isFunctional;
+    //  filter for functional Centaur Chips
+    TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF);
     // declare a postfix expression widget
     TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter;
     //  is-a-membuf-chip  is-functional   AND
     l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And();
-    // loop through all the targets, applying the filter,  and put the results in l_pMbas
+    // loop through all the targets, applying the filter,  and put the results in l_pMemBufs
     TARGETING::TargetRangeFilter    l_pMemBufs(
             TARGETING::targetService().begin(),
             TARGETING::targetService().end(),
             &l_functionalAndMembufChipFilter );
 
-    for (   uint8_t l_membufNum=0 ;
-            l_pMemBufs ;
-            l_membufNum++, ++l_pMemBufs
-    )
+    // Limit the number of MBAs to run in VPO environment to save time.
+    uint8_t l_memBufLimit = UNLIMITED_RUN;
+    if (TARGETING::is_vpo() )
     {
-        //  make a local copy of the target for ease of use
+        l_memBufLimit = VPO_NUM_OF_MEMBUF_TO_RUN ;
+    }
+
+    for (uint8_t l_memBufNum=0 ;
+            (l_memBufNum < l_memBufLimit) && l_pMemBufs ;
+            l_memBufNum++, ++l_pMemBufs)
+    {
+
         const TARGETING::Target*  l_membuf_target = *l_pMemBufs;
 
-        //  print call to hwp and dump physical path of the target(s)
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "=====  mss_draminit_mc HWP( %d )",
-                l_membufNum );
-        //  dump physical path to targets
+        // Dump current run on target
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit_mc HWP on..." );
         EntityPath l_path;
         l_path  =   l_membuf_target->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
-        // cast OUR type of target to a FAPI type of target.
-        const fapi::Target l_fapi_membuf_target(
+        // Cast to a fapi target
+        fapi::Target l_fapi_membuf_target(
                 TARGET_TYPE_MEMBUF_CHIP,
                 reinterpret_cast<void *>
-        (const_cast<TARGETING::Target*>(l_membuf_target)) );
+                (const_cast<TARGETING::Target*>(l_membuf_target)) );
 
         //  call the HWP with each fapi::Target
-        l_fapirc  =   mss_draminit_mc( l_fapi_membuf_target );
+        FAPI_INVOKE_HWP(l_err, mss_draminit_mc, l_fapi_membuf_target);
 
-        //  process return code.
-        if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
+        if (l_err)
         {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  mss_draminit_mc HWP( %d )",
-                    l_membufNum );
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : mss_draminit_mc HWP returns error");
+            errlCommit(l_err, HWPF_COMP_ID);
         }
         else
         {
-            /**
-             * @todo fapi error - just print out for now...
-             */
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "ERROR %d:  mss_draminit_mc HWP( %d ) ",
-                    static_cast<uint32_t>(l_fapirc),
-                    l_membufNum );
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  mss_draminit_mc HWP( )" );
         }
+
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc exit" );
 
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile
index 871f2701d..887b89c6a 100644
--- a/src/usr/hwpf/hwp/dram_training/makefile
+++ b/src/usr/hwpf/hwp/dram_training/makefile
@@ -44,19 +44,21 @@ EXTRAINCDIR	+= ${ROOTPATH}/src/usr/hwpf/hwp/dram_training
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset
 
 ##  NOTE: add new object files when you add a new HWP
 OBJS =  dram_training.o \
         mss_draminit.o \
         mss_funcs.o \
         mss_draminit_mc.o \
-        mss_draminit_training.o
+        mss_draminit_training.o \
+        mss_ddr_phy_reset.o
    		
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
-
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset
 
 include ${ROOTPATH}/config.mk
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
new file mode 100644
index 000000000..b3aee3a57
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
@@ -0,0 +1,472 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+// $Id: mss_ddr_phy_reset.C,v 1.4 2012/02/22 18:36:36 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_ddr_phy_reset
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
+// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// #! ADDITIONAL COMMENTS :
+//
+// The purpose of this procedure is to do a soft reset of the DDR PHY logic
+// and to get the Centaur chip ready for DRAM initializaion.
+// See sepecific instructions below.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include <cen_scom_addresses.H>
+
+uint64_t  delay_1ns               = 1;        // general purpose 1 ns delay for HW mode        (20 sim cycles if simclk - 20ghz)
+uint64_t  delay_10ns              = 10;       // general purpose 10 ns delay for HW mode       (200 sim cycles if simclk - 20ghz)
+uint64_t  delay_100ns             = 100;      // general purpose 100 ns delay for HW mode      (2000 sim cycles if simclk - 20ghz)
+uint64_t  delay_1us               = 1000;     // general purpose 1 usec delay for HW mode      (20000 sim cycles if simclk - 20ghz)
+uint64_t  delay_10us              = 10000;    // general purpose 10 usec delay for HW mode     (200000 sim cycles if simclk - 20ghz)
+uint64_t  delay_100us             = 100000;   // general purpose 100 usec delay for HW mode    (2000000 sim cycles if simclk - 20ghz)
+uint64_t  delay_1ms               = 1000000;  // general purpose 1 ms delay for HW mode        (20000000 sim cycles if simclk - 20ghz)
+uint64_t  delay_20simcycles       = 20;       // general purpose 20 sim cycle delay for sim mode       (1 ns if simclk = 20Ghz)
+uint64_t  delay_200simcycles      = 200;      // general purpose 200 sim cycle delay for sim mode      (10 ns if simclk = 20Ghz)
+uint64_t  delay_2000simcycles     = 2000;     // general purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
+uint64_t  delay_20000simcycles    = 20000;    // general purpose 20000 sim cycle delay for sim mode    (1 usec if simclk = 20Ghz)
+uint64_t  delay_200000simcycles   = 200000;   // general purpose 200000 sim cycle delay for sim mode   (10 usec if simclk = 20Ghz)
+uint64_t  delay_2000000simcycles  = 2000000;  // general purpose 2000000 sim cycle delay for sim mode  (100 usec if simclk = 20Ghz)
+uint64_t  delay_20000000simcycles = 20000000; // general purpose 20000000 sim cycle delay for sim mode (1 ms if simclk = 20Ghz)
+
+
+extern "C" {
+
+
+using namespace fapi;
+
+//ReturnCode mss_ddr_phy_reset(Target i_target, bool i_parm1, uint32_t i_parm2) {
+ReturnCode mss_ddr_phy_reset(Target i_target) {
+  ReturnCode l_rc;
+  ecmdDataBufferBase data;
+  ecmdDataBufferBase mask;
+  ecmdDataBufferBase i_data, j_data, k_data, l_data;
+  i_data.setBitLength(64);
+  j_data.setBitLength(64);
+  k_data.setBitLength(64);
+  l_data.setBitLength(64);
+  uint32_t poll_count = 0;
+  uint32_t done_polling = 0;
+  uint8_t dram_gen = 0; 
+
+  FAPI_INF("");
+  FAPI_INF("********* *********************** *********");
+  FAPI_INF("********* mss_ddr_phy_reset start *********");
+  FAPI_INF("********* *********************** *********");
+
+  //FAPI_INF("mss_ddr_phy_reset::My parms are:");
+  //FAPI_INF("       ::i_parm1 = %d", i_parm1);
+  //FAPI_INF("       ::i_parm2 = %d", i_parm2);
+ 
+  //l_rc = fapiGetScom(i_target, 0x000F0012, data );
+  //if (l_rc) {
+  //  FAPI_ERR("fapiGetScom() failed."); return l_rc;
+  //}
+  //data.flushTo1();
+  //data.clearBit(0); 
+  //data.clearBit(31); 
+  //l_rc = fapiPutScom(i_target, 0x000F0012, data );
+  //if (l_rc) {
+  //  FAPI_ERR("fapiGetScom() failed."); return l_rc;
+  //}
+
+  //
+  // Here are the specific instructions from section 14.7.2 of the Centaur Chip Specification:
+  // 
+  // Run cen_ddr_phy_reset.C prepares the DDR PLLs. These PLLs were previously configured via scan init, but have
+  // been held in reset. At this point the PLL GP bit is deasserted to take the PLLs out of reset.
+  // Note - this is done in the cen_startclocks.C procedure.
+  //
+  // The cen_ddr_phy_reset.C now resets the DDR PHY logic. This process will NOT destroy any configuration values
+  // previously loaded via the init file. The intent is for the initialized phase rotator configuration to remain valid after the
+  // soft reset completes. If this assumption fails to hold true, it will require replacing this step with a PHY hard reset,
+  // and then using inband configuration writes to restore all the DDR Configuration Registers.
+  //
+  // The following steps must be performed as part of the PHY reset procedure.
+
+
+
+  //
+  // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value.
+  //    (Note: The chip should already be in this state.)
+    FAPI_DBG("Step 1: All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values.\n");
+
+
+
+  //
+  // 2. For DD0: Assert dfi_reset_all (GP4 bit 5 = "1") for at least 32 memory clock cycles. This signal DOES
+  //    erradicate all DDR configuration register initialization, thereby requiring the DDR registers to be reprogrammed
+  //    via SCOM after the PHY reset sequence completes.
+  //    For DD1: Set mcbist_ddr_dfi_reset_recover ="1" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 & 0x03010EA7)
+  //    for at least 32 memory clock cycles. This signal does NOT reset the configuration registers
+  //    within the PHY.
+
+    FAPI_DBG("Step 2: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 1 for DDR PHY soft reset.\n");
+    l_rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data); if ( l_rc ) return l_rc;
+    data.setBit(25);
+    l_rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data); if ( l_rc ) return l_rc;
+
+    fapiDelay(delay_100ns, delay_2000simcycles); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
+
+
+
+  //
+  // 3. For DD0: Deassert dfi_reset_all (GP4 bit 5 = "0")
+  //    For DD1: Deassert mcbist_ddr_dfi_reset_recover = "0" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 0x03010EA7)
+    FAPI_DBG("Step 3: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 0 to release soft reset.\n");
+    l_rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data); if ( l_rc ) return l_rc;
+    data.clearBit(25);
+    l_rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 4. Write 0x0008 to PC IO PVT N/P FET driver control registers to assert ZCTL reset
+  //    and reset the internal impedance controller.(SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+    FAPI_DBG("Step 4: Write 0x0008 to PC IO PVT N/P FET driver control registers to assert ZCTL reset.\n");
+    i_data.setHalfWord(3, 0x0008);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 5. Write 0x0000 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset
+  //                                                (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+    FAPI_DBG("Step 5: Write 0x0000 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset.\n");
+    i_data.setHalfWord(3, 0x0000);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 6. For DD0: 32 memory clock cycles after asserting dfi_reset_recover, program the following registers
+  //    to all zeros for DDR3. Set to 0x1202 for DDR4
+  // -- Set PC Configuration 0            to 0x0000 for DDR3 or 0x1202 for DDR4
+  //                                                (SCOM Addr: 0x8000C00C0301143F, 0x8000C00C0301183F, 0x8001C00C0301143F, 0x8001C00C0301183F)
+  // -- Set ADR PLL/VREG Configuration 0  to 0x0000 (SCOM Addr: 0x800080300301143F, 0x800084300301143F, 0x800180300301143F, 0x800184300301143F,
+  //                                                            0x800080300301183F, 0x800084300301183F, 0x800180300301183F, 0x800184300301183F)
+  // -- Set ADR PLL/VREG Configuration 1  to 0x0040 (SCOM Addr: 0x800080310301143F, 0x800084310301143F, 0x800180310301143F, 0x800184310301143F,
+  //                                                            0x800080310301183F, 0x800084310301183F, 0x800180310301183F, 0x800184310301183F)
+  // -- Set DP18 PLL/VREG Configuration 0 to 0x0000 (SCOM Addr: 0x800000760301143F, 0x800004760301143F, 0x800008760301143F, 0x80000C760301143F, 0x800010760301143F,
+  //                                                            0x800000760301183F, 0x800004760301183F, 0x800008760301183F, 0x80000C760301183F, 0x800010760301183F,
+  //                                                            0x800100760301143F, 0x800104760301143F, 0x800108760301143F, 0x80010C760301143F, 0x800110760301143F,
+  //                                                            0x800100760301183F, 0x800104760301183F, 0x800108760301183F, 0x80010C760301183F, 0x800110760301183F)
+  // -- Set DP18 PLL/VREG Configuration 1 to 0x0040 (SCOM Addr: 0x800000770301143F, 0x800004770301143F, 0x800008770301143F, 0x80000C770301143F, 0x800010770301143F,
+  //                                                            0x800000770301183F, 0x800004770301183F, 0x800008770301183F, 0x80000C770301183F, 0x800010770301183F,
+  //                                                            0x800100770301143F, 0x800104770301143F, 0x800108770301143F, 0x80010C770301143F, 0x800110770301143F,
+  //                                                            0x800100770301183F, 0x800104770301183F, 0x800108770301183F, 0x80010C770301183F, 0x800110770301183F)
+  //    For DD1; This step might be able to be skipped if the PLL registers will be scan initialized to the proper values.
+
+    // Step 6a: selects either 0x0000 (for DDR3) or 0x1202 (for DDR4) based on the dram_generation attribute
+    l_rc = FAPI_ATTR_GET( ATTR_EFF_DRAM_GEN, &i_target, dram_gen); if ( l_rc ) return l_rc;
+    if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
+    {
+        FAPI_DBG("Step 6a: Set PC Configuration 0 to 0x1202 for DDR4.\n");
+        i_data.setHalfWord(3, 0x1202);
+    }
+    else
+    {
+        FAPI_DBG("Step 6a: Set PC Configuration 0 to 0x0000 for DDR3.\n");
+        i_data.setHalfWord(3, 0x0000);
+    }
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_CONFIG0_P0_0x8000C00C0301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_CONFIG0_P1_0x8001C00C0301143F, i_data); if ( l_rc ) return l_rc;
+
+    FAPI_DBG("Step 6b: Set ADR PLL/VREG Configuration 0 to 0x0000.\n");
+    i_data.setHalfWord(3, 0x0000);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_0x800080300301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_0x800180300301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_0x800084300301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_0x800184300301143F, i_data); if ( l_rc ) return l_rc;
+
+    FAPI_DBG("Step 6c: Set ADR PLL/VREG Configuration 1 to 0x0040.\n");
+    i_data.setHalfWord(3, 0x0040);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_0x800080310301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_0x800180310301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_0x800084310301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_0x800184310301143F, i_data); if ( l_rc ) return l_rc;
+
+    FAPI_DBG("Step 6d: Set DP18 PLL/VREG Configuration 0 to 0x0000.\n");
+    i_data.setHalfWord(3, 0x0000);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_0_0x800000760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_0_0x800100760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_1_0x800004760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_1_0x800104760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_2_0x800008760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_2_0x800108760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_3_0x80000C760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_3_0x80010C760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_4_0x800010760301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_4_0x800110760301143F, i_data); if ( l_rc ) return l_rc;
+
+    FAPI_DBG("Step 6e: Set DP18 PLL/VREG Configuration 1 to 0x0040.\n");
+    i_data.setHalfWord(3, 0x0040);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_0_0x800000770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_0_0x800100770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_1_0x800004770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_1_0x800104770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_2_0x800008770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_2_0x800108770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_3_0x80000C770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_3_0x80010C770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_4_0x800010770301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_4_0x800110770301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 7. Wait at least 1 microsecond. This is the required PLL reset time.  (This may be skipped for DD1)
+    FAPI_DBG("Step 7: PLL reset delay is not required for Centaur DD1.\n");
+    // This delay should not be required for DD1
+    // fapiDelay(delay_1us, delay_20000simcycles); // wait 20000 simcycles (in sim mode) OR 1 usec (in hw mode)
+
+
+
+  //
+  // 8. Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active
+  //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
+    FAPI_DBG("Step 8: Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active.\n");
+    i_data.setHalfWord(3, 0x4000);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 9. Wait at least 1 millisecond to allow the PLLs to lock. Otherwise, poll the PC DP18 PLL Lock Status
+  //    and the PC AD32S PLL Lock Status to determine if all PLLs have locked.
+  //    PC DP18 PLL Lock Status should be 0xF800:  (SCOM Addr: 0x8000C0000301143F, 0x8001C0000301143F, 0x8000C0000301183F, 0x8001C0000301183F)
+  //    PC AD32S PLL Lock Status should be 0xC000: (SCOM Addr: 0x8000C0010301143F, 0x8001C0010301143F, 0x8000C0010301183F, 0x8001C0010301183F)
+    FAPI_DBG("Step 9: Poll until DP18 and AD32S PLLs have locked....\n");
+    // fapiDelay(delay_1ms, delay_20000000simcycles); // wait 20000000 simcycles (in sim mode) OR 1 mS (in hw mode)
+    do
+    {
+        fapiDelay(delay_1us, delay_20000simcycles); // wait 20000 simcycles (in sim mode) OR 1 usec (in hw mode)
+        done_polling = 1;
+        l_rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, i_data); if ( l_rc ) return l_rc;
+        if ( i_data.getHalfWord(3) != 0xF800 ) done_polling = 0;
+        l_rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, j_data); if ( l_rc ) return l_rc;
+        if ( j_data.getHalfWord(3) != 0xF800 ) done_polling = 0;
+        l_rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, k_data); if ( l_rc ) return l_rc;
+        if ( k_data.getHalfWord(3) != 0xC000 ) done_polling = 0;
+        l_rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, l_data); if ( l_rc ) return l_rc;
+        if ( l_data.getHalfWord(3) != 0xC000 ) done_polling = 0;
+
+
+//      FAPI_INF("Polling Loop = %i", poll_count);
+//      if ( i_data.getHalfWord(3) != 0xF800 ) FAPI_ERR("DP18  0x0C000 PLL failed to lock!   Lock Status = %04X",i_data.getHalfWord(3));
+//      if ( j_data.getHalfWord(3) != 0xF800 ) FAPI_ERR("DP18  0x1C000 PLL failed to lock!   Lock Status = %04X",j_data.getHalfWord(3));
+//      if ( k_data.getHalfWord(3) != 0xC000 ) FAPI_ERR("AD32S 0x0C001 PLL failed to lock!   Lock Status = %04X",k_data.getHalfWord(3));
+//      if ( l_data.getHalfWord(3) != 0xC000 ) FAPI_ERR("AD32S 0x1C001 PLL failed to lock!   Lock Status = %04X",l_data.getHalfWord(3));
+
+
+        poll_count++;
+    } while ((done_polling == 0) && (poll_count < 10)); // Poll until PLLs are locked.
+
+    if (poll_count == 10)
+    {
+        FAPI_ERR("DP18 and/or AD32S PLLs failed to lock!");
+        if ( i_data.getHalfWord(3) != 0xF800 ) FAPI_ERR("DP18  0x0C000 PLL failed to lock!   Lock Status = %04X",i_data.getHalfWord(3));
+        if ( j_data.getHalfWord(3) != 0xF800 ) FAPI_ERR("DP18  0x1C000 PLL failed to lock!   Lock Status = %04X",j_data.getHalfWord(3));
+        if ( k_data.getHalfWord(3) != 0xC000 ) FAPI_ERR("AD32S 0x0C001 PLL failed to lock!   Lock Status = %04X",k_data.getHalfWord(3));
+        if ( l_data.getHalfWord(3) != 0xC000 ) FAPI_ERR("AD32S 0x1C001 PLL failed to lock!   Lock Status = %04X",l_data.getHalfWord(3));
+    }
+    else
+    {
+        FAPI_INF("DP18 and AD32S PLLs are now locked.");
+    }
+
+
+
+  //
+  // 10.Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
+  //    This takes the dphy_nclk/SysClk alignment circuit out of reset and puts the dphy_nclk/SysClk alignment circuit into the Continuous Update Mode.
+  //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
+  //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
+  //          DP18 SysClk PR Control Registers  :  (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F,
+  //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
+  //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
+  //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
+    FAPI_DBG("Step 10: Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.\n");
+    i_data.setHalfWord(3, 0x8024);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 11.Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.
+    FAPI_DBG("Step 11: Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.\n");
+    fapiDelay(delay_100us, delay_2000000simcycles); // wait 2000000 simcycles (in sim mode) OR 100 usec (in hw mode)
+
+
+
+  //
+  // 12.Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset
+  //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
+    FAPI_DBG("Step 12: Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset.\n");
+    i_data.setHalfWord(3, 0x0000);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 13.Write '8020'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
+  //    This takes the dphy_nclk/SysClk alignment circuit out of Continuous Update Mode.
+  //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
+  //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
+  //          DP18 SysClk PR Control Registers  :  (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F,
+  //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
+  //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
+  //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
+    FAPI_DBG("Step 13: .\n");
+    i_data.setHalfWord(3, 0x8020);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); if ( l_rc ) return l_rc;
+
+
+
+  //
+  // 14.Wait at least 32 memory clock cycles.
+    FAPI_DBG("Step 14: Wait at least 32 memory clock cycles.\n");
+    fapiDelay(delay_100ns, delay_2000simcycles); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
+
+
+
+  //
+  // 15.For DD0, use of reset_all results in all DDR configuration informating being erradicated. Therefore, a
+  //    multitude of registers needs to be reprogrammed via SCOM. The entire list is enumerated in Section 5.2
+  //    Table 51 of the Neo Spec (those with a value of 2, 3 or 4 in the Notes column). The values of these registers
+  //    depend on system topology, configuration, physical and environmental characteristics and are maintained in
+  //    design data.
+  //    For DD1, this step is skipped as those registers would've been configured via scan initialization and should
+  //    still be valid due to use of reset_recover.
+    FAPI_DBG("Step 15: This step can be skipped for DD1.\n");
+
+
+
+  //
+  // 16.Write 0x0010 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.
+  //    This step takes approximately 2112 (64 * 33) memory clock cycles.
+  //                                                (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+    FAPI_DBG("Step 16: Write 0x0010 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.\n");
+    i_data.setHalfWord(3, 0x0010);
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data); if ( l_rc ) return l_rc;
+    l_rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data); if ( l_rc ) return l_rc;
+
+  //
+
+
+
+
+  FAPI_INF("");
+  FAPI_INF("********* ************************** *********");
+  FAPI_INF("********* mss_ddr_phy_reset complete *********");
+  FAPI_INF("********* ************************** *********");
+  return l_rc;
+}
+
+} //end extern C
+
+
+
+
+
+
+/*
+*************** Do not edit this area ***************
+This section is automatically updated by CVS when you check in this file.
+Be sure to create CVS comments when you commit so that they can be included here.
+
+$Log: mss_ddr_phy_reset.C,v $
+Revision 1.4  2012/02/22 18:36:36  mfred
+update for PLL lock polling, and check for ddr3 vs ddr4
+
+Revision 1.3  2012/02/14 16:34:12  mfred
+Fixed code to use halfword(3) instead of halfword(0)
+
+Revision 1.2  2012/01/31 18:42:07  mfred
+Change proc to do a single MBA and DDRPHY.  Looping will be handled by the target.
+
+Revision 1.1  2011/11/18 14:20:10  mfred
+Changed name of cen_ddr_phy_reset to mss_ddr_phy_reset.
+
+Revision 1.1  2011/10/27 22:49:36  mfred
+New version of cen_ddr_phy_reset that support the extended scom addresses.
+
+Revision 1.5  2011/04/29 16:44:06  mfred
+Removed a couple of unused address variables.
+
+Revision 1.4  2011/04/18 20:12:49  mfred
+Update scom addresses in comments and fix steps 10 and 13 per info from Gary H.
+
+Revision 1.3  2011/04/18 18:54:58  mfred
+Fixed some output messages.
+
+Revision 1.2  2011/04/12 13:22:32  mfred
+Fixed some output messages.
+
+Revision 1.1  2011/04/07 16:15:03  mfred
+Initial release.
+
+
+
+*/
+
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H
new file mode 100644
index 000000000..cb5556733
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H
@@ -0,0 +1,67 @@
+//  IBM_PROLOG_BEGIN_TAG
+//  This is an automatically generated prolog.
+//
+//  $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H $
+//
+//  IBM CONFIDENTIAL
+//
+//  COPYRIGHT International Business Machines Corp. 2012
+//
+//  p1
+//
+//  Object Code Only (OCO) source materials
+//  Licensed Internal Code Source Materials
+//  IBM HostBoot Licensed Internal Code
+//
+//  The source code for this program is not published or other-
+//  wise divested of its trade secrets, irrespective of what has
+//  been deposited with the U.S. Copyright Office.
+//
+//  Origin: 30
+//
+//  IBM_PROLOG_END
+// $Id: mss_ddr_phy_reset.H,v 1.1 2011/11/19 19:19:34 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_ddr_phy_reset.H
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
+// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// Header file for mss_ddr_phy_reset.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.1    | mfred  | 11/19/11| Updated
+
+#ifndef MSS_DDR_PHY_RESETHWPB_H_
+#define MSS_DDR_PHY_RESETHWPB_H_
+
+#include <fapi.H>
+
+extern "C"
+{
+
+/**
+ * @brief ddr_phy_reset procedure.
+ *
+ * @param[in]  i_target  Reference to target
+ *
+ * @return ReturnCode
+ */
+
+fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target target);
+
+} // extern "C"
+
+#endif // MSS_DDR_PHY_RESETHWPB_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 1689c244e..263bcc61e 100755
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -1,7 +1,7 @@
 //  IBM_PROLOG_BEGIN_TAG
 //  This is an automatically generated prolog.
 //
-//  $Source: src/usr/HWPs/dmi_training/cen_scom_addresses.H $
+//  $Source: src/usr/hwpf/hwp/include/cen_scom_addresses.H $
 //
 //  IBM CONFIDENTIAL
 //
@@ -20,7 +20,7 @@
 //  Origin: 30
 //
 //  IBM_PROLOG_END
-// $Id: cen_scom_addresses.H,v 1.11 2012/01/06 22:34:45 jmcgill Exp $
+// $Id: cen_scom_addresses.H,v 1.15 2012/03/06 16:40:00 divyakum Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -37,6 +37,30 @@
 // This will help catch address typos at compile time, and will make it easy
 // to track down which procedures use each address
 //
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//         |          |         | 
+//  1.15   | divyakum |06-Mar-12| Added calibration status regs
+//  1.14   | divyakum |22-Feb-12| Added CALIBRATION registers.
+//         |          |         | Added Change history table
+//  1.13   | mfred    |24-Jan-12| Moved common multicast address constants to common_scom_accresses.H
+//  1.12   | mfred    |24-Jan-12| Move multicast group 1 to group 3 for consistency with P8
+//  1.11   | jmcgill  |06-Jan-12| move shared/common addresses to common_scom_addresses.H, general cleanup
+//  1.10   | mfred    |26-Oct-12| Fix error.  Extra space in an address was causing compile failure.
+//  1.9    | mfred    |25-Oct-12| Added MEM chiplet indirect scom addresses (DPHY registers).
+//  1.8    | venton   |20-Sep-12| Add missing SCOMs from P8
+//  1.7    | mfred    |02-Aug-12| added some 8-bit constants for use with P0 and P1
+//  1.6    | mfred    |28-Aug-12| Added more multicast addresses.
+//  1.5    | mfred    |27-Jul-12| Added multicast addresses for OPCG, etc.
+//  1.3    | gweber   |25-Jul-12| moved centaur constants from p8_scom_addresses.H
+//  1.2    | mfred    |13-Jul-12| Get rid of some temp lines and comments.
+//  1.1    | mfred    |07-Jul-12| Adding first version of scom address file.  Was created from P8 version.
+
 
 #ifndef CEN_SCOM_ADDRESSES
 #define CEN_SCOM_ADDRESSES
@@ -312,69 +336,56 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F,           ULL(0x8001C0140301143F) );
 CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301183F,           ULL(0x8000C0140301183F) );
 CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301183F,           ULL(0x8001C0140301183F) );
- 
- 
+
+//------------------------------------------------------------------------------
+//      CALIBRATION SCOM ADDRESSES (DPHY REGISTERS)
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F,             ULL(0x8000C0160301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F,             ULL(0x8001C0160301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301183F,             ULL(0x8000C0160301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301183F,             ULL(0x8000C0160301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0_0x8000C0170301143F,             ULL(0x8000C0160301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P1_0x8001C0170301143F,             ULL(0x8001C0160301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG1_P0_0x8000C0170301183F,             ULL(0x8000C0160301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG1_P1_0x8001C0170301183F,             ULL(0x8000C0160301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F,              ULL(0x8000C0190301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F,              ULL(0x8001C0190301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301183F,              ULL(0x8000C0190301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301183F,              ULL(0x8001C0190301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F,               ULL(0x8000C0180301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F,               ULL(0x8001C0180301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301183F,               ULL(0x8000C0180301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301183F,               ULL(0x8001C0180301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_MASK_P0_0x8000C01A0301143F,                ULL(0x8000C01A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_MASK_P1_0x8001C01A0301143F,                ULL(0x8001C01A0301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_MASK_P0_0x8000C01A0301183F,                ULL(0x8000C01A0301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_MASK_P1_0x8001C01A0301183F,                ULL(0x8001C01A0301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F,               ULL(0x8000C00B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F,               ULL(0x8001C00B0301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301183F,               ULL(0x8000C00B0301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301183F,               ULL(0x8001C00B0301183F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143F,              ULL(0x8000C00F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143F,              ULL(0x8001C00F0301143F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301183F,              ULL(0x8000C00F0301183F) );
+CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301183F,              ULL(0x8001C00F0301183F) );
+
+
 /******************************************************************************/
 /*********  MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/
 /******************************************************************************/
-CONST_UINT64_T( READ_OR_ALL_FUNC_GP0_0x41000000         , ULL(0x41000000) ); // group1: all except PRV: GP0
-CONST_UINT64_T( READ_OR_ALL_FUNC_GP1_0x41000001         , ULL(0x41000001) ); // group1: all except PRV: GP1
-CONST_UINT64_T( READ_OR_ALL_FUNC_GP2_0x41000002         , ULL(0x41000002) ); // group1: all except PRV: GP2
-CONST_UINT64_T( READ_OR_ALL_FUNC_GP4_0x41000003         , ULL(0x41000003) ); // group1: all except PRV: GP4
-CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL0_0x41030002  , ULL(0x41030002) ); // group1: all except PRV: OPCG_CNTL0
-CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL1_0x41030003  , ULL(0x41030003) ); // group1: all except PRV: OPCG_CNTL1
-CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL2_0x41030004  , ULL(0x41030004) ); // group1: all except PRV: OPCG_CNTL2
-CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL3_0x41030005  , ULL(0x41030005) ); // group1: all except PRV: OPCG_CNTL3
-CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_REGION_0x41030006  , ULL(0x41030006) ); // group1: all except PRV: CLK_REGION
-CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_SCANSEL_0x41030007 , ULL(0x41030007) ); // group1: all except PRV: CLK_SCANSEL
-CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_STATUS_0x41030008  , ULL(0x41030008) ); // group1: all except PRV: CLK_STATUS
-CONST_UINT64_T( READ_OR_ALL_FUNC_GP3_0x410F0012         , ULL(0x410F0012) ); // group1: all except PRV: GP3
-CONST_UINT64_T( READ_OR_ALL_PCB_SLAVE_ERRREG_0x410F001F , ULL(0x410F001F) ); // group1: all except PRV:
-
-CONST_UINT64_T( READ_AND_ALL_FUNC_GP0_0x49000000         , ULL(0x49000000) ); // group1: all except PRV: GP0
-CONST_UINT64_T( READ_AND_ALL_FUNC_GP1_0x49000001         , ULL(0x49000001) ); // group1: all except PRV: GP1
-CONST_UINT64_T( READ_AND_ALL_FUNC_GP2_0x49000002         , ULL(0x49000002) ); // group1: all except PRV: GP2
-CONST_UINT64_T( READ_AND_ALL_FUNC_GP4_0x49000003         , ULL(0x49000003) ); // group1: all except PRV: GP4
-CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL0_0x49030002  , ULL(0x49030002) ); // group1: all except PRV: OPCG_CNTL0
-CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL1_0x49030003  , ULL(0x49030003) ); // group1: all except PRV: OPCG_CNTL1
-CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL2_0x49030004  , ULL(0x49030004) ); // group1: all except PRV: OPCG_CNTL2
-CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL3_0x49030005  , ULL(0x49030005) ); // group1: all except PRV: OPCG_CNTL3
-CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_REGION_0x49030006  , ULL(0x49030006) ); // group1: all except PRV: CLK_REGION
-CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_SCANSEL_0x49030007 , ULL(0x49030007) ); // group1: all except PRV: CLK_SCANSEL
-CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_STATUS_0x49030008  , ULL(0x49030008) ); // group1: all except PRV: CLK_STATUS
-CONST_UINT64_T( READ_AND_ALL_FUNC_GP3_0x490F0012         , ULL(0x490F0012) ); // group1: all except PRV: GP3
-CONST_UINT64_T( READ_AND_ALL_PCB_SLAVE_ERRREG_0x490F001F , ULL(0x490F001F) ); // group1: all except PRV:
-
-CONST_UINT64_T( WRITE_ALL_FUNC_GP0_0x69000000            , ULL(0x69000000) ); // group1: all except PRV: GP0
-CONST_UINT64_T( WRITE_ALL_FUNC_GP1_0x69000001            , ULL(0x69000001) ); // group1: all except PRV: GP1
-CONST_UINT64_T( WRITE_ALL_FUNC_GP2_0x69000002            , ULL(0x69000002) ); // group1: all except PRV: GP2
-CONST_UINT64_T( WRITE_ALL_FUNC_GP4_0x69000003            , ULL(0x69000003) ); // group1: all except PRV: GP4
-CONST_UINT64_T( WRITE_ALL_FUNC_GP0_AND_0x69000004        , ULL(0x69000004) ); // group1: all except PRV: GP0 AND (for clearing bits)
-CONST_UINT64_T( WRITE_ALL_FUNC_GP0_OR_0x69000005         , ULL(0x69000005) ); // group1: all except PRV: GP0 OR  (for setting bits)
-CONST_UINT64_T( WRITE_ALL_FUNC_GP4_AND_0x69000006        , ULL(0x69000006) ); // group1: all except PRV: GP4 AND (for clearing bits)
-CONST_UINT64_T( WRITE_ALL_FUNC_GP4_OR_0x69000007         , ULL(0x69000007) ); // group1: all except PRV: GP4 OR  (for setting bits)
-CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL0_0x69030002     , ULL(0x69030002) ); // group1: all except PRV: OPCG_CNTL0
-CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL1_0x69030003     , ULL(0x69030003) ); // group1: all except PRV: OPCG_CNTL1
-CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL2_0x69030004     , ULL(0x69030004) ); // group1: all except PRV: OPCG_CNTL2
-CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL3_0x69030005     , ULL(0x69030005) ); // group1: all except PRV: OPCG_CNTL3
-CONST_UINT64_T( WRITE_ALL_FUNC_CLK_REGION_0x69030006     , ULL(0x69030006) ); // group1: all except PRV: CLK_REGION
-CONST_UINT64_T( WRITE_ALL_FUNC_CLK_SCANSEL_0x69030007    , ULL(0x69030007) ); // group1: all except PRV: CLK_SCANSEL
-CONST_UINT64_T( WRITE_ALL_FUNC_CLK_STATUS_0x69030008     , ULL(0x69030008) ); // group1: all except PRV: CLK_STATUS
-CONST_UINT64_T( WRITE_ALL_FUNC_GP3_0x690F0012            , ULL(0x690F0012) ); // group1: all except PRV: GP3
-CONST_UINT64_T( WRITE_ALL_FUNC_GP3_AND_0x690F0013        , ULL(0x690F0013) ); // group1: all except PRV: GP3 AND (for clearing bits)
-CONST_UINT64_T( WRITE_ALL_FUNC_GP3_OR_0x690F0014         , ULL(0x690F0014) ); // group1: all except PRV: GP3 OR  (for setting bits)
-CONST_UINT64_T( WRITE_ALL_PCB_SLAVE_ERRREG_0x690F001F    , ULL(0x690F001F) ); // group1: all except PRV:
+// moved to common_scom_addresses.H       1/24/2010   mfred
+
 
 //******************************************************************************/
 //*********  ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/
 //******************************************************************************/
-
-CONST_UINT8_T( READ_OR_ALL_CHIPLETS,              ULL(0x40) );   // group 0: TP, MEM, NEST
-CONST_UINT8_T( READ_OR_ALL_FUNC_CHIPLETS,         ULL(0x41) );   // group 1: MEM, NEST// CONST_UINT8_T( READ_AND_ALL_CHIPLETS,             ULL(0x48) );   // group 0: TP, MEM, NEST
-CONST_UINT8_T( READ_AND_ALL_FUNC_CHIPLETS,        ULL(0x49) );   // group 1: MEM, NEST
-CONST_UINT8_T( WRITE_ALL_CHIPLETS,                ULL(0x68) );   // group 0: TP, MEM, NEST
-CONST_UINT8_T( WRITE_ALL_FUNC_CHIPLETS,           ULL(0x69) );   // group 1: MEM, NEST
-
+// moved to common_scom_addresses.H       1/24/2010   mfred
 
 #endif
 
@@ -385,6 +396,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.15  2012/03/06 16:40:00  divyakum
+Added calibration status regs
+
+Revision 1.14  2012/02/22 22:50:52  divyakum
+Added CALIBRATION registers. Added Change history table.
+
+Revision 1.13  2012/01/24 21:58:33  mfred
+Moved common multicast address constants to common_scom_accresses.H
+
+Revision 1.12  2012/01/24 20:50:01  mfred
+Move multicast group 1 to group 3 for consistency with P8
+
 Revision 1.11  2012/01/06 22:34:45  jmcgill
 move shared/common addresses to common_scom_addresses.H, general cleanup
 
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/fapi_sbe_common.h b/src/usr/hwpf/hwp/include/fapi_sbe_common.h
index 2ad5b7bda..2ad5b7bda 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/fapi_sbe_common.h
+++ b/src/usr/hwpf/hwp/include/fapi_sbe_common.h
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 17b672b30..17b672b30 100755
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H