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| author | Brian Silver <bsilver@us.ibm.com> | 2016-01-19 08:25:33 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-02-22 15:56:25 -0600 |
| commit | 79dda8f853a2bb9e7721249c881de152ffa8665f (patch) | |
| tree | f52cf98b47a512807a6c50dbc9c112480b429475 /src | |
| parent | 2f46abb3479821544b5e082cc74bbec750397c35 (diff) | |
| download | talos-hostboot-79dda8f853a2bb9e7721249c881de152ffa8665f.tar.gz talos-hostboot-79dda8f853a2bb9e7721249c881de152ffa8665f.zip | |
Changes related to model 31, attr changes for sim latencies
Fix bug in ODT write config, using read config values
Turn off WL RTT Swap
Change VBU attribute file to include all sim cal steps
Change-Id: I3dbc4293449d9914b27fc64b66af61540dee346a
Original-Change-Id: I75aa17dcc46cecd120cdcd1847ea7e28b82c4dc8
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23418
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Andre A. Marin <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24602
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H | 2 | ||||
| -rw-r--r-- | src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H index 383d64c2c..a9b21a258 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index 3a1a1a6d0..1021dd8fb 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -47,4 +47,9 @@ REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC , 9 , SH_UN REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WL_SWAP_ENABLE_P0 , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); +REG64_FLD( MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0 , 49 , SH_UNT_MCA , SH_ACS_SCOM_RW , + 0 ); + #endif |
