HB procedure updates

Change-Id: I0aa14b5dc1dc11757c46599d8b7de37e51bf21fc
CQ: SW241338
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8435
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 373 insertions, 122 deletions

diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
index ba886ff14..415346551 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
@@ -20,7 +20,8 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pcbs_init.C,v 1.23 2013/12/16 18:52:09 stillgs Exp $
+
+// $Id: p8_pcbs_init.C,v 1.26 2014/01/29 17:54:51 cswenson Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -310,7 +311,7 @@
 /// OLD-DOC - Restore to Deep Sleep and Deep Winkle upon reset
 /// OLD-DOC - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for
 ///     reset case) SCAN0
-/// OLD-DOC     -For reset case, disable all “global_en” bits in PMCR and PMICR;
+/// OLD-DOC     -For reset case, disable all “global_en” bits in PMCR and PMICR;
 ///                 this keeps Global Pstate Request from occuring to the PMC until
 ///                 it has been initialized.  OCCFW to be do this
 /// OLD-DOC - PMICR default value adjustment (Hardware flush 0 -> restore to 0 for
@@ -392,7 +393,7 @@ CONST_UINT64_T( PMGP0_REG_0x100F0100_scan0                              ,  ULL(0
 CONST_UINT64_T( PMGP1_REG_0x100F0103_scan0                              ,  ULL(0x6C00000000000000) );
 CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106_scan0                   ,  ULL(0x0A00000000000000) );
 CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E_scan0                   ,  ULL(0xFFF0FFF080800000) );     //1000 0000 1000 000
-CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A_scan0                       ,  ULL(0x00000000));
+CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A_scan0                       ,  ULL(0xFFFFFFFFFFE00000));
 CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B_scan0                    ,  ULL(0x00000000));
 CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C_scan0                    ,  ULL(0x00000000));    // This is different than the hardware
 CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D_scan0                   ,  ULL(0x00000000));
@@ -448,10 +449,16 @@ pcbs_init  (  const fapi::Target& i_target);
 fapi::ReturnCode
 pcbs_scan0(const Target &i_target, uint8_t i_ex_number);
 
+// FIR trace function
+fapi::ReturnCode
+glob_fir_trace  (   const fapi::Target& i_target,
+                    const char * i_msg);
+
 // ----------------------------------------------------------------------
 // Function definitions
 // ----------------------------------------------------------------------
 
+
 // ----------------------------------------------------------------------
 /**
  * p8_pcbs_init calls the underlying routine based on mode parameter
@@ -741,7 +748,7 @@ pcbs_init(const Target& i_target)
                                chipHasPcbsErrReset);
             if(rc)
             {
-     		    FAPI_ERR("Error querying Chip EC feature: "
+                FAPI_ERR("Error querying Chip EC feature: "
                          "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET");
                 break;
             }
@@ -806,7 +813,7 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
     const uint32_t              PMGP1_FORCE_SAFE_MODE_BIT = 12;
 
     // PMSR bits
-    const uint32_t              PMSR_PSAFE_MODE_ACTIVE_BIT = 33;
+//    const uint32_t              PMSR_PSAFE_MODE_ACTIVE_BIT = 33;
     const uint32_t              PMSR_ALL_FSMS_IN_SAFE_STATE_BIT = 36;
 
     // PMCR bits
@@ -830,6 +837,10 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
     const uint32_t              IVRMCS_IVRM_CORE_VCS_BYPASS_B_BIT = 6;
     const uint32_t              IVRMCS_IVRM_ECO_VDD_BYPASS_B_BIT = 8;
     const uint32_t              IVRMCS_IVRM_ECO_VCS_BYPASS_B_BIT = 10;
+    
+    // detect PCBS interrupt retry bug HW226980 that is fixed.  This is 
+    // only present only on Murano 1.3.
+    uint8_t                     chipHasPcbIntrFixed = 0;
 
     FAPI_INF("p8_pcbs_init_reset beginning for target %s ...", i_target.toEcmdString());
     do
@@ -845,6 +856,17 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
         }
 
         FAPI_DBG("Chiplet vector size => %u", l_exChiplets.size());
+        
+        // The attribute for the PCBS Reset bug fix applies to the PCB Interrupt
+        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET,
+                               &i_target,
+                               chipHasPcbIntrFixed);
+        if(rc)
+        {
+            FAPI_ERR("Error querying Chip EC feature: "
+                     "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET");
+            break;
+        }
 
         // For each chiplet
         for (uint8_t c=0; c< l_exChiplets.size(); c++)
@@ -860,6 +882,21 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             FAPI_DBG("\tCore number = %d", l_ex_number);
 
             ex_offset = l_ex_number * 0x01000000;
+            
+            address = EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 + ex_offset;
+            GETSCOM(rc, i_target, address, data);
+            uint32_t psafe;
+            e_rc = data.extractToRight(&psafe, 17, 8);
+            E_RC_CHECK(e_rc, rc);
+                       
+            address = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset;
+            GETSCOM(rc, i_target, address, data);
+            uint32_t gactual;
+            e_rc = data.extractToRight(&gactual, 0, 8);
+            E_RC_CHECK(e_rc, rc);
+            
+            FAPI_DBG("\tEX %d - Global Actual: 0x%02X, Psafe: 0x%02X", 
+                            l_ex_number, gactual, psafe);
 
             //  ******************************************************************
             //  Force safe mode if Pstates are enabled.
@@ -874,85 +911,118 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
 
             if (data.isBitSet(PCBSPMMODE_ENABLE_PSTATE_MODE_BIT))  // Pstates enabled
             {
+                // if the part does not have HW226980 fixed, do not try to use the 
+                // hardware to enter safe mode in the PCBS.  BTW:  this function is
+                // somewhat redundant to the PMC Vsafe being successfully invoked as
+                // that establishes the Global Actual PState anyway
+                
+                FAPI_INF("PCBS Interrupt will %sbe performed",
+                     (chipHasPcbIntrFixed ? "" : "NOT "));
+                
+                if (chipHasPcbIntrFixed)
+                {
 
-                FAPI_INF("Pstate enabled - Force safe mode");
+                    FAPI_INF("Pstate enabled - Force safe mode");
 
-                // Using Write OR to just set bit12
-                // Clear buffer
-                e_rc = data.flushTo0();
-                E_RC_CHECK(e_rc, rc);
+                    // Using Write OR to just set bit12
+                    // Clear buffer
+                    e_rc = data.flushTo0();
+                    E_RC_CHECK(e_rc, rc);
 
-                e_rc = data.setBit(PMGP1_FORCE_SAFE_MODE_BIT);  // force_safe_mode = 1
-                E_RC_CHECK(e_rc, rc);
+                    e_rc = data.setBit(PMGP1_FORCE_SAFE_MODE_BIT);  // force_safe_mode = 1
+                    E_RC_CHECK(e_rc, rc);
 
-                address =  EX_PMGP1_OR_0x100F0105 + ex_offset;
-                PUTSCOM(rc, i_target, address, data);
+                    address =  EX_PMGP1_OR_0x100F0105 + ex_offset;
+                    //PUTSCOM(rc, i_target, address, data);
 
-                FAPI_INF("Forced Safe Mode");
 
-                //  ******************************************************************
-                //  psafe Pstate achived AND FSM-stable ?
-                //  ******************************************************************
-                //  ******************************************************************
-                //  - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active
-                //  - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state
-                //  ******************************************************************
-                FAPI_INF("Psafe Pstate and FSM-stable?");
+                    rc = glob_fir_trace (i_target, "after setting force safe mode bit");
+                    if (!rc.ok()) 
+                    {
+                        break;
+                    }
 
-                loopcount = 0;
+                    FAPI_INF("Forced Safe Mode");
 
-                address =  EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + ex_offset;
-                // loop until  (safe_mode_active AND all_fsms_in_safe_state)
-                do
-                {
+                    //  ******************************************************************
+                    //  psafe Pstate achived AND FSM-stable ?
+                    //  ******************************************************************
+                    //  ******************************************************************
+                    //  - PCBS_POWER_MANAGEMENT_STATUS_REG[33] safe_mode_active
+                    //  - PCBS_POWER_MANAGEMENT_STATUS_REG[36] all_fsms_in_safe_state
+                    //  ******************************************************************
+                    FAPI_INF("Psafe Pstate and FSM-stable?");
 
-                    // Read PMSR
-                    GETSCOM(rc, i_target, address, data);
+                    loopcount = 0;
 
-                    FAPI_DBG("\t loopcount => %d ",loopcount  );
-                    // OR timeout .... set to 20 loops
-                    if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS )
+                    address =  EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 + ex_offset;
+                    // loop until  (safe_mode_active AND all_fsms_in_safe_state)
+                    do
                     {
-                        FAPI_ERR("Gave up waiting for Psafe Pstate and FSM-stable!" );
-                        const fapi::Target& PROC_CHIP = i_target;
-                        const uint64_t& LOOPCOUNT = (uint32_t)loopcount;
-                        const uint64_t& PMSR = data.getDoubleWord(0);
-                        
-                        address =  EX_PCBS_FSM_MONITOR1_REG_0x100F0170 + ex_offset;
-                        GETSCOM(rc, i_target, address, data);
-                        const uint64_t& PCBSPM_MON1 = data.getDoubleWord(0);
-                        
-                        address =  EX_PCBS_FSM_MONITOR2_REG_0x100F0171 + ex_offset;
-                        GETSCOM(rc, i_target, address, data);
-                        const uint64_t& PCBSPM_MON2 = data.getDoubleWord(0);                        
-                        
-                        FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT);
-                        break;
-                    }
 
-                    FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content :  %016llX",
-                                    data.getDoubleWord(0));
-
-                    FAPI_DBG("Is Psafe Pstate and FSM-stable ? ");
-                    FAPI_DBG("\t Wait DELAY: %d  ", pcbs_val_init.MAX_DELAY);
-                    FAPI_DBG("\t Wait SimCycles: %d  ", pcbs_val_init.MAX_SIM_CYCLES);
+                        // Read PMSR
+                        GETSCOM(rc, i_target, address, data);
 
-                    rc =  fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES);
-                    if (rc)
+                        FAPI_DBG("\t loopcount => %d ",loopcount  );
+                        // OR timeout .... set to 20 loops
+                        if( ++loopcount > pcbs_val_init.MAX_PSAFE_FSM_LOOPS )
+                        {
+                            FAPI_ERR("Gave up waiting for Psafe Pstate and FSM-stable!" );
+                            const fapi::Target& PROC_CHIP = i_target;
+                            const uint64_t& LOOPCOUNT = (uint32_t)loopcount;
+                            const uint64_t& PMSR = data.getDoubleWord(0);
+
+                            address =  EX_PCBS_FSM_MONITOR1_REG_0x100F0170 + ex_offset;
+                            GETSCOM(rc, i_target, address, data);
+                            const uint64_t& PCBSPM_MON1 = data.getDoubleWord(0);
+
+                            address =  EX_PCBS_FSM_MONITOR2_REG_0x100F0171 + ex_offset;
+                            GETSCOM(rc, i_target, address, data);
+                            const uint64_t& PCBSPM_MON2 = data.getDoubleWord(0);                        
+
+                            FAPI_SET_HWP_ERROR(rc, RC_PROC_PCBS_CODE_SAFE_FSM_TIMEOUT);
+                            break;
+                        }
+
+                        FAPI_DBG("Read of PCBS_POWER_MANAGEMENT_STATUS_REG_0x1*0F0153 content :  %016llX",
+                                        data.getDoubleWord(0));
+
+                        FAPI_DBG("Is Psafe Pstate and FSM-stable ? ");
+                        FAPI_DBG("\t Wait DELAY: %d  ", pcbs_val_init.MAX_DELAY);
+                        FAPI_DBG("\t Wait SimCycles: %d  ", pcbs_val_init.MAX_SIM_CYCLES);
+
+                        rc =  fapiDelay(pcbs_val_init.MAX_DELAY, pcbs_val_init.MAX_SIM_CYCLES);
+                        if (rc)
+                        {
+                            FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc);
+                            break;
+                        }
+
+                    //} while ( data.isBitClear(PMSR_PSAFE_MODE_ACTIVE_BIT) ||
+                    //          data.isBitClear(PMSR_ALL_FSMS_IN_SAFE_STATE_BIT));
+                    } while ( data.isBitClear(PMSR_ALL_FSMS_IN_SAFE_STATE_BIT));
+                    // if error, break the outer loop
+                    if (!rc.ok())
                     {
-                        FAPI_ERR("fapiDelay(MAX_DELAY, MAX_SIM_CYCLES) failed. With rc = 0x%x", (uint32_t)rc);
                         break;
                     }
 
-                } while ( data.isBitClear(PMSR_PSAFE_MODE_ACTIVE_BIT) ||
-                          data.isBitClear(PMSR_ALL_FSMS_IN_SAFE_STATE_BIT));
-                // if error, break the outer loop
-                if (!rc.ok())
+                    FAPI_INF("Psafe Pstate and FSM-stable is reached ...");
+                } // PCBS Interrupt
+                else
                 {
-                    break;
+                    FAPI_INF("PCBS safe mode not used");
                 }
+            } // Pstates enabled
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
 
-                FAPI_INF("Psafe Pstate and FSM-stable is reached ...");
+            rc = glob_fir_trace (i_target, "after force safe mode poll");
+            if (!rc.ok()) 
+            {
+                break;
             }
 
             //  ******************************************************************
@@ -986,6 +1056,15 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             E_RC_CHECK(e_rc, rc);
 
             PUTSCOM(rc, i_target, address, data);
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after FREQ_CTRL_REG");
+            if (!rc.ok()) 
+            {
+                break;
+            } 
 
             // Lock the DPLL in via the override mode.  Note:  this DOES
             // allow for continued CPM enablement
@@ -995,6 +1074,15 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
 
             address = EX_PMGP1_OR_0x100F0105 + ex_offset;
             PUTSCOM(rc, i_target, address, data);
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after hold DPLL");
+            if (!rc.ok()) 
+            {
+                break;
+            }  
 
             //  ******************************************************************
             //  - Disable Pstate mode
@@ -1011,6 +1099,15 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             E_RC_CHECK(e_rc, rc);
 
             PUTSCOM(rc, i_target, address, data );
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after disable Pstates");
+            if (!rc.ok()) 
+            {
+                break;
+            }  
 
             FAPI_INF("Disabled Pstate mode");
 
@@ -1100,7 +1197,16 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             PUTSCOM(rc, i_target, address, data);
 
             FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " );
-
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after RESCLK");
+            if (!rc.ok()) 
+            {
+                break;
+            }  
+            
             //  ******************************************************************
             //  Disable OCC Heartbeat
             //  ******************************************************************
@@ -1147,6 +1253,15 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
 
                 FAPI_INF ("iVRMs disabled and in bypass-mode" );
             }
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after IVRM Disable");
+            if (!rc.ok()) 
+            {
+                break;
+            }  
 
             //  ******************************************************************
             //  Disable undervolting
@@ -1194,6 +1309,16 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
                 FAPI_ERR(" pcbs_scan0 failed. With rc = 0x%x", (uint32_t)rc);
                 break;
             }
+            
+            //  ******************************************************************
+            //  Check for xstops and recoverables
+            //  ******************************************************************
+            rc = glob_fir_trace (i_target, "after SCAN0");
+            if (!rc.ok()) 
+            {
+                break;
+            }  
+
 
         } // Chiplet loop
     } while(0);
@@ -1263,11 +1388,21 @@ pcbs_scan0(const Target &i_target, uint8_t i_ex_number)
         address =  EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + ex_offset;
         reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0;
         SETDWSCAN0(i_target, address, data, reset_doubleword );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PMErrMask_REG_0x100F010A + ex_offset;
-        reset_word = EX_PMErrMask_REG_0x100F010A_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
+        GETSCOM(rc, i_target, address, data);
+        FAPI_DBG("EX_PMErrMask_REG_0x100F010A value = 0x%016llX", data.getDoubleWord(0));
+        
+        reset_doubleword = EX_PMErrMask_REG_0x100F010A_scan0;
+        SETDWSCAN0(i_target, address, data, reset_doubleword );
+
+        rc = glob_fir_trace (i_target, "after scan0 EX_PMErrMask_REG_0x100F010A");
+        if (!rc.ok()) { break; }  
+
 
         // OCC does not mess with the PFET delays so these are left in tact.
 
@@ -1275,51 +1410,145 @@ pcbs_scan0(const Target &i_target, uint8_t i_ex_number)
         address =  EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset;
         reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Control_Status_Reg_0x100F0154");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + ex_offset;
         reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset;
         reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_PMC_VF_CTRL_REG_0x100F015A");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + ex_offset;
         reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + ex_offset;
         reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162  + ex_offset;
         reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + ex_offset;
         reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163");
+        if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + ex_offset;
         reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0;
         SETSCAN0(i_target, address, data, reset_word );
+        
+        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166");
+        if (!rc.ok()) { break; }  
+     
+    } while(0);
+    return rc;
+}
 
-        /// \todo  Regcheck error check at latest model
-        // address =  EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168
-        //          + ex_offset;
-        // reset_word = EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168_scan0;
-        // SETSCAN0(i_target, address, data, reset_word );
+
+//------------------------------------------------------------------------------
+/**
+ * Trace a set of FIRs (Globals and select Locals)
+ *
+ * @param[in] i_target Chip target
+ * @param[in] i_msg    String to put out in the trace
+ *
+ * @retval ECMD_SUCCESS
+ * @retval ERROR defined in xml
+ */
+fapi::ReturnCode
+glob_fir_trace  (   const fapi::Target& i_target,
+                    const char * i_msg)
+{
+    fapi::ReturnCode                rc;
+    ecmdDataBufferBase              data(64);
+    uint64_t                        address;
+    
+    CONST_UINT64_T( GLOB_XSTOP_FIR_0x01040000                                 , ULL(0x01040000) );
+    CONST_UINT64_T( GLOB_RECOV_FIR_0x01040001                                 , ULL(0x01040001) );
+    CONST_UINT64_T( TP_LFIR_0x0104000A                                        , ULL(0x0104000A) );
+
+    do
+    {
+        //  ******************************************************************
+        //  Check for xstops and recoverables and put in the trace
+        //  ******************************************************************
+        address =  READ_GLOBAL_XSTOP_FIR_0x570F001B;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Xstop is **ACTIVE** %s", i_msg);
+        }           
+
+        address =  READ_GLOBAL_RECOV_FIR_0x570F001C;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg);
+        }
+
+        address =  READ_GLOBAL_RECOV_FIR_0x570F001C;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg);
+        }
+
+        address =  GLOB_XSTOP_FIR_0x01040000;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Glob Xstop FIR is **ACTIVE** %s", i_msg);
+        }
+
+        address =  GLOB_RECOV_FIR_0x01040001;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Glob Recov FIR is **ACTIVE** %s", i_msg);
+        }
+
+        address =  TP_LFIR_0x0104000A;
+        GETSCOM(rc, i_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("TP LFIR is **ACTIVE** %s", i_msg);
+        }
+                        
     } while(0);
     return rc;
 }
 
+
 } //end extern C
 
 /*
@@ -1328,6 +1557,24 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_pcbs_init.C,v $
+Revision 1.26  2014/01/29 17:54:51  cswenson
+changed char* to const char* in glob_fir_trace()
+
+Revision 1.25  2014/01/22 20:58:31  stillgs
+
+For SW238575, added an EC attribute check of an existing attribute to skip the forcing
+of PCBS Safe mode for Murano 1.x parts as these parts have a lost PCB interrupt issue
+(HW226980) that cannot be easily work-around in all cases.  For the case of the timeout
+in SW238575, the forcing is not necessary as the invocation of Pvsafe before this is
+sufficient.
+
+Revision 1.24  2014/01/13 21:15:37  stillgs
+
+- Fixed PMErrMask to properly default to "masked" vs "unmasked" to deal with
+PLL error upon OCC restart (SW237068)
+- Added passive global xstop and recoverable FIR tracing to aid in future
+debug.  Did not put these as specific checks -> FFDC at this time.
+
 Revision 1.23  2013/12/16 18:52:09  stillgs
 
 Added additional FFDC for SAFE FSM TIME check to add hardware FSM monitor
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C
index 2d5483c53..3a5a131f1 100755
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm_pmc_firinit.C,v 1.15 2013/08/26 12:44:38 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $
+
+// $Id: p8_pm_pmc_firinit.C,v 1.16 2014/01/14 17:13:31 stillgs Exp $
+// $Source: /archive/shadow/ekb/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -123,7 +124,7 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode  )
             rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask );
             if (rc)
             {
-	            FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed.");
+                FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed.");
                 break;
             }
         }
@@ -134,7 +135,7 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode  )
             rc = fapiGetScom(i_target, PMC_LFIR_MASK_0x01010843, mask );
             if (rc)
             {
-	            FAPI_ERR("fapiGetScom(PMC_LFIR_MASK_0x01010843) failed.");
+                FAPI_ERR("fapiGetScom(PMC_LFIR_MASK_0x01010843) failed.");
                 break;
             }
                                            
@@ -156,7 +157,7 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode  )
             rc = fapiPutScom(i_target, PMC_LFIR_MASK_0x01010843, mask );
             if (rc)
             {
-	            FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed.");
+                FAPI_ERR("fapiPutScom(PMC_LFIR_MASK_0x01010843) failed.");
                 break;
             }
         }
@@ -172,45 +173,46 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode  )
                 break;
             }
 
-            SET_RECOV_INTR(PSTATE_OCI_MASTER_RDERR                 ); // pstate_oci_master_rderr
-            SET_RECOV_INTR(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR     ); // pstate_oci_master_rddata_parity_err
-            SET_RECOV_INTR(PSTATE_GPST_CHECKBYTE_ERR               ); // pstate_gpst_checkbyte_err
-            SET_RECOV_INTR(PSTATE_GACK_TO_ERR                      ); // pstate_gack_to_err
-            SET_RECOV_INTR(PSTATE_PIB_MASTER_NONOFFLINE_ERR        ); // pstate_pib_master_nonoffline_err
-            SET_RECOV_INTR(PSTATE_PIB_MASTER_OFFLINE_ERR           ); // pstate_pib_master_offline_err
-            SET_RECOV_INTR(PSTATE_OCI_MASTER_TO_ERR                ); // pstate_oci_master_to_err
-            SET_RECOV_INTR(PSTATE_INTERCHIP_UE_ERR                 ); // pstate_interchip_ue_err
-            SET_RECOV_INTR(PSTATE_INTERCHIP_ERRORFRAME_ERR         ); // pstate_interchip_errorframe_err
-            SET_RECOV_INTR(PSTATE_MS_FSM_ERR                       ); // pstate_ms_fsm_err
-            SET_MALF_ALERT(MS_COMP_PARITY_ERR                      ); // ms_comp_parity_err
-            SET_MALF_ALERT(IDLE_PORESW_FATAL_ERR                   ); // idle_poresw_fatal_err
-            SET_MALF_ALERT(IDLE_PORESW_STATUS_RC_ERR               ); // idle_poresw_status_rc_err
-            SET_MALF_ALERT(IDLE_PORESW_STATUS_VALUE_ERR            ); // idle_poresw_status_value_err
-            SET_MALF_ALERT(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR    ); // idle_poresw_write_while_inactive_err
-            SET_MALF_ALERT(IDLE_PORESW_TIMEOUT_ERR                 ); // idle_poresw_timeout_err
-            SET_FIR_MASKED(IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR       ); // idle_oci_master_write_timeout_err
-            SET_MALF_ALERT(IDLE_INTERNAL_ERR                       ); // idle_internal_err
-            SET_MALF_ALERT(INT_COMP_PARITY_ERR                     ); // int_comp_parity_err
-            SET_FIR_MASKED(PMC_OCC_HEARTBEAT_TIMEOUT               ); // pmc_occ_heartbeat_timeout
-            SET_FIR_MASKED(SPIVID_CRC_ERROR0                       ); // spivid_crc_error0
-            SET_FIR_MASKED(SPIVID_CRC_ERROR1                       ); // spivid_crc_error1
-            SET_FIR_MASKED(SPIVID_CRC_ERROR2                       ); // spivid_crc_error2
-            SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT                    ); // spivid_retry_timeout
-            SET_FIR_MASKED(SPIVID_FSM_ERR                          ); // spivid_fsm_err
-            SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY     ); // spivid_majority_detected_a_minority
-            SET_FIR_MASKED(O2S_CRC_ERROR0                          ); // o2s_crc_error0
-            SET_FIR_MASKED(O2S_CRC_ERROR1                          ); // o2s_crc_error1
-            SET_FIR_MASKED(O2S_CRC_ERROR2                          ); // o2s_crc_error2
-            SET_FIR_MASKED(O2S_RETRY_TIMEOUT                       ); // o2s_retry_timeout
-            SET_FIR_MASKED(O2S_WRITE_WHILE_BRIDGE_BUSY_ERR         ); // o2s_write_while_bridge_busy_err
-            SET_FIR_MASKED(O2S_FSM_ERR                             ); // o2s_fsm_err
-            SET_FIR_MASKED(O2S_MAJORITY_DETECTED_A_MINORITY        ); // o2s_majority_detected_a_minority
-            SET_FIR_MASKED(O2P_WRITE_WHILE_BRIDGE_BUSY_ERR         ); // o2p_write_while_bridge_busy_err
-            SET_FIR_MASKED(O2P_FSM_ERR                             ); // o2p_fsm_err
-            SET_FIR_MASKED(OCI_SLAVE_ERR                           ); // oci_slave_err
-            SET_MALF_ALERT(IF_COMP_PARITY_ERR                      ); // if_comp_parity_err 37:46   spare_fir
-            SET_RECOV_ATTN(FIR_PARITY_ERR_DUP                      ); // fir_parity_err_dup
-            SET_RECOV_ATTN(FIR_PARITY_ERR                          ); // fir_parity_err
+            SET_RECOV_INTR(PSTATE_OCI_MASTER_RDERR              ); //  0  pstate_oci_master_rderr
+            SET_RECOV_INTR(PSTATE_OCI_MASTER_RDDATA_PARITY_ERR  ); //  1  pstate_oci_master_rddata_parity_err
+            SET_RECOV_INTR(PSTATE_GPST_CHECKBYTE_ERR            ); //  2  pstate_gpst_checkbyte_err
+            SET_RECOV_INTR(PSTATE_GACK_TO_ERR                   ); //  3  pstate_gack_to_err
+            SET_RECOV_INTR(PSTATE_PIB_MASTER_NONOFFLINE_ERR     ); //  4  pstate_pib_master_nonoffline_err
+            SET_RECOV_INTR(PSTATE_PIB_MASTER_OFFLINE_ERR        ); //  5  pstate_pib_master_offline_err
+            SET_RECOV_INTR(PSTATE_OCI_MASTER_TO_ERR             ); //  6  pstate_oci_master_to_err
+            SET_RECOV_INTR(PSTATE_INTERCHIP_UE_ERR              ); //  7  pstate_interchip_ue_err
+            SET_RECOV_INTR(PSTATE_INTERCHIP_ERRORFRAME_ERR      ); //  8  pstate_interchip_errorframe_err
+            SET_RECOV_INTR(PSTATE_MS_FSM_ERR                    ); //  9  pstate_ms_fsm_err
+            SET_MALF_ALERT(MS_COMP_PARITY_ERR                   ); // 10  ms_comp_parity_err
+            SET_MALF_ALERT(IDLE_PORESW_FATAL_ERR                ); // 11  idle_poresw_fatal_err
+            SET_MALF_ALERT(IDLE_PORESW_STATUS_RC_ERR            ); // 12  idle_poresw_status_rc_err
+            SET_MALF_ALERT(IDLE_PORESW_STATUS_VALUE_ERR         ); // 13  idle_poresw_status_value_err
+            SET_MALF_ALERT(IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR ); // 14  idle_poresw_write_while_inactive_err
+            SET_MALF_ALERT(IDLE_PORESW_TIMEOUT_ERR              ); // 15  idle_poresw_timeout_err
+            SET_FIR_MASKED(IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR    ); // 16  idle_oci_master_write_timeout_err
+            SET_MALF_ALERT(IDLE_INTERNAL_ERR                    ); // 17  idle_internal_err
+            SET_MALF_ALERT(INT_COMP_PARITY_ERR                  ); // 18  int_comp_parity_err
+            SET_FIR_MASKED(PMC_OCC_HEARTBEAT_TIMEOUT            ); // 19  pmc_occ_heartbeat_timeout
+            SET_FIR_MASKED(SPIVID_CRC_ERROR0                    ); // 20  spivid_crc_error0
+            SET_FIR_MASKED(SPIVID_CRC_ERROR1                    ); // 21  spivid_crc_error1
+            SET_FIR_MASKED(SPIVID_CRC_ERROR2                    ); // 22  spivid_crc_error2
+            SET_FIR_MASKED(SPIVID_RETRY_TIMEOUT                 ); // 23  spivid_retry_timeout
+            SET_FIR_MASKED(SPIVID_FSM_ERR                       ); // 24  spivid_fsm_err
+            SET_FIR_MASKED(SPIVID_MAJORITY_DETECTED_A_MINORITY  ); // 25  spivid_majority_detected_a_minority
+            SET_FIR_MASKED(O2S_CRC_ERROR0                       ); // 26  o2s_crc_error0
+            SET_FIR_MASKED(O2S_CRC_ERROR1                       ); // 27  o2s_crc_error1
+            SET_FIR_MASKED(O2S_CRC_ERROR2                       ); // 28  o2s_crc_error2
+            SET_FIR_MASKED(O2S_RETRY_TIMEOUT                    ); // 29  o2s_retry_timeout
+            SET_FIR_MASKED(O2S_WRITE_WHILE_BRIDGE_BUSY_ERR      ); // 30  o2s_write_while_bridge_busy_err
+            SET_FIR_MASKED(O2S_FSM_ERR                          ); // 31  o2s_fsm_err
+            SET_FIR_MASKED(O2S_MAJORITY_DETECTED_A_MINORITY     ); // 32  o2s_majority_detected_a_minority
+            SET_FIR_MASKED(O2P_WRITE_WHILE_BRIDGE_BUSY_ERR      ); // 33  o2p_write_while_bridge_busy_err
+            SET_FIR_MASKED(O2P_FSM_ERR                          ); // 34  o2p_fsm_err
+            SET_FIR_MASKED(OCI_SLAVE_ERR                        ); // 35  oci_slave_err
+            SET_MALF_ALERT(IF_COMP_PARITY_ERR                   ); // 36  if_comp_parity_err
+            SET_RECOV_INTR(IDLE_RECOVERY_NOTIFY_PRD             ); // 37  idle_recovery_notify_prd
+            SET_FIR_MASKED(FIR_PARITY_ERR_DUP                   ); // 47  fir_parity_err_dup
+            SET_FIR_MASKED(FIR_PARITY_ERR                       ); // 48  fir_parity_err
 
             if (e_rc)
             {
@@ -272,4 +274,4 @@ p8_pm_pmc_firinit(const fapi::Target& i_target , uint32_t mode  )
 } // Procedure
 
 
-} //end extern C
+} //end extern C
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H
index 67eafb6f1..ab4e8587c 100755
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_pmc_firinit.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,8 +20,9 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm_pmc_firinit.H,v 1.6 2013/08/26 12:44:39 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.H,v $
+
+// $Id: p8_pm_pmc_firinit.H,v 1.7 2014/01/14 17:13:34 stillgs Exp $
+// $Source: /archive/shadow/ekb/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_pmc_firinit.H,v $
 //------------------------------------------------------------------------------
 // *|
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -87,6 +88,7 @@ enum PMC_FIRS
     O2P_FSM_ERR                                 = 34,
     OCI_SLAVE_ERR                               = 35,
     IF_COMP_PARITY_ERR                          = 36,
+    IDLE_RECOVERY_NOTIFY_PRD                    = 37,
     FIR_PARITY_ERR_DUP                          = 47,
     FIR_PARITY_ERR                              = 48
 };
@@ -113,4 +115,4 @@ p8_pm_pmc_firinit(const fapi::Target& i_target, uint32_t mode );
 
 } // extern "C"
 
-#endif // _P8_PM_PMC_FIRINIT_H_
+#endif // _P8_PM_PMC_FIRINIT_H_
\ No newline at end of file