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| author | Ben Gass <bgass@us.ibm.com> | 2018-08-31 12:42:39 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-10-18 11:13:33 -0500 |
| commit | 7504dc6275e7da30b0ce064b2af983457950aca7 (patch) | |
| tree | f63852ca87b66989329431128d1191a6437b509e /src | |
| parent | e5eb14043e5dee87618875f178c5af0c90f5166a (diff) | |
| download | talos-hostboot-7504dc6275e7da30b0ce064b2af983457950aca7.tar.gz talos-hostboot-7504dc6275e7da30b0ce064b2af983457950aca7.zip | |
Adding p9a_get/put_mmio and explorer_inband
p9a_get/put_mmio implements getMMIO and putMMIO via
the ADU.
explorer_inband implements functions to access MSCC
MMIO registers, MSCC RAM space for commands and
responses, and IBM scom registers via inband/mmio
to Explorer.
Change-Id: I7b0213b1cb426b10f2902e06373295986e01cd9b
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65569
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66608
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
17 files changed, 1869 insertions, 3 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C new file mode 100644 index 000000000..9a0c3ee00 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C @@ -0,0 +1,476 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file exp_inband.C +/// @brief implement OpenCAPI config, scom, and MSCC MMIO operations. +// +// *HWP HWP Owner: bgass@us.ibm.com +// *HWP FW Owner: dcrowell@us.ibm.com +// *HWP Team: +// *HWP Level: 2 +// *HWP Consumed by: HB + +#include <exp_inband.H> +#include <lib/omi/crc32.H> +#include <lib/shared/exp_consts.H> + +#include <mmio_access.H> +#include <generic/memory/lib/utils/c_str.H> + +namespace mss +{ + +namespace exp +{ + +namespace ib +{ + +//-------------------------------------------------------------------------------- +// Write operations +//-------------------------------------------------------------------------------- + +/// @brief Writes 64 bits of data to MMIO space to the selected Explorer +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_addr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putMMIO64( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + const fapi2::buffer<uint64_t>& i_data ) +{ + uint64_t l_v = static_cast<uint64_t>(i_data); + std::vector<uint8_t> l_wd; + forceLE(l_v, l_wd); + return fapi2::putMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 8, l_wd); +} + + + + +/// @brief Writes 32 bits of data to MMIO space to the selected Explorer +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_addr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putMMIO32( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + const fapi2::buffer<uint32_t>& i_data ) +{ + uint32_t l_v = static_cast<uint32_t>(i_data); + std::vector<uint8_t> l_wd; + forceLE(l_v, l_wd); + return fapi2::putMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 4, l_wd); +} + + + + +/// @brief Writes 64 bits of data to SCOM MMIO space +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_scomAddr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putScom( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_scomAddr, + const fapi2::buffer<uint64_t>& i_data) +{ + // Converts from the scom address to the MMIO address by shifting left by 3 bits + uint64_t l_scomAddr = i_scomAddr << 3; + return putMMIO64(i_target, l_scomAddr, i_data); +} + + + + +/// @brief Writes 32 bits of data to OpenCAPI config space +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_cfgAddr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putOCCfg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_cfgAddr, + const fapi2::buffer<uint32_t>& i_data) +{ + uint32_t l_v = static_cast<uint32_t>(i_data); + std::vector<uint8_t> l_wd; + forceLE(l_v, l_wd); + return fapi2::putMMIO(i_target, i_cfgAddr, 4, l_wd); +} + + + + +/// +/// @brief Converts user_input_msdg to little endian +/// @param[in] i_input user_input_msdg structure to convert +/// @return vector of little endian data +/// +std::vector<uint8_t> user_input_msdg_to_little_endian(const user_input_msdg& i_input) +{ + std::vector<uint8_t> l_data; + forceLE(i_input.DimmType, l_data); + forceLE(i_input.CsPresent, l_data); + forceLE(i_input.DramDataWidth, l_data); + forceLE(i_input.Height3DS, l_data); + forceLE(i_input.ActiveDBYTE, l_data); + forceLE(i_input.ActiveNibble, l_data); + forceLE(i_input.AddrMirror, l_data); + forceLE(i_input.ColumnAddrWidth, l_data); + forceLE(i_input.RowAddrWidth, l_data); + forceLE(i_input.SpdCLSupported, l_data); + forceLE(i_input.SpdtAAmin, l_data); + forceLE(i_input.Rank4Mode, l_data); + forceLE(i_input.DDPCompatible, l_data); + forceLE(i_input.TSV8HSupport, l_data); + forceLE(i_input.MRAMSupport, l_data); + forceLE(i_input.NumPStates, l_data); + forceLEArray(i_input.Frequency, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.PhyOdtImpedance, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.PhyDrvImpedancePU, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.PhyDrvImpedancePD, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.PhySlewRate, MSDG_MAX_PSTATE, l_data); + forceLE(i_input.ATxImpedance, l_data); + forceLE(i_input.ATxSlewRate, l_data); + forceLE(i_input.CKTxImpedance, l_data); + forceLE(i_input.CKTxSlewRate, l_data); + forceLE(i_input.AlertOdtImpedance, l_data); + forceLEArray(i_input.DramRttNomR0, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttNomR1, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttNomR2, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttNomR3, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttWrR0, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttWrR1, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttWrR2, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttWrR3, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttParkR0, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttParkR1, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttParkR2, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramRttParkR3, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramDic, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramWritePreamble, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.DramReadPreamble, MSDG_MAX_PSTATE, l_data); + forceLE(i_input.PhyEqualization, l_data); + forceLEArray(i_input.InitVrefDQ, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.InitPhyVref, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.OdtWrMapCs, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.OdtRdMapCs, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.Geardown, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.CALatencyAdder, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.BistCALMode, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.BistCAParityLatency, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.RcdDic, MSDG_MAX_PSTATE, l_data); + forceLEArray(i_input.RcdVoltageCtrl, MSDG_MAX_PSTATE, l_data); + forceLE(i_input.RcdIBTCtrl, l_data); + forceLE(i_input.RcdDBDic, l_data); + forceLE(i_input.RcdSlewRate, l_data); + forceLE(i_input.EmulationSupport, l_data); + return l_data; +} + +/// @brief Writes user_input_msdg to the data buffer +/// +/// @param[in] i_target The Explorer chip to issue the command to +/// @param[in] i_data The user_input_msdg data to write +/// @param[out] o_crc The calculated crc of the data. +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putUserInputMsdg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_input_msdg& i_data, + uint32_t& o_crc) +{ + const auto l_data = user_input_msdg_to_little_endian(i_data); + o_crc = crc32_gen(l_data); + + return fapi2::putMMIO(i_target, EXPLR_IB_DATA_ADDR, 8, l_data); +} + + + +/// +/// @brief Converts host_fw_command_struct to little endian +/// @param[in] i_input user_input_msdg structure to convert +/// @return vector of little endian data +/// +std::vector<uint8_t> host_fw_command_struct_to_little_endian(const host_fw_command_struct& i_input) +{ + std::vector<uint8_t> l_data; + + forceLE(i_input.cmd_id, l_data); + forceLE(i_input.cmd_flags, l_data); + forceLE(i_input.request_identifier, l_data); + forceLE(i_input.cmd_length, l_data); + forceLE(i_input.cmd_crc, l_data); + forceLE(i_input.host_work_area, l_data); + forceLE(i_input.cmd_work_area, l_data); + forceLEArray(i_input.padding, PADDING_SIZE, l_data); + forceLEArray(i_input.command_argument, ARGUMENT_SIZE, l_data); + + // Generates and adds on the CRC + const uint32_t l_cmd_header_crc = crc32_gen(l_data); + FAPI_DBG("Command header crc: %xl", l_cmd_header_crc); + forceLE(l_cmd_header_crc, l_data); + + return l_data; +} + +/// @brief Writes a command to the command buffer and issues interrupt +/// +/// @param[in] i_target The Explorer chip to issue the command to +/// @param[in] i_cmd The command structure to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putCMD( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_command_struct& i_cmd) +{ + const auto l_data = host_fw_command_struct_to_little_endian(i_cmd); + fapi2::buffer<uint64_t> l_scom; + + // Clear the doorbell + l_scom.setBit<EXPLR_MMIO_MDBELLC_MDBELL_MDBELL>(); + FAPI_TRY(mss::exp::ib::putScom(i_target, EXPLR_MMIO_MDBELLC, l_scom)); + + // Set the command + FAPI_TRY(fapi2::putMMIO(i_target, EXPLR_IB_CMD_ADDR, 8, l_data)) + + // Ring the doorbell - aka the bit that interrupts the microchip FW and tells it to do the thing + l_scom.flush<0>(); + l_scom.setBit<EXPLR_MMIO_MDBELL_MDBELL>(); + FAPI_TRY(mss::exp::ib::putScom(i_target, EXPLR_MMIO_MDBELL, l_scom)); + +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + + + +//-------------------------------------------------------------------------------- +// Read operations +//-------------------------------------------------------------------------------- + +/// @brief Reads 64 bits of data from MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_addr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getMMIO64( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + fapi2::buffer<uint64_t>& o_data) +{ + uint64_t l_rd = 0; + std::vector<uint8_t> l_data(8); + uint32_t l_idx = 0; + FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 8, l_data)); + readLE(l_data, l_idx, l_rd); + o_data = l_rd; +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + + + + +/// @brief Reads 32 bits of data from MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_addr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getMMIO32( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + fapi2::buffer<uint32_t>& o_data) +{ + uint32_t l_rd = 0; + std::vector<uint8_t> l_data(4); + uint32_t l_idx = 0; + FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 4, l_data)); + readLE(l_data, l_idx, l_rd); + o_data = l_rd; +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + + + + +/// @brief Reads 64 bits of data from SCOM MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_scomAddr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getScom( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_scomAddr, + fapi2::buffer<uint64_t>& o_data) +{ + // Converts from the scom address to the MMIO address by shifting left by 3 bits + uint64_t l_scomAddr = i_scomAddr << 3; + return getMMIO64(i_target, l_scomAddr, o_data); +} + + + + +/// @brief Reads 32 bits of data from OpenCAPI config space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_cfgAddr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getOCCfg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_cfgAddr, + fapi2::buffer<uint32_t>& o_data) +{ + uint32_t l_rd = 0; + std::vector<uint8_t> l_data(4); + uint32_t l_idx = 0; + FAPI_TRY(fapi2::getMMIO(i_target, i_cfgAddr, 4, l_data)); + readLE(l_data, l_idx, l_rd); + o_data = l_rd; +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + + + +/// +/// @brief Converts a little endian data array to a host_fw_response_struct +/// @param[in] i_data little endian data to process +/// @param[out] o_crc computed CRC +/// @param[out] o_response response structure +/// @return true if success false if failure +/// @note helper function - returning a bool and will have true FFDC in a separate function +/// +bool host_fw_response_struct_from_little_endian(const std::vector<uint8_t>& i_data, + uint32_t& o_crc, + host_fw_response_struct& o_response) +{ + uint32_t l_idx = 0; + bool l_rc = readLE(i_data, l_idx, o_response.response_id); + l_rc &= readLE(i_data, l_idx, o_response.response_flags); + l_rc &= readLE(i_data, l_idx, o_response.request_identifier); + l_rc &= readLE(i_data, l_idx, o_response.response_length); + l_rc &= readLE(i_data, l_idx, o_response.response_crc); + l_rc &= readLE(i_data, l_idx, o_response.host_work_area); + + l_rc &= readLEArray(i_data, PADDING_SIZE, l_idx, o_response.padding); + l_rc &= readLEArray(i_data, ARGUMENT_SIZE, l_idx, o_response.response_argument); + + o_crc = crc32_gen(i_data, l_idx); + l_rc &= readLE(i_data, l_idx, o_response.response_header_crc); + + return l_rc; +} + +/// +/// @brief Converts a little endian data array to a host_fw_response_struct +/// @param[in] i_target OCMB target on which to operate +/// @param[in] i_data little endian data to process +/// @param[out] o_response response structure +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// @note helper function to allow for checking FFDC +/// +fapi2::ReturnCode host_fw_response_struct_from_little_endian(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target, + const std::vector<uint8_t>& i_data, + host_fw_response_struct& o_response) +{ + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + uint32_t l_crc = 0; + FAPI_ASSERT( host_fw_response_struct_from_little_endian(i_data, + l_crc, + o_response), + fapi2::EXP_INBAND_LE_DATA_RANGE() + .set_TARGET(i_target) + .set_FUNCTION(mss::exp::READ_HOST_FW_RESPONSE_STRUCT) + .set_DATA_SIZE(i_data.size()) + .set_MAX_INDEX(sizeof(host_fw_response_struct)), + "%s Failed to convert from data to host_fw_response_struct data size %u expected size %u", + mss::c_str(i_target), i_data.size(), sizeof(host_fw_response_struct)); + + FAPI_ASSERT(l_crc == o_response.response_header_crc, + fapi2::EXP_INBAND_RSP_CRC_ERR() + .set_COMPUTED(l_crc) + .set_RECEIVED(o_response.response_header_crc) + .set_OCMB_TARGET(i_target), + "%s Response CRC failed to validate computed: 0x%08x got: 0x%08x", + mss::c_str(i_target), l_crc, o_response.response_header_crc); + +fapi_try_exit: + return fapi2::current_err; +} + +/// @brief Reads a response from the response buffer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[out] o_rsp The response data read from the buffer +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getRSP( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_response_struct& o_rsp) +{ + std::vector<uint8_t> l_data(static_cast<int>(sizeof(o_rsp))); + FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_RSP_ADDR, 8, l_data)); + + FAPI_TRY(host_fw_response_struct_from_little_endian(i_target, l_data, o_rsp)); + +fapi_try_exit: + FAPI_DBG("%s Exiting with return code : 0x%08X...", mss::c_str(i_target), (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +} // ns ib + +} // ns exp + +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H new file mode 100644 index 000000000..e179069bd --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H @@ -0,0 +1,441 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file exp_inband.H +/// @brief Explorer specifics for get/putMMIO inband ops +/// +/// One Axone bar register is set per MC channel for MMIO, and another +/// is set per MC channel for config space. Each bar is shared between +/// both sub-channels each with an OCMB. The upper bit of the address +/// determined by the bar sizes is used to determine which sub-channel +/// is selected. This means that for a pair of OCMB's on a channel +/// their config space is contiguous and their MMIO space is contiguous. +/// Therefore a single OCMB's MMIO and config space cannot be contiguous. +/// However, we can still use one BAR attribute and the set_bars procedure +/// can interleave the config space and MMIO space as shown in the table +/// bellow. For example, both MMIO and config bar sizes are 2GB. The +/// 2GB bit becomes the selector for the subchannel. The 4GB bit +/// becomes the offset applied for MMIO operations. +/// +/// +/// Each OCMB is assigned one base address attribute. For example: +/// ocmb | BAR ATTRIBUTE | Type | Base reg - end addr | size | sub-ch +/// +-----+--------------------+------+-----------------------------------------+------+------- +/// ocmb0 | 0x0006030200000000 | cnfg | 0x0006030200000000 - 0x000603027FFFFFFF | 2GB | 0 +/// ocmb1 | 0x0006030280000000 | cnfg | 0x0006030280000000 - 0x00060302FFFFFFFF | 2GB | 1 +/// ocmb0 | N/A | mmio | 0x0006030300000000 - 0x000603037FFFFFFF | 2GB | 0 +/// ocmb1 | N/A | mmio | 0x0006030380000000 - 0x00060303FFFFFFFF | 2GB | 1 +/// +-----+--------------------+------+-----------------------------------------+------+------- +/// ocmb2 | 0x0006030400000000 | cnfg | 0x0006030400000000 - 0x000603047FFFFFFF | 2GB | 0 +/// ocmb3 | 0x0006030480000000 | cnfg | 0x0006030480000000 - 0x00060304FFFFFFFF | 2GB | 1 +/// ocmb2 | N/A | mmio | 0x0006030500000000 - 0x000603057FFFFFFF | 2GB | 0 +/// ocmb3 | N/A | mmio | 0x0006030580000000 - 0x00060305FFFFFFFF | 2GB | 1 +/// +/// Bit 33 of the 64 bit address in big endian order determines if +/// the MMIO operation is a SCOM to the core or a register access +/// to MSCC space. If an MSCC access falls within the range specified +/// by the MSCCRNGE core register it is an access to the MIPS SRAM. +/// Specific locations within the SRAM have been set asside for command +/// and response buffers. Once written an interrupt must be issued +/// to MIPS indicating a new command is ready. Responses will send +/// an interrupt back to the host. +/// +/// Table 4-8:- Address of various buffers +/// Buffer Type MIPS view (un-cached) Host View (OpenCapi) I2C View +/// Command Buffer 0xA103 FF40 BAR + 0x0103 FF40 0xA103 FF40 +/// Response Buffer 0xA103 FF00 BAR + 0x0103 FF00 0xA103 FF00 +/// Data Buffer 0xA102 FF00 BAR + 0x0102 FF00 0xA102 FF00 +/// + +/// @file exp_inband.H +/// @brief implement OpenCAPI config, scom, and MSCC MMIO operations. +// +// *HWP HWP Owner: bgass@us.ibm.com +// *HWP FW Owner: dcrowell@us.ibm.com +// *HWP Team: +// *HWP Level: 2 +// *HWP Consumed by: HB +// +//-------------------------------------------------------------------------------- + +#ifndef __EXP_INBAND_H_ +#define __EXP_INBAND_H_ + +#include <fapi2.H> +#include <exp_data_structs.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> + +namespace mss +{ + +namespace exp +{ + +namespace ib +{ + +static const uint64_t EXPLR_IB_CONFIG_OFFSET = 0x0000000000000000ull; +static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; // 4GB + +//-------------------------------------------------------------------------------- +// The MSCC RAM Range Register SCOM 0x080108e5 MSCCRNGE +// determines the address range for the MIPS SRAM +// An offset within the the 1MB range is used for the command +// +/// Table 4-8:- Address of various buffers 64K 0x1 0000 +/// Buffer Type MIPS view (un-cached) Host View (OpenCapi) I2C View +/// Command Buffer 0xA103 FF40 BAR + 0x0103 FF40 0xA103 FF40 +/// Response Buffer 0xA103 FF00 BAR + 0x0103 FF00 0xA103 FF00 +/// Data Buffer 0xA102 FF00 BAR + 0x0102 FF00 0xA102 FF00 +/// +static const uint64_t EXPLR_IB_SRAM_BASE = 0x01000000; // MSCCRNGE 01000000 020FFFFF +static const uint64_t EXPLR_IB_CMD_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF40; +static const uint64_t EXPLR_IB_RSP_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF00; +static const uint64_t EXPLR_IB_DATA_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x02FF00; + +static const uint64_t EXPLR_IB_CMD_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_CMD_SRAM_ADDR; +static const uint64_t EXPLR_IB_RSP_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_RSP_SRAM_ADDR; +static const uint64_t EXPLR_IB_DATA_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_DATA_SRAM_ADDR; + +//-------------------------------------------------------------------------------- +// Utilities +//-------------------------------------------------------------------------------- + +/// +/// @brief Forces native data into LE order +/// @tparam T the data type to process +/// @param[in] i_input inputted data to process +/// @param[in,out] io_data vector to append data to +/// +template < typename T > +void forceLE(const T& i_input, std::vector<uint8_t>& io_data) +{ + // Temporary variable to process - we'll be doing bit shifts below + T l_temp = i_input; + + for(size_t i = 0; i < sizeof(i_input); i++) + { + // Grab the lowe rorder byte and add it to the back of the vector + const uint8_t l_byte = l_temp & 0xFF; + io_data.push_back(l_byte); + + // Shift higher byte value into lowest no matter existing endianness + l_temp >>= mss::BITS_PER_BYTE; + } +} + +/// +/// @brief Forces native data into LE order for an array +/// @tparam T the data type to process +/// @param[in] i_input inputted data to process +/// @param[in] i_size size of the array +/// @param[in,out] io_data vector to append data to +/// +template < typename T > +inline void forceLEArray(const T* i_input, const uint64_t i_size, std::vector<uint8_t>& io_data) +{ + for(size_t i = 0; i < i_size; i++) + { + forceLE(i_input[i], io_data); + } +} + +/// +/// @brief Converts LE data into native order +/// @tparam T the data type to output to +/// @param[in] i_input inputted data to process +/// @param[in,out] io_idx current index +/// @param[out] o_data data that has been converted into native endianness +/// @return bool true if passing false if failing +/// @note Real FFDC will be handled outside +/// +template < typename T > +bool readLE(const std::vector<uint8_t>& i_input, uint32_t& io_idx, T& o_data) +{ + const uint32_t l_sz = static_cast<uint32_t>(sizeof(o_data)); + io_idx = l_sz + io_idx; + + // Checks that our final index is within the data range + // Note: we decrement the index prior, so equal to is ok + if(io_idx > i_input.size()) + { + return false; + } + + uint64_t l_idx = io_idx; + + o_data = 0; + + for(uint64_t i = 0; i < l_sz; i++) + { + l_idx--; + uint8_t v = i_input[l_idx]; + o_data <<= mss::BITS_PER_BYTE; + o_data |= v; + } + + return true; +} + +/// +/// @brief Converts LE data into native order +/// @tparam T the data type to output to +/// @param[in] i_input inputted data to process +/// @param[in] i_size size of the array +/// @param[in,out] io_idx current index +/// @param[out] o_data data that has been converted into native endianness +/// @return bool true if passing false if failing +/// @note Real FFDC will be handled outside +/// +template < typename T > +bool readLEArray(const std::vector<uint8_t>& i_input, const uint32_t i_size, uint32_t& io_idx, T* o_data) +{ + // Loop while the readLE is still passing and we haven't looped through the array's boundaries + bool l_passing = true; + + for(uint32_t i = 0; i < i_size && l_passing; ++i) + { + l_passing = readLE(i_input, io_idx, o_data[i]); + } + + return l_passing; +} + +/// +/// @brief Converts user_input_msdg to little endian +/// @param[in] i_input user_input_msdg structure to convert +/// @return vector of little endian data +/// +std::vector<uint8_t> user_input_msdg_to_little_endian(const user_input_msdg& i_input); + +/// +/// @brief Converts host_fw_command_struct to little endian +/// @param[in] i_input user_input_msdg structure to convert +/// @return vector of little endian data +/// +std::vector<uint8_t> host_fw_command_struct_to_little_endian(const host_fw_command_struct& i_input); + +/// +/// @brief Converts a little endian data array to a host_fw_response_struct +/// @param[in] i_data little endian data to process +/// @param[out] o_crc computed CRC +/// @param[out] o_response response structure +/// @return true if success false if failure +/// @note helper function - returning a bool and will have true FFDC in a separate function +/// +bool host_fw_response_struct_from_little_endian(const std::vector<uint8_t>& i_data, + uint32_t& o_crc, + host_fw_response_struct& o_response); + +/// +/// @brief Converts a little endian data array to a host_fw_response_struct +/// @param[in] i_target OCMB target on which to operate +/// @param[in] i_data little endian data to process +/// @param[out] o_response response structure +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// @note helper function to allow for checking FFDC +/// +fapi2::ReturnCode host_fw_response_struct_from_little_endian(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target, + const std::vector<uint8_t>& i_data, + host_fw_response_struct& o_response); + +//-------------------------------------------------------------------------------- +// Write operations +//-------------------------------------------------------------------------------- + +/// @brief Writes 64 bits of data to MMIO space to the selected Explorer +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_addr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putMMIO64( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + const fapi2::buffer<uint64_t>& i_data ) ; + + + + +/// @brief Writes 32 bits of data to MMIO space to the selected Explorer +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_addr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putMMIO32( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + const fapi2::buffer<uint32_t>& i_data ) ; + + + + +/// @brief Writes 64 bits of data to SCOM MMIO space +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_scomAddr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putScom( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_scomAddr, + const fapi2::buffer<uint64_t>& i_data) ; + + + + +/// @brief Writes 32 bits of data to OpenCAPI config space +/// +/// @param[in] i_target The Explorer chip to write +/// @param[in] i_cfgAddr The address to write +/// @param[in] i_data The data to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putOCCfg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_cfgAddr, + const fapi2::buffer<uint32_t>& i_data) ; + + + + +/// @brief Writes user_input_msdg to the data buffer +/// +/// @param[in] i_target The Explorer chip to issue the command to +/// @param[in] i_data The user_input_msdg data to write +/// @param[out] o_crc The calculated crc of the data. +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putUserInputMsdg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_input_msdg& i_data, + uint32_t& o_crc); + + + + +/// @brief Writes a command to the command buffer and issues interrupt +/// +/// @param[in] i_target The Explorer chip to issue the command to +/// @param[in] i_cmd The command structure to write +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode putCMD( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_command_struct& i_cmd) ; + + + +//-------------------------------------------------------------------------------- +// Read operations +//-------------------------------------------------------------------------------- + +/// @brief Reads 64 bits of data from MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_addr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getMMIO64( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + fapi2::buffer<uint64_t>& o_data) ; + + + + +/// @brief Reads 32 bits of data from MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_addr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getMMIO32( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_addr, + fapi2::buffer<uint32_t>& o_data) ; + + + + +/// @brief Reads 64 bits of data from SCOM MMIO space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_scomAddr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getScom( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_scomAddr, + fapi2::buffer<uint64_t>& o_data) ; + + + + +/// @brief Reads 32 bits of data from OpenCAPI config space on the selected Explorer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[in] i_cfgAddr The address to read +/// @param[out] o_data The data read from the address +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getOCCfg( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_cfgAddr, + fapi2::buffer<uint32_t>& o_data) ; + + + + +/// @brief Reads a response from the response buffer +/// +/// @param[in] i_target The Explorer chip to read data from +/// @param[out] o_rsp The response data read from the buffer +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode getRSP( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_response_struct& o_rsp) ; + + +//-------------------------------------------------------------------------------- + +} // ns ib + +} // ns exp + +} // ns mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk new file mode 100644 index 000000000..3f998fd58 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk @@ -0,0 +1,32 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=exp_inband +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/nest) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/common/include) +# Explicitly calling the below to only pick up the generic constants +# We don't want to clutter this procedure w/ too many includes +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/procedures/hwp/memory) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H new file mode 100644 index 000000000..c6a6793aa --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H @@ -0,0 +1,133 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file crc32.H +/// @brief Implement crc32 +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB +// + +#ifndef __CRC32_H_ +#define __CRC32_H_ + +#include <stdint.h> +#include <vector> + +// CRC32 lookup table can be found online via multiple websites +static const uint32_t crc32_lookup_table[] = +{ + 0x00000000ul, 0x77073096ul, 0xEE0E612Cul, 0x990951BAul, + 0x076DC419ul, 0x706AF48Ful, 0xE963A535ul, 0x9E6495A3ul, + 0x0EDB8832ul, 0x79DCB8A4ul, 0xE0D5E91Eul, 0x97D2D988ul, + 0x09B64C2Bul, 0x7EB17CBDul, 0xE7B82D07ul, 0x90BF1D91ul, + 0x1DB71064ul, 0x6AB020F2ul, 0xF3B97148ul, 0x84BE41DEul, + 0x1ADAD47Dul, 0x6DDDE4EBul, 0xF4D4B551ul, 0x83D385C7ul, + 0x136C9856ul, 0x646BA8C0ul, 0xFD62F97Aul, 0x8A65C9ECul, + 0x14015C4Ful, 0x63066CD9ul, 0xFA0F3D63ul, 0x8D080DF5ul, + 0x3B6E20C8ul, 0x4C69105Eul, 0xD56041E4ul, 0xA2677172ul, + 0x3C03E4D1ul, 0x4B04D447ul, 0xD20D85FDul, 0xA50AB56Bul, + 0x35B5A8FAul, 0x42B2986Cul, 0xDBBBC9D6ul, 0xACBCF940ul, + 0x32D86CE3ul, 0x45DF5C75ul, 0xDCD60DCFul, 0xABD13D59ul, + 0x26D930ACul, 0x51DE003Aul, 0xC8D75180ul, 0xBFD06116ul, + 0x21B4F4B5ul, 0x56B3C423ul, 0xCFBA9599ul, 0xB8BDA50Ful, + 0x2802B89Eul, 0x5F058808ul, 0xC60CD9B2ul, 0xB10BE924ul, + 0x2F6F7C87ul, 0x58684C11ul, 0xC1611DABul, 0xB6662D3Dul, + 0x76DC4190ul, 0x01DB7106ul, 0x98D220BCul, 0xEFD5102Aul, + 0x71B18589ul, 0x06B6B51Ful, 0x9FBFE4A5ul, 0xE8B8D433ul, + 0x7807C9A2ul, 0x0F00F934ul, 0x9609A88Eul, 0xE10E9818ul, + 0x7F6A0DBBul, 0x086D3D2Dul, 0x91646C97ul, 0xE6635C01ul, + 0x6B6B51F4ul, 0x1C6C6162ul, 0x856530D8ul, 0xF262004Eul, + 0x6C0695EDul, 0x1B01A57Bul, 0x8208F4C1ul, 0xF50FC457ul, + 0x65B0D9C6ul, 0x12B7E950ul, 0x8BBEB8EAul, 0xFCB9887Cul, + 0x62DD1DDFul, 0x15DA2D49ul, 0x8CD37CF3ul, 0xFBD44C65ul, + 0x4DB26158ul, 0x3AB551CEul, 0xA3BC0074ul, 0xD4BB30E2ul, + 0x4ADFA541ul, 0x3DD895D7ul, 0xA4D1C46Dul, 0xD3D6F4FBul, + 0x4369E96Aul, 0x346ED9FCul, 0xAD678846ul, 0xDA60B8D0ul, + 0x44042D73ul, 0x33031DE5ul, 0xAA0A4C5Ful, 0xDD0D7CC9ul, + 0x5005713Cul, 0x270241AAul, 0xBE0B1010ul, 0xC90C2086ul, + 0x5768B525ul, 0x206F85B3ul, 0xB966D409ul, 0xCE61E49Ful, + 0x5EDEF90Eul, 0x29D9C998ul, 0xB0D09822ul, 0xC7D7A8B4ul, + 0x59B33D17ul, 0x2EB40D81ul, 0xB7BD5C3Bul, 0xC0BA6CADul, + 0xEDB88320ul, 0x9ABFB3B6ul, 0x03B6E20Cul, 0x74B1D29Aul, + 0xEAD54739ul, 0x9DD277AFul, 0x04DB2615ul, 0x73DC1683ul, + 0xE3630B12ul, 0x94643B84ul, 0x0D6D6A3Eul, 0x7A6A5AA8ul, + 0xE40ECF0Bul, 0x9309FF9Dul, 0x0A00AE27ul, 0x7D079EB1ul, + 0xF00F9344ul, 0x8708A3D2ul, 0x1E01F268ul, 0x6906C2FEul, + 0xF762575Dul, 0x806567CBul, 0x196C3671ul, 0x6E6B06E7ul, + 0xFED41B76ul, 0x89D32BE0ul, 0x10DA7A5Aul, 0x67DD4ACCul, + 0xF9B9DF6Ful, 0x8EBEEFF9ul, 0x17B7BE43ul, 0x60B08ED5ul, + 0xD6D6A3E8ul, 0xA1D1937Eul, 0x38D8C2C4ul, 0x4FDFF252ul, + 0xD1BB67F1ul, 0xA6BC5767ul, 0x3FB506DDul, 0x48B2364Bul, + 0xD80D2BDAul, 0xAF0A1B4Cul, 0x36034AF6ul, 0x41047A60ul, + 0xDF60EFC3ul, 0xA867DF55ul, 0x316E8EEFul, 0x4669BE79ul, + 0xCB61B38Cul, 0xBC66831Aul, 0x256FD2A0ul, 0x5268E236ul, + 0xCC0C7795ul, 0xBB0B4703ul, 0x220216B9ul, 0x5505262Ful, + 0xC5BA3BBEul, 0xB2BD0B28ul, 0x2BB45A92ul, 0x5CB36A04ul, + 0xC2D7FFA7ul, 0xB5D0CF31ul, 0x2CD99E8Bul, 0x5BDEAE1Dul, + 0x9B64C2B0ul, 0xEC63F226ul, 0x756AA39Cul, 0x026D930Aul, + 0x9C0906A9ul, 0xEB0E363Ful, 0x72076785ul, 0x05005713ul, + 0x95BF4A82ul, 0xE2B87A14ul, 0x7BB12BAEul, 0x0CB61B38ul, + 0x92D28E9Bul, 0xE5D5BE0Dul, 0x7CDCEFB7ul, 0x0BDBDF21ul, + 0x86D3D2D4ul, 0xF1D4E242ul, 0x68DDB3F8ul, 0x1FDA836Eul, + 0x81BE16CDul, 0xF6B9265Bul, 0x6FB077E1ul, 0x18B74777ul, + 0x88085AE6ul, 0xFF0F6A70ul, 0x66063BCAul, 0x11010B5Cul, + 0x8F659EFFul, 0xF862AE69ul, 0x616BFFD3ul, 0x166CCF45ul, + 0xA00AE278ul, 0xD70DD2EEul, 0x4E048354ul, 0x3903B3C2ul, + 0xA7672661ul, 0xD06016F7ul, 0x4969474Dul, 0x3E6E77DBul, + 0xAED16A4Aul, 0xD9D65ADCul, 0x40DF0B66ul, 0x37D83BF0ul, + 0xA9BCAE53ul, 0xDEBB9EC5ul, 0x47B2CF7Ful, 0x30B5FFE9ul, + 0xBDBDF21Cul, 0xCABAC28Aul, 0x53B39330ul, 0x24B4A3A6ul, + 0xBAD03605ul, 0xCDD70693ul, 0x54DE5729ul, 0x23D967BFul, + 0xB3667A2Eul, 0xC4614AB8ul, 0x5D681B02ul, 0x2A6F2B94ul, + 0xB40BBE37ul, 0xC30C8EA1ul, 0x5A05DF1Bul, 0x2D02EF8Dul +}; + +/// +/// @brief Generates a CRC on all +/// @param[in] i_data data on which to generate the CRC32 +/// @param[in] i_len allows the user to specify a length of data to generate CRC - used for response structure - defaulted to max (use whole array) +/// @return the CRC32 for the inputted vector +/// +inline uint32_t crc32_gen(const std::vector<uint8_t>& i_data, const uint64_t i_len = ~0) +{ + uint32_t l_crc = 0xFFFFFFFFul; + + // Loops until + // 1) data array is completed OR + // 2) data length is completed + for (uint64_t i = 0; i < i_data.size() && i < i_len; ++i) + { + const uint8_t l_data = i_data[i]; + const uint32_t l_tmp = l_crc ^ static_cast<uint32_t>(l_data); + l_crc = (l_crc >> 8) ^ crc32_lookup_table[ l_tmp & 0xFF ]; + } + + return l_crc ^ 0xFFFFFFFFul; +} + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 83aee0285..5769ec258 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -40,8 +40,6 @@ namespace mss { namespace exp { -namespace i2c -{ /// /// @brief explorer ffdc codes @@ -50,8 +48,12 @@ enum ffdc_codes { EXP_I2C_GET_FIELD = 0x0000, EXP_I2C_SET_FIELD = 0x0001, + READ_HOST_FW_RESPONSE_STRUCT = 0x0003, }; +namespace i2c +{ + /// @brief List of explorer I2C commands /// enum cmd_id : uint8_t @@ -119,7 +121,6 @@ enum boot_stages FW_UPGRADE_MODE = 0x02, RUNTIME_FW = 0x03, }; - }// i2c }// exp }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml new file mode 100644 index 000000000..94b77129e --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml @@ -0,0 +1,58 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + + <hwpError> + <rc>RC_EXP_INBAND_RSP_CRC_ERR</rc> + <description> + Inband response CRC failed to validate. + </description> + <ffdc>COMPUTED</ffdc> + <ffdc>RECEIVED</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_EXP_INBAND_LE_DATA_RANGE</rc> + <description> + Data is not long enough for little endian conversion + </description> + <ffdc>TARGET</ffdc> + <ffdc>FUNCTION</ffdc> + <ffdc>DATA_SIZE</ffdc> + <ffdc>MAX_INDEX</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + +</hwpErrors> diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C new file mode 100644 index 000000000..c2cb8d8ef --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C @@ -0,0 +1,129 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_get_mmio.C +/// @brief Implement getMMIO via ADU +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB + +#include <p9a_get_mmio.H> +#include <p9a_mmio_util.H> +#include <p9_adu_setup.H> +#include <p9_adu_access.H> +#include <p9_adu_coherent_utils.H> + +/// @brief Reads data via mmio from the target +/// +/// @param[in] i_target HW target to operate on. +/// @param[in] i_mmioAddr Address to read, relative to this Target's system +/// MMIO address. +/// @param[in] i_transSize The transaction size. +/// @param[out] o_data Buffer that holds data read from HW target. +/// The size of the buffer determines the number of +/// amount of bytes that are read. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9a_get_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_mmioAddr, + const size_t i_transSize, + std::vector<uint8_t>& o_data) +{ + uint8_t data[8]; + uint8_t l_idx; + uint8_t l_data_idx; + uint32_t l_max_grans; + uint32_t l_grans; + p9_ADU_oper_flag l_myAduFlag; + uint64_t l_addr = i_mmioAddr; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc_target; + uint32_t l_i = 0; + const auto l_size = o_data.size(); + char l_hexdata[(l_size * 2) + 1]; + + const uint32_t l_tsize = static_cast<uint32_t>(i_transSize); + + FAPI_ASSERT(l_tsize == 4 || l_tsize == 8, + fapi2::P9A_MMIO_BAD_SIZE_ERR() + .set_TARGET(i_target) + .set_SIZE(l_tsize), + "Incorrect MMIO size"); + + l_grans = (l_size / l_tsize); + + if ((l_size % l_tsize) > 0) + { + l_grans++; + } + + FAPI_TRY(addOMIBase(i_target, l_addr)); + FAPI_INF("Read address: 0x%lX transaction size: %d", l_addr, l_tsize); + + l_proc_target = i_target.getParent<fapi2::TARGET_TYPE_OMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + + l_myAduFlag.setOperationType(p9_ADU_oper_flag::CACHE_INHIBIT); + l_myAduFlag.setAutoIncrement(true); + l_myAduFlag.setTransactionSize(static_cast<p9_ADU_oper_flag::Transaction_size_t>(l_tsize)); + + l_data_idx = 0; + + while (l_data_idx < l_size) + { + FAPI_TRY(p9_adu_setup(l_proc_target, l_addr, true, l_myAduFlag.setFlag(), l_max_grans)); + + while (l_grans > 0 && l_max_grans > 0) + { + FAPI_TRY(p9_adu_access(l_proc_target, l_addr, true, l_myAduFlag.setFlag(), + l_data_idx == 0, // The first transaction + l_grans == 1, // The last transaction + data)); + + for (l_idx = (l_addr & 0x4) ; l_idx < 8 && l_data_idx < l_size; l_idx++) + { + o_data[l_data_idx] = data[l_idx]; + l_data_idx++; + } + + l_grans--; + l_max_grans--; + l_addr += l_tsize; + } + } + + for (l_i = 0; l_i < l_size; l_i++) + { + sprintf(&l_hexdata[l_i * 2], "%02X", o_data[l_i]); + } + + FAPI_INF("Read data: 0x%s", l_hexdata); + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.H b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.H new file mode 100644 index 000000000..8e0d482d9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_get_mmio.H +/// @brief Implement getMMIO via ADU +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB +// + +#ifndef _P9A_GET_MMIO_H__ +#define _P9A_GET_MMIO_H__ + +#include <fapi2.H> +#include <vector> + +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9a_get_mmio_FP_t) +(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + const uint64_t, + const size_t, + std::vector<uint8_t>&); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// @brief Reads data via mmio from the target +/// +/// @param[in] i_target HW target to operate on. +/// @param[in] i_mmioAddr Address to read, relative to this Target's system +/// MMIO address. +/// @param[in] i_transSize The transaction size. +/// @param[out] o_data Buffer that holds data read from HW target. +/// The size of the buffer determines the number of +/// amount of bytes that are read. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. + fapi2::ReturnCode p9a_get_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_mmioAddr, + const size_t i_transSize, + std::vector<uint8_t>& o_data); + +} +#endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.mk b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.mk new file mode 100644 index 000000000..76abb0618 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.mk @@ -0,0 +1,31 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9a_get_mmio +OBJS+=p9a_mmio_util.o +OBJS+=p9_adu_setup.o +OBJS+=p9_adu_access.o +OBJS+=p9_adu_coherent_utils.o +OBJS+=p9_fbc_utils.o +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.C b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.C new file mode 100644 index 000000000..a1eb3d0dd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.C @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_mmio_util.C +/// @brief MMIO utility functions +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB + +#include <p9a_mmio_util.H> +#include <p9_adu_setup.H> +#include <p9_adu_access.H> +#include <p9_adu_coherent_utils.H> + + +fapi2::ReturnCode addOMIBase(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint64_t& io_mmioAddr) +{ + uint64_t l_base_addr; + + fapi2::Target<fapi2::TARGET_TYPE_OMI> l_omi_target = i_target.getParent<fapi2::TARGET_TYPE_OMI>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET, + l_omi_target, + l_base_addr), + "Error from FAPI_ATTR_GET (ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET)"); + + io_mmioAddr |= l_base_addr; + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.H b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.H new file mode 100644 index 000000000..550e813a4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.H @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_mmio_util.H +/// @brief MMIO utility functions +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB +// + +#ifndef _P9A_MMIO_UTIL_H__ +#define _P9A_MMIO_UTIL_H__ + +#include <fapi2.H> +#include <vector> + +/// @brief Adds the OCMB BAR to the address. +/// +/// @param[in] i_target HW target to operate on. +/// @param[inout] io_mmioAddr Address to add bar to +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode addOMIBase(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint64_t& io_mmioAddr); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.mk b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.mk new file mode 100644 index 000000000..5b68227ad --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.mk @@ -0,0 +1,26 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/nest/p9a_mmio_util.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9a_mmio_util +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C new file mode 100644 index 000000000..adebd16da --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C @@ -0,0 +1,129 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_put_mmio.C +/// @brief Implement putMMIO via ADU +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB + +#include <p9a_put_mmio.H> +#include <p9a_mmio_util.H> +#include <p9_adu_setup.H> +#include <p9_adu_access.H> +#include <p9_adu_coherent_utils.H> + +/// @brief Writes data via mmio to the target. +/// +/// @param[in] i_target HW target to operate on. +/// @param[in] i_mmioAddr Address to read, relative to this Target's system +/// MMIO address. +/// @param[in] i_transSize The transaction size. +/// @param[in] i_data Buffer that holds data to write to the HW target. +/// The size of the buffer determines the number of +/// amount of bytes that are written. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9a_put_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_mmioAddr, + const size_t i_transSize, + const std::vector<uint8_t>& i_data) +{ + uint8_t data[8]; + uint8_t l_idx; + uint8_t l_data_idx; + uint32_t l_max_grans; + uint32_t l_grans; + p9_ADU_oper_flag l_myAduFlag; + uint64_t l_addr = i_mmioAddr; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc_target; + + auto l_size = i_data.size(); + char l_hexdata[(l_size * 2) + 1]; + + for (uint32_t l_i = 0; l_i < l_size; l_i++) + { + sprintf(&l_hexdata[l_i * 2], "%02X", i_data[l_i]); + } + + uint32_t l_tsize = static_cast<uint32_t>(i_transSize); + + FAPI_ASSERT(l_tsize == 4 || l_tsize == 8, + fapi2::P9A_MMIO_BAD_SIZE_ERR() + .set_TARGET(i_target) + .set_SIZE(l_size), + "Incorrect MMIO size"); + + l_grans = (l_size / l_tsize); + + if ((l_size % l_tsize) > 0) + { + l_grans++; + } + + FAPI_TRY(addOMIBase(i_target, l_addr)); + FAPI_INF("Write address: %lX", l_addr); + FAPI_INF("Write data: %s", l_hexdata); + + l_proc_target = i_target.getParent<fapi2::TARGET_TYPE_OMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + + l_myAduFlag.setOperationType(p9_ADU_oper_flag::CACHE_INHIBIT); + l_myAduFlag.setAutoIncrement(true); + l_myAduFlag.setTransactionSize(static_cast<p9_ADU_oper_flag::Transaction_size_t>(l_tsize)); + + l_data_idx = 0; + + while (l_data_idx < l_size) + { + FAPI_TRY(p9_adu_setup(l_proc_target, l_addr, false, l_myAduFlag.setFlag(), l_max_grans)); + + while (l_grans > 0 && l_max_grans > 0) + { + + for (l_idx = 0 ; l_idx < l_tsize && l_data_idx < l_size; l_idx++) + { + data[l_idx + (l_addr & 0x4)] = i_data[l_data_idx]; + l_data_idx++; + } + + FAPI_TRY(p9_adu_access(l_proc_target, l_addr, false, l_myAduFlag.setFlag(), + l_data_idx == 0, // The first transaction + l_grans == 1, // The last transaction + data)); + + l_grans--; + l_max_grans--; + l_addr += l_tsize; + } + } + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.H b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.H new file mode 100644 index 000000000..befe3fe59 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9a_put_mmio.H +/// @brief Implement putMMIO via ADU +// +// *HWP HWP Owner: Ben Gass bgass@us.ibm.com +// *HWP FW Owner: Daniel Crowell dcrowell@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB +// + +#ifndef _P9A_PUT_MMIO_H__ +#define _P9A_PUT_MMIO_H__ + +#include <fapi2.H> +#include <vector> + +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9a_put_mmio_FP_t) +(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + const uint64_t, + const size_t, + const std::vector<uint8_t>&); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// @brief Writes data via mmio to the target. +/// +/// @param[in] i_target HW target to operate on. +/// @param[in] i_mmioAddr Address to read, relative to this Target's system +/// MMIO address. +/// @param[in] i_transSize The transaction size. +/// @param[in] i_data Buffer that holds data to write to the HW target. +/// The size of the buffer determines the number of +/// amount of bytes that are written. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. + fapi2::ReturnCode p9a_put_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_mmioAddr, + const size_t i_transSize, + const std::vector<uint8_t>& i_data); + +} +#endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.mk b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.mk new file mode 100644 index 000000000..b5dcf4743 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.mk @@ -0,0 +1,31 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9a_put_mmio +OBJS+=p9a_mmio_util.o +OBJS+=p9_adu_setup.o +OBJS+=p9_adu_access.o +OBJS+=p9_adu_coherent_utils.o +OBJS+=p9_fbc_utils.o +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml new file mode 100644 index 000000000..779aec2fc --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml @@ -0,0 +1,83 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_setup_bars.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_OMI_INBAND_BAR_ENABLE</id> + <targetType>TARGET_TYPE_OMI</targetType> + <description> DMI inband BAR enable. + Set by platform. + Used by p9c_set_inband_addr. + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_OMI</targetType> + <description> + OMI inband BAR address offset. + + Set by platform. + + One Axone bar register is set per MC channel for MMIO and another + is set per MC channel for config space. The bar is shared between + both sub-channels each with an OCMB. The upper bit of the bar + size is used to determine which sub-channel is selected. This + means that for two OCMB's their config space is contiguous and + their MMIO space is contiguous. Therefore a single OCMB's MMIO + and config space cannot be contiguous. However, we can still + use one BAR attribute. The p9a_omi_setup_bars procedure can interleave + the config space and MMIO space as shown in the table bellow. + For example, both MMIO and config bar sizes are 2GB. The 2GB + bit becomes the selector for the subchannel. The 4GB bit becomes + the offset applied for MMIO operations. + + + Each OCMB is assigned one base address attribute. + ocmb | BAR ATTRIBUTE | Type | Base reg - end addr | size | sub-ch + +-----+--------------------+------+-----------------------------------------+------+------- + ocmb0 | 0x0006030200000000 | cnfg | 0x0006030200000000 - 0x000603027FFFFFFF | 2GB | 0 + ocmb1 | 0x0006030280000000 | cnfg | 0x0006030280000000 - 0x00060302FFFFFFFF | 2GB | 1 + ocmb0 | N/A | mmio | 0x0006030300000000 - 0x000603037FFFFFFF | 2GB | 0 + ocmb1 | N/A | mmio | 0x0006030380000000 - 0x00060303FFFFFFFF | 2GB | 1 + +-----+--------------------+------+-----------------------------------------+------+------- + ocmb2 | 0x0006030400000000 | cnfg | 0x0006030400000000 - 0x000603047FFFFFFF | 2GB | 0 + ocmb3 | 0x0006030480000000 | cnfg | 0x0006030480000000 - 0x00060304FFFFFFFF | 2GB | 1 + ocmb2 | N/A | mmio | 0x0006030500000000 - 0x000603057FFFFFFF | 2GB | 0 + ocmb3 | N/A | mmio | 0x0006030580000000 - 0x00060305FFFFFFFF | 2GB | 1 + + Used by p9a_omi_setup_bars + </description> + <valueType>uint64</valueType> + <platInit/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> + +</attributes> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9a_mmio_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9a_mmio_errors.xml new file mode 100644 index 000000000..2a9cf87d6 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/error_info/p9a_mmio_errors.xml @@ -0,0 +1,38 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9a_mmio_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_P9A_MMIO_BAD_SIZE_ERR</rc> + <description> + Procedure: p9a_mmio_utils + Incorrect data size for MMIO operation + </description> + <ffdc>TARGET</ffdc> + <ffdc>SIZE</ffdc> + <!-- no callout, deconfig, gard tags as FW does not consume --> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> |
