diff options
author | Dean Sanner <dsanner@us.ibm.com> | 2013-03-20 13:25:46 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-03-29 13:31:04 -0500 |
commit | 6e854b214f209e339309170c4bcb2e090bd57e89 (patch) | |
tree | 8d2512de22bf1b8e60f9d54c6f3f6547fd9ca973 /src | |
parent | 3cf441484baeef5b4219a757776cd1c963eb5f70 (diff) | |
download | talos-hostboot-6e854b214f209e339309170c4bcb2e090bd57e89.tar.gz talos-hostboot-6e854b214f209e339309170c4bcb2e090bd57e89.zip |
Updated DMI ref clock swizzle for DMI/MCS numbering
Change-Id: I20e5dde7b318ceff543be8b527b478fef3abf1a0
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3656
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
4 files changed, 275 insertions, 268 deletions
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C index d2413c303..95f20019b 100644 --- a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C +++ b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_dmi_scominit.C,v 1.2 2013/01/24 20:21:23 thomsen Exp $ +// $Id: cen_dmi_scominit.C,v 1.4 2013/02/05 17:41:18 thomsen Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_dmi_scominit.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -39,7 +39,8 @@ //------------------------------------------------------------------------------ // Version Date Owner Description //------------------------------------------------------------------------------ -// 1.3 01/23/13 thomsen Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files +// 1.4 02/05/13 thomsen Fixed typo that caused the procedure to not compile +// 1.3 01/31/13 thomsen Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files, Fixed informational print to not say Error // 1.2 01/09/13 thomsen Added separate calls to SIM vs. HW scominit files // Added commented-out call to OVERRIDE initfile for system/bus/lane specific inits // 1.1 8/11/12 jmcgill Initial release @@ -77,7 +78,7 @@ fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target) if (target_type == fapi::TARGET_TYPE_MEMBUF_CHIP) { // Call BASE DMI SCOMINIT - FAPI_INF("cen_dmi_scominit: Executing %s on %s", + FAPI_INF("cen_dmi_scominit: fapiHwpExecInitfile executing %s on %s", CEN_DMI_BASE_IF, i_target.toEcmdString()); FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_BASE_IF); if (!rc.ok()) @@ -87,8 +88,8 @@ fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target) break; } // Call CUSTOMIZED DMI SCOMINIT (system specific) - FAPI_INF("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s", - CEN_DMI_CUSTOM_IF, i_target.toEcmdString(), i_target.toEcmdString()); + FAPI_INF("cen_dmi_scominit: fapiHwpExecInitfile executing %s on %s", + CEN_DMI_CUSTOM_IF, i_target.toEcmdString()); FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_CUSTOM_IF); if (!rc.ok()) { diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile index ba8e45593..a9192ad09 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile @@ -1,13 +1,24 @@ -#-- $Id: cen.dmi.custom.scom.initfile,v 1.1 2013/01/24 20:17:06 thomsen Exp $ +#-- $Id: cen.dmi.custom.scom.initfile,v 1.6 2013/03/15 21:21:27 thomsen Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.6 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. +#-- 1.5 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. +#-- | | |Fixed address typo on tx_clk_invert entry +#-- 1.4 |thomsen |02/26/13|Fixed typo on lane 22 tx_lane_invert +#-- 1.3 |thomsen |02/18/13|Renamed HW_EXPRESS and VBU_EXPRESS to def_IS_HW & def_IS_VBU. Added target comments, changed to attribute method of setting tx_lane_invert's and added tx_clk_invert +#-- 1.2 |berger |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert #-- 1.1 |thomsen |01/23/13|Created initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- +#-- TARGETS: +#-- SYS. Chiplet target +#-- TGT1. Proc target +#-- TGT2. Connected Chiplet target +#-- TGT3. Connected Proc target #--Master list of variables that can be used in this file is at: #--<Attribute Definition Location> @@ -34,37 +45,33 @@ include edi.io.define #-- ----------------------------------------------------------------------------- #--****************************************************************************** #-- ----------------------------------------------------------------------------- +define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); +define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); -# ./iotk put rx_fence=1 -# 0x -scom 0x800.0b(rx_fence_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_fence, 0b1; -} +define def_all_lanes=11111; + + +#--*********************************************************************************** +#------------------------------------------------------------------------------------- +#-- Overrides +#------------------------------------------------------------------------------------- +#--*********************************************************************************** -# ./iotk put rx_c4_sel=00 -# ./iotk put rx_prot_speed_slct=1 -# 0x8009C0000201043F -scom 0x800.0b(rx_misc_analog_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_c4_sel, 0b00; -rx_prot_speed_slct, 0b1; -} # ./iotk put rx_servo_timeout_sel_D=1001 -# 0x800B60000201043F +# 0x800B60000201043F scom 0x800.0b(rx_servo_to1_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_servo_timeout_sel_d, 0b1001; } # ./iotk put rx_servo_timeout_sel_H=1110 -# 0x800B68000201043F +# 0x800B68000201043F scom 0x800.0b(rx_servo_to2_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_servo_timeout_sel_h, 0b1110; } # ./iotk put rx_servo_timeout_sel_I=1011 # ./iotk put rx_servo_timeout_sel_J=1100 -# 0x800B70000201043F +# 0x800B70000201043F scom 0x800.0b(rx_servo_to3_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_servo_timeout_sel_i, 0b1011; @@ -75,7 +82,7 @@ rx_servo_timeout_sel_k, 0b1101; # ./iotk put rx_ds_bl_timeout_sel=101 # ./iotk put rx_ds_timeout_sel=110 #./iotk put rx_sls_timeout_sel=111 -# 0x800898000201043F +# 0x800898000201043F scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_wt_timeout_sel, 0b111; @@ -85,7 +92,7 @@ rx_sls_timeout_sel, 0b001; } # ./iotk put rx_bit_lock_timeout_sel=110 -# 0x800B08000201043F +# 0x800B08000201043F scom 0x800.0b(rx_mode1_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_bit_lock_timeout_sel, 0b110; @@ -95,7 +102,7 @@ rx_bit_lock_timeout_sel, 0b110; # ./iotk put rx_eo_ctle_timeout_sel=111 # ./iotk put rx_eo_h1ap_timeout_sel=111 # ./iotk put rx_eo_ddc_timeout_sel=111 -# 0x800910000201043F +# 0x800910000201043F scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_eo_offset_timeout_sel, 0b111; @@ -105,337 +112,267 @@ rx_eo_h1ap_timeout_sel, 0b111; rx_eo_ddc_timeout_sel, 0b111; } -#./iotk put tx_zcal_sm_min_val=0010101 -#./iotk put tx_zcal_sm_max_val=1000110 -# 0x800F2C000201043F -scom 0x800.0b(tx_impcal_swo2_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -tx_zcal_sm_min_val, 0b0010101; -tx_zcal_sm_max_val, 0b1000110; -} -#./iotk put tx_zcal_p_4x=00100 -# 0x800F1C000201043F -scom 0x800.0b(tx_impcal_p_4x_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -tx_zcal_p_4x, 0b00100; -} - -# 800A380002011E3F -scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_eo_enable_latch_offset_cal, 0b1; -rx_eo_enable_ctle_cal, 0b1; -rx_eo_enable_vga_cal, 0b1; -rx_eo_enable_dfe_h1_cal, 0b1; -rx_eo_enable_h1ap_tweak, 0b1; -rx_eo_enable_ddc, 0b1; -rx_eo_enable_final_l2u_adj, 0b1; -rx_eo_enable_ber_test, 0b1; -rx_eo_enable_result_check, 0b1; -} scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { bits, scom_data; rx_eo_converged_end_count, 0b111; } +#--*********************************************************************************** +#------------------------------------------------------------------------------------- +# __ ____ __ __ +# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ +# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ +# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / +# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ +# /_/ +#------------------------------------------------------------------------------------- +#--*********************************************************************************** -# 0x800AB8000201043F -scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_rc_enable_latch_offset_cal, 0b1; -rx_rc_enable_ctle_cal, 0b1; -rx_rc_enable_vga_cal, 0b1; -rx_rc_enable_h1ap_tweak, 0b1; -rx_rc_enable_ddc, 0b1; -rx_rc_enable_ber_test, 0b1; -rx_rc_enable_result_check, 0b1; -#rx_rc_enable_dfe_h1_cal, 0b0; # Leave DFE off during recal for now -} - +# rx_lane_pdwn +#scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(cn_gcr_addr){ +# bits, scom_data; +# rx_lane_pdwn, 0b0; +#} -#--****************************************************************************** +# tx_lane_pdwn +#scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(cn_gcr_addr){ +# bits, scom_data; +# tx_lane_pdwn, 0b0; +#} +#--*********************************************************************************** #------------------------------------------------------------------------------------- # _______ __ __ ___ _ ________ _____ ___ ____________ ______ # /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ -# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / -# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / -# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ +# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / +# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / +# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ # figlet -fslant #------------------------------------------------------------------------------------- -#--****************************************************************************** +#--*********************************************************************************** # These need to come as attributes from the MRW rather than be hardcoded here -define def_EI_TX_LANE_INVERT_VEC_CEN4 = 0x60003500; # MSBSWAP=0 ON TULETA -define def_EI_TX_LANE_INVERT_VEC_CEN5 = 0x7FE4FF00; # MSBSWAP=1 ON TULETA -define def_EI_TX_LANE_INVERT_VEC_CEN6 = 0xED937F00; # MSBSWAP=1 ON TULETA -define def_EI_TX_LANE_INVERT_VEC_CEN7 = 0xFFF4FF00; # MSBSWAP=1 ON TULETA +#define def_EI_TX_LANE_INVERT_VEC_CEN4 = 0x60003500; # MSBSWAP=0 ON TULETA +#define def_EI_TX_LANE_INVERT_VEC_CEN5 = 0x7FE4FF00; # MSBSWAP=1 ON TULETA +#define def_EI_TX_LANE_INVERT_VEC_CEN6 = 0xED937F00; # MSBSWAP=1 ON TULETA +#define def_EI_TX_LANE_INVERT_VEC_CEN7 = 0xFFF4FF00; # MSBSWAP=1 ON TULETA # These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'. # Lane 0 -# scom 0x800404000201043F +# scom 0x800404000201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x80000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x80000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x80000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x80000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x80000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0; } # Lane 1 -# 0x800404010201043F +# 0x800404010201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x40000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x40000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x40000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x40000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x40000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0; } # Lane 2 -# 0x800404020201043F +# 0x800404020201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x20000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x20000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x20000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x20000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x20000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0; } # Lane 3 -# 0x800404030201043F +# 0x800404030201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x10000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x10000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x10000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x10000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x10000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0; } # Lane 4 -# 0x800404040201043F +# 0x800404040201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x08000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x08000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x08000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x08000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x08000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0; } # Lane 5 # 0x800404050201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x04000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x04000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x04000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x04000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x04000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0; } # Lane 6 # 0x800404060201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x02000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x02000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x02000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x02000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x02000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0; } # Lane 7 # 0x800404070201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x01000000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x01000000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x01000000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x01000000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x01000000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0; } # Lane 8 # 0x800404080201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00800000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00800000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00800000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00800000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00800000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0; } # Lane 9 # 0x800404090201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00400000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00400000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00400000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00400000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00400000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0; } # Lane 10 # 0x8004040A0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00200000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00200000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00200000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00200000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00200000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0; } # Lane 11 # 0x8004040B0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00100000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00100000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00100000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00100000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00100000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0; } # Lane 12 # 0x8004040C0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00080000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00080000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00080000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00080000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00080000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0; } # Lane 13 # 0x8004040D0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00040000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00040000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00040000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00040000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00040000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0; } # Lane 14 # 0x8004040E0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00020000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00020000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00020000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00020000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00020000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0; } # Lane 15 # 0x8004040F0201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00010000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00010000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00010000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00010000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00010000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0; } # Lane 16 # 0x800404100201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00008000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00008000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00008000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00008000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00008000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0; } # Lane 17 # 0x800404110201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00004000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00004000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00004000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00004000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00004000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0; } # Lane 18 # 0x800404120201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00002000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00002000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00002000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00002000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00002000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0; } # Lane 19 # 0x800404130201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00001000) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00001000) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00001000) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00001000) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00001000) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0; } # Lane 20 # 0x800404140201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000800) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000800) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000800) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000800) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000800) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0; } # Lane 21 # 0x800404150201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000400) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000400) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000400) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000400) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000400) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0; } # Lane 22 # 0x800404160201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000200) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000200) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000200) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000200) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000200) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0; } # Lane 23 # 0x800404170201043F scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr) { bits, scom_data, expr; -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000100) > 0) && (ATTR_POS % 4 == 0); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000100) > 0) && (ATTR_POS % 4 == 1); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000100) > 0) && (ATTR_POS % 4 == 2); -tx_lane_invert, 0b1, ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000100) > 0) && (ATTR_POS % 4 == 3); -#tx_lane_invert, 0b1, (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000100) > 0; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000100) > 0; +} + +#--*********************************************************************************** +#------------------------------------------------------------------------------------- +# _______ __ ________ __ __ ____ __ +# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ /_ +# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ +# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / /_ +# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ + +# figlet -fslant +#------------------------------------------------------------------------------------- +#--*********************************************************************************** +# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) +# 0x800???7008010C3F +scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_22).0x(cn_gcr_addr) { +bits, scom_data, expr; +tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0; } #--*********************************************************************************** #------------------------------------------------------------------------------------- -# __ ________ ____ _____ -# / |/ / ___// __ ) / ___/ ______ _____ +# __ ________ ____ _____ +# / |/ / ___// __ ) / ___/ ______ _____ # / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ # / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / -# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ -# /_/ +# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ +# /_/ # figlet -fslant #------------------------------------------------------------------------------------- #--*********************************************************************************** # TX_MSBSWAP setting via manaual SCOM overrides # ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0) -# 0x800C1C000201043F +# 0x800C1C000201043F scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_msbswap, 0b0, (ATTR_POS % 4 == 0); # P4 -tx_msbswap, 0b1, (ATTR_POS % 4 == 1); # P5 -tx_msbswap, 0b1, (ATTR_POS % 4 == 2); # P6 -tx_msbswap, 0b1, (ATTR_POS % 4 == 3); # P7 -#tx_msbswap, 0b1, (ATTR_EI_BUS_TX_MSBSWAP == 0x01); +bits, scom_data; +tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); } +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# ________________ ____ ________ ____ _ __ __ ___ __ +# / ____/ ____/ __ \ / __ )__ __/ __/ __/__ _____ / __ \____ ______(_) /___ __ / |/ /___ ______/ /__ +# / / __/ / / /_/ / / __ / / / / /_/ /_/ _ \/ ___/ / /_/ / __ `/ ___/ / __/ / / / / /|_/ / __ `/ ___/ //_/ +# / /_/ / /___/ _, _/ / /_/ / /_/ / __/ __/ __/ / / ____/ /_/ / / / / /_/ /_/ / / / / / /_/ (__ ) ,< +# \____/\____/_/ |_| /_____/\__,_/_/ /_/ \___/_/ /_/ \__,_/_/ /_/\__/\__, / /_/ /_/\__,_/____/_/|_| +# /____/ +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** +# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. +# 0x800???0002011E3F +# This is applied to all configured clkgrp's via chiplet targetting +scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { +bits, scom_data; +rx_pg_fir_err_mask_gcr_buff, 0b1; +} +scom 0x800.0b(tx_fir_mask_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) { +bits, scom_data; +tx_pg_fir_err_mask_gcr_buff, 0b1; +} +scom 0x800.0b(rx_fir_mask_pb)(rx_grp0)(lane_na).0x(cn_gcr_addr) { +bits, scom_data; +rx_pb_fir_err_mask_gcr_buff0, 0b1; +rx_pb_fir_err_mask_gcr_buff1, 0b1; +rx_pb_fir_err_mask_gcr_buff2, 0b1; +} + +# Mask off all rx and tx parity errors in the fir register +scom 0x02010403 { +scom_data; +0xC000000000000000; +} ############################################################################################ # END OF FILE diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile index fa924880d..3e2abbaa6 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen.dmi.scom.initfile,v 1.8 2013/02/04 17:22:52 thomsen Exp $ +#-- $Id: cen.dmi.scom.initfile,v 1.11 2013/03/20 18:11:01 jgrell Exp $ #################################################################### @@ -7,13 +7,14 @@ ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb ## -## Created on Thu Jan 24 14:48:19 EST 2013, by derrin +## Created on Wed Mar 20 11:03:01 CDT 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs13011000| mbs |01-10-13| Added rx_prot_speed_slct and rx_c4_sel ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 @@ -59,37 +60,37 @@ SyntaxVersion = 1 #################################################################### include edi.io.define + define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; + define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; + -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB -scom 0x800F1C000201043F { - bits, scom_data, expr; - tx_zcal_p_4x, 0b00100, any; -} - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB -scom 0x800F2C000201043F { - bits, scom_data, expr; - tx_zcal_sm_max_val, 0b1000110, any; - tx_zcal_sm_min_val, 0b0010101, any; -} #RX.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B78000201043F { bits, scom_data, expr; - rx_amin_cfg, 0b111, any; - rx_anap_cfg, 0b10, any; - rx_h1_cfg, 0b01, any; - rx_peak_cfg, 0b10, any; + rx_amin_cfg, 0b111 , def_IS_HW; + rx_amin_cfg, 0b000 , def_IS_VBU; + rx_anap_cfg, 0b10 , def_IS_HW; + rx_anap_cfg, 0b00 , def_IS_VBU; + rx_h1_cfg, 0b01 , def_IS_HW; + rx_h1_cfg, 0b00 , def_IS_VBU; + rx_peak_cfg, 0b10 , def_IS_HW; + rx_peak_cfg, 0b00 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B80000201043F { bits, scom_data, expr; - rx_ber_cfg, 0b100, any; - rx_dac_bo_cfg, 0b100, any; - rx_ddc_cfg, 0b10, any; - rx_init_tmr_cfg, 0b111, any; - rx_prot_cfg, 0b10, any; + rx_ber_cfg, 0b100 , def_IS_HW; + rx_ber_cfg, 0b000 , def_IS_VBU; + rx_dac_bo_cfg, 0b100 , def_IS_HW; + rx_dac_bo_cfg, 0b000 , def_IS_VBU; + rx_ddc_cfg, 0b10 , def_IS_HW; + rx_ddc_cfg, 0b00 , def_IS_VBU; + rx_init_tmr_cfg, 0b111 , def_IS_HW; + rx_init_tmr_cfg, 0b000 , def_IS_VBU; + rx_prot_cfg, 0b10 , def_IS_HW; + rx_prot_cfg, 0b00 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG @@ -113,18 +114,33 @@ scom 0x800AE0000201043F { rx_dyn_rpr_err_cntr2_duration, 0b0111, any; } +#RX.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG +scom 0x800A80000201043F { + bits, scom_data, expr; + rx_eo_converged_end_count, 0b0111 , def_IS_HW; + rx_eo_converged_end_count, 0b0011 , def_IS_VBU; +} + #RX.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG scom 0x800A38000201043F { bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1, any; - rx_eo_enable_ctle_cal, 0b1, any; - rx_eo_enable_ddc, 0b1, any; - rx_eo_enable_dfe_h1_cal, 0b1, any; + rx_eo_enable_ber_test, 0b1 , def_IS_HW; + rx_eo_enable_ber_test, 0b0 , def_IS_VBU; + rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; + rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; + rx_eo_enable_ddc, 0b1 , def_IS_HW; + rx_eo_enable_ddc, 0b0 , def_IS_VBU; + rx_eo_enable_dfe_h1_cal, 0b1 , def_IS_HW; + rx_eo_enable_dfe_h1_cal, 0b0 , def_IS_VBU; rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_h1ap_tweak, 0b1, any; - rx_eo_enable_latch_offset_cal, 0b1, any; - rx_eo_enable_result_check, 0b1, any; - rx_eo_enable_vga_cal, 0b1, any; + rx_eo_enable_h1ap_tweak, 0b1 , def_IS_HW; + rx_eo_enable_h1ap_tweak, 0b0 , def_IS_VBU; + rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; + rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; + rx_eo_enable_result_check, 0b1 , def_IS_HW; + rx_eo_enable_result_check, 0b0 , def_IS_VBU; + rx_eo_enable_vga_cal, 0b1 , def_IS_HW; + rx_eo_enable_vga_cal, 0b0 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_FENCE_PG @@ -168,73 +184,124 @@ scom 0x800930000201043F { #RX.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG scom 0x8009C0000201043F { bits, scom_data, expr; - rx_c4_sel, 0b00, any; - rx_prot_speed_slct, 0b1, any; + rx_c4_sel, 0b00 , def_IS_HW; + rx_c4_sel, 0b11 , def_IS_VBU; + rx_prot_speed_slct, 0b1 , def_IS_HW; + rx_prot_speed_slct, 0b0 , def_IS_VBU; +} + +#RX.RXCTL.RX_CTL_REGS.RX_MODE1_PP +scom 0x800B08000201043F { + bits, scom_data, expr; + rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; + rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG scom 0x800AB8000201043F { bits, scom_data, expr; - rx_rc_enable_ber_test, 0b1, any; - rx_rc_enable_ctle_cal, 0b1, any; - rx_rc_enable_ddc, 0b1, any; - rx_rc_enable_dfe_h1_cal, 0b1, any; - rx_rc_enable_h1ap_tweak, 0b1, any; - rx_rc_enable_latch_offset_cal, 0b1, any; - rx_rc_enable_result_check, 0b1, any; - rx_rc_enable_vga_cal, 0b1, any; + rx_rc_enable_ber_test, 0b1 , def_IS_HW; + rx_rc_enable_ber_test, 0b0 , def_IS_VBU; + rx_rc_enable_ctle_cal, 0b1 , def_IS_HW; + rx_rc_enable_ctle_cal, 0b0 , def_IS_VBU; + rx_rc_enable_ddc, 0b1 , def_IS_HW; + rx_rc_enable_ddc, 0b0 , def_IS_VBU; + rx_rc_enable_dfe_h1_cal, 0b1 , def_IS_HW; + rx_rc_enable_dfe_h1_cal, 0b0 , def_IS_VBU; + rx_rc_enable_h1ap_tweak, 0b1 , def_IS_HW; + rx_rc_enable_h1ap_tweak, 0b0 , def_IS_VBU; + rx_rc_enable_latch_offset_cal, 0b1 , def_IS_HW; + rx_rc_enable_latch_offset_cal, 0b0 , def_IS_VBU; + rx_rc_enable_result_check, 0b1 , def_IS_HW; + rx_rc_enable_result_check, 0b0 , def_IS_VBU; + rx_rc_enable_vga_cal, 0b1 , def_IS_HW; + rx_rc_enable_vga_cal, 0b0 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP scom 0x800B90000201043F { bits, scom_data, expr; - rx_recal_timeout_sel_b, 0b0100, any; + rx_recal_timeout_sel_b, 0b0100 , def_IS_HW; + rx_recal_timeout_sel_b, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B98000201043F { bits, scom_data, expr; - rx_recal_timeout_sel_h, 0b1011, any; + rx_recal_timeout_sel_h, 0b1011 , def_IS_HW; + rx_recal_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA0000201043F { bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b1011, any; - rx_recal_timeout_sel_j, 0b1011, any; - rx_recal_timeout_sel_k, 0b1011, any; + rx_recal_timeout_sel_i, 0b1011 , def_IS_HW; + rx_recal_timeout_sel_i, 0b1000 , def_IS_VBU; + rx_recal_timeout_sel_j, 0b1011 , def_IS_HW; + rx_recal_timeout_sel_j, 0b1000 , def_IS_VBU; + rx_recal_timeout_sel_k, 0b1011 , def_IS_HW; + rx_recal_timeout_sel_k, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SCOPE_CNTL_PP scom 0x800BC0000201043F { bits, scom_data, expr; - rx_scope_control, 0b01, any; + rx_scope_control, 0b01 , def_IS_HW; + rx_scope_control, 0b00 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B60000201043F { bits, scom_data, expr; - rx_servo_timeout_sel_b, 0b1000, any; + rx_servo_timeout_sel_b, 0b1000 , def_IS_HW; + rx_servo_timeout_sel_b, 0b1010 , def_IS_VBU; + rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; + rx_servo_timeout_sel_d, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B68000201043F { bits, scom_data, expr; - rx_servo_timeout_sel_h, 0b1011, any; + rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; + rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP scom 0x800B70000201043F { bits, scom_data, expr; - rx_servo_timeout_sel_i, 0b1101, any; - rx_servo_timeout_sel_j, 0b1101, any; - rx_servo_timeout_sel_k, 0b1101, any; + rx_servo_timeout_sel_i, 0b1011 , def_IS_HW; + rx_servo_timeout_sel_i, 0b1000 , def_IS_VBU; + rx_servo_timeout_sel_j, 0b1100 , def_IS_HW; + rx_servo_timeout_sel_j, 0b1000 , def_IS_VBU; + rx_servo_timeout_sel_k, 0b1101 , def_IS_HW; + rx_servo_timeout_sel_k, 0b1000 , def_IS_VBU; +} + +#RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG +scom 0x800910000201043F { + bits, scom_data, expr; + rx_eo_amp_timeout_sel, 0b111 , def_IS_HW; + rx_eo_amp_timeout_sel, 0b110 , def_IS_VBU; + rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; + rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; + rx_eo_ddc_timeout_sel, 0b111 , def_IS_HW; + rx_eo_ddc_timeout_sel, 0b110 , def_IS_VBU; + rx_eo_h1ap_timeout_sel, 0b111 , def_IS_HW; + rx_eo_h1ap_timeout_sel, 0b110 , def_IS_VBU; + rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; + rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG scom 0x800898000201043F { bits, scom_data, expr; + rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; + rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; + rx_ds_timeout_sel, 0b110 , def_IS_HW; + rx_ds_timeout_sel, 0b010 , def_IS_VBU; rx_sls_timeout_sel, 0b001, any; + rx_wt_timeout_sel, 0b111 , def_IS_HW; + rx_wt_timeout_sel, 0b011 , def_IS_VBU; } #RX.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG @@ -253,8 +320,10 @@ scom 0x800958000201043F { #RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A30000201043F { bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b001, any; - rx_wt_cu_pll_reset, 0b0, any; + rx_wt_cu_pll_pgooddly, 0b001 , def_IS_HW; + rx_wt_cu_pll_pgooddly, 0b000 , def_IS_VBU; + rx_wt_cu_pll_reset, 0b0 , def_IS_HW; + rx_wt_cu_pll_reset, 0b1 , def_IS_VBU; } #RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index 5e88444f8..0571ce3b7 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -107,8 +107,8 @@ if ($SYSNAME eq "TULETA") { $DmiRefClockSwizzle[4] = 7; $DmiRefClockSwizzle[5] = 6; - $DmiRefClockSwizzle[6] = 5; - $DmiRefClockSwizzle[7] = 4; + $DmiRefClockSwizzle[6] = 4; + $DmiRefClockSwizzle[7] = 5; } open (FH, "<$mrwdir/${sysname}-system-policy.xml") || |