diff options
author | Joe McGill <jmcgill@us.ibm.com> | 2017-10-27 18:48:39 -0500 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-12-22 13:27:42 -0500 |
commit | 63167adf8994c5b89f5a52d0a1a81e84a91b7f1e (patch) | |
tree | 2ee20cb5006af904c17114ad0ec444d112109b19 /src | |
parent | d2b876356f5441e7be94c434952c25826e929370 (diff) | |
download | talos-hostboot-63167adf8994c5b89f5a52d0a1a81e84a91b7f1e.tar.gz talos-hostboot-63167adf8994c5b89f5a52d0a1a81e84a91b7f1e.zip |
MCD disable workaround for HW423589 (option1)
chip_ec_attributes.xml
add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need
MCD disable for HW423589 (applied to Nimbus EC20 and 22+)
p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scan.initfile
p9.l3.scan.initfile
p9.mmu.scom.initfile
p9.ncu.scan.initfile
p9.npu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_pcie_config.C
set unit scope disable dials
p9_sbe_scominit.C
p9_pm_pba_init.C
set PBA unit scope disable dial
p9_pm_set_homer_bar.C
change PBA0 default command scope from GROUP to NODAL
p9.fbc.ab_hp.scom.initfile
disable group master setup
p9_setup_bars.C
p9_setup_bars_defs.H
skip MCD setup for HW423589_OPTION1
Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48964
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
13 files changed, 379 insertions, 43 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C index a5bc32cad..2d7e7be05 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C @@ -133,6 +133,18 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target<fapi2::TARGET_TYPE_CAPP>& TGT0 l_scom_buffer.insert<25, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_G_ON = 0x1; + l_scom_buffer.insert<4, 1, 63, uint64_t>(l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_G_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<3, 1, 63, uint64_t>(l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_DISABLE_VG_NOT_SYS_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x2010818ull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C index 376d88de4..e19f3f653 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ab_hp_scom.C @@ -29,8 +29,8 @@ using namespace fapi2; -constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_2 = 2; constexpr uint64_t literal_3 = 3; constexpr uint64_t literal_4 = 4; @@ -58,6 +58,9 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); fapi2::ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP_Type l_TGT0_ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP, TGT0, l_TGT0_ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP)); + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, TGT0, + l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1)); fapi2::ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_Type l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_MASTER_CHIP, TGT0, l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP)); fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE_Type l_TGT1_ATTR_PROC_FABRIC_SMP_OPTICS_MODE; @@ -138,7 +141,8 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ l_scom_buffer.insert<1, 1, 61, uint64_t>(l_PB_COM_PB_CFG_TM_MASTER_NEXT_OFF ); } - if ((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE)) + if (((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE) + && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 == literal_0))) { constexpr auto l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON = 0x7; l_scom_buffer.insert<2, 1, 61, uint64_t>(l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON ); @@ -1182,7 +1186,8 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ l_scom_buffer.insert<1, 1, 62, uint64_t>(l_PB_COM_PB_CFG_TM_MASTER_NEXT_OFF ); } - if ((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE)) + if (((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE) + && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 == literal_0))) { constexpr auto l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON = 0x7; l_scom_buffer.insert<2, 1, 62, uint64_t>(l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON ); @@ -2226,7 +2231,8 @@ fapi2::ReturnCode p9_fbc_ab_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ l_scom_buffer.insert<1, 1, 63, uint64_t>(l_PB_COM_PB_CFG_TM_MASTER_NEXT_OFF ); } - if ((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE)) + if (((l_TGT0_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP == fapi2::ENUM_ATTR_PROC_FABRIC_GROUP_MASTER_CHIP_TRUE) + && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 == literal_0))) { constexpr auto l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON = 0x7; l_scom_buffer.insert<2, 1, 63, uint64_t>(l_PB_COM_PB_CFG_CHG_RATE_GP_MASTER_NEXT_ON ); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C index a0a9b07b7..0391b1d3d 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C @@ -111,6 +111,18 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<49, 1, 63, uint64_t>(literal_0 ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_G_ON = 0x1; + l_scom_buffer.insert<47, 1, 63, uint64_t>(l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_G_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<46, 1, 63, uint64_t>(l_INT_INT_CQ_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x5013021ull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C index 04bed54b1..d8a01bcdc 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C @@ -122,6 +122,30 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<8, 3, 61, uint64_t>(literal_0x3 ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x5012c15ull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C index f239a1cbb..c88ac0be5 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C @@ -93,6 +93,9 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& || (l_TGT0_ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE[literal_3] == fapi2::ENUM_ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE_NV)); fapi2::ATTR_CHIP_EC_FEATURE_HW372457_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW372457; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW372457, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW372457)); + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, TGT0, + l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1)); fapi2::ATTR_CHIP_EC_FEATURE_HW410625_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW410625, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625)); fapi2::ATTR_CHIP_EC_FEATURE_HW364887_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW364887; @@ -134,11 +137,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -277,11 +286,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -412,10 +427,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) @@ -591,10 +612,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -793,11 +820,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -1017,10 +1050,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -1267,11 +1306,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -1429,11 +1474,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -1591,11 +1642,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -1753,11 +1810,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -1984,10 +2047,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) @@ -2002,10 +2071,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if ((l_def_NVLINK_ACTIVE == literal_1)) @@ -2205,11 +2280,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -2340,10 +2421,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) @@ -2519,10 +2606,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -2724,10 +2817,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) @@ -2742,10 +2841,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if ((l_def_NVLINK_ACTIVE == literal_1)) @@ -3026,10 +3131,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } } if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -3387,11 +3498,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -3606,11 +3723,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -3830,11 +3953,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); @@ -3999,11 +4128,17 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<50, 1, 63, uint64_t>(literal_0b0 ); } - if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0)) + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW410625 != literal_0) + || (l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0))) { l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); } + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW423589_OPTION1 != literal_0)) + { + l_scom_buffer.insert<7, 1, 63, uint64_t>(literal_0x1 ); + } + if ((l_def_NVLINK_ACTIVE == literal_1)) { l_scom_buffer.insert<52, 1, 63, uint64_t>(literal_0x1 ); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C index b486e2090..00479d551 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C @@ -663,6 +663,54 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<60, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<9, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_GROUP_ON = 0x1; + l_scom_buffer.insert<13, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_GROUP_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<10, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_WR_DISABLE_VG_NOT_SYS_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_VG_NOT_SYS_ON = 0x1; + l_scom_buffer.insert<14, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_UMAC_RD_DISABLE_VG_NOT_SYS_ON ); + } + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_RD_GO_M_QOS_ON = 0x1; l_scom_buffer.insert<22, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_RD_GO_M_QOS_ON ); constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_ADDR_BAR_MODE_OFF = 0x0; diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C index 193d6d1bf..c45810d86 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C @@ -153,6 +153,31 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& l_scom_buffer.insert<20, 8, 56, uint64_t>(literal_0xFC ); l_scom_buffer.insert<28, 8, 56, uint64_t>(literal_0xFC ); + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_WR_ON = 0x1; + l_scom_buffer.insert<1, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_WR_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_RD_ON = 0x1; + l_scom_buffer.insert<5, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_G_RD_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_WR_ON = 0x1; + l_scom_buffer.insert<2, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_WR_ON ); + } + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) ) + { + constexpr auto l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_RD_ON = 0x1; + l_scom_buffer.insert<6, 1, 63, uint64_t>(l_VA_VA_SOUTH_VA_EG_EG_SCF_DISABLE_VG_RD_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x301184eull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C index 9026870ba..d9c9ebaa7 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C @@ -88,6 +88,7 @@ fapi2::ReturnCode p9_pcie_config( fapi2::ATTR_PROC_PCIE_BAR_SIZE_Type l_bar_sizes; fapi2::ATTR_CHIP_EC_FEATURE_HW363246_Type l_hw363246; fapi2::ATTR_CHIP_EC_FEATURE_HW410503_Type l_hw410503; + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1_Type l_hw423589_option1; fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; @@ -196,6 +197,7 @@ fapi2::ReturnCode p9_pcie_config( // Set bits 34:35 = 0b11 Set P9 Style cache-inject behavior // Set bits 46:48 = 0b011 Set P9 Style cache-inject rate, 1/16 cycles // Set bit 60 = 0b1 only if PEC is bifurcated or trifurcated. + // if HW423589_option1, set Disable Group Scope (r/w) and Use Vg(sys) at Vg scope FAPI_TRY(fapi2::getScom(l_pec_chiplet, PEC_PBCQHWCFG_REG, l_buf), "Error from getScom (PEC_PBCQHWCFG_REG)"); l_buf.insertFromRight<PEC_PBCQHWCFG_REG_HANG_POLL_SCALE, @@ -206,6 +208,20 @@ fapi2::ReturnCode p9_pcie_config( PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN>(PEC_PBCQ_HWCFG_HANG_PE_SCALE); l_buf.setBit<PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE>(); l_buf.setBit<PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, + i_target, + l_hw423589_option1), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION1)"); + + if (l_hw423589_option1) + { + l_buf.setBit<PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP>(); + l_buf.setBit<PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP>(); + l_buf.setBit<PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG>(); + l_buf.setBit<PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG>(); + } + l_buf.insertFromRight<PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE, PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN>( PEC_PBCQ_HWCFG_P9_CACHE_INJ_MODE); diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C index 25f5281a3..819dea211 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C @@ -95,6 +95,11 @@ p9_setup_bars_build_chip_info(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& io_chip_info.hw423589_option2), "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, + i_target, + io_chip_info.hw423589_option1), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION1)"); + fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; @@ -1247,17 +1252,20 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) "Error from p9_setup_bars_npu"); // MCD - if (l_chip_info.extended_addressing_mode && l_chip_info.hw423589_option2) + if (!l_chip_info.hw423589_option1) { - FAPI_TRY(p9_setup_bars_mcd_HW423589_OPTION2(i_target, - FAPI_SYSTEM, - l_chip_info), - "Error from p9_setup_bars_mcd_HW423589_OPTION2"); - } - else - { - FAPI_TRY(p9_setup_bars_mcd(i_target, FAPI_SYSTEM, l_chip_info), - "Error from p9_setup_bars_mcd"); + if (l_chip_info.extended_addressing_mode && l_chip_info.hw423589_option2) + { + FAPI_TRY(p9_setup_bars_mcd_HW423589_OPTION2(i_target, + FAPI_SYSTEM, + l_chip_info), + "Error from p9_setup_bars_mcd_HW423589_OPTION2"); + } + else + { + FAPI_TRY(p9_setup_bars_mcd(i_target, FAPI_SYSTEM, l_chip_info), + "Error from p9_setup_bars_mcd"); + } } // INT diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H index 84500f122..ebf4682af 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H @@ -295,6 +295,7 @@ struct p9_setup_bars_chip_info uint64_t base_address_mmio; std::vector<p9_setup_bars_addr_range> ranges; uint8_t hw423589_option2; + uint8_t hw423589_option1; uint8_t extended_addressing_mode; }; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C index 2ab615c97..51520e0b0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pba_init.C @@ -285,13 +285,24 @@ fapi2::ReturnCode pba_init( uint8_t l_attr_pbax_groupid; uint8_t l_attr_pbax_chipid; uint8_t l_attr_pbax_broadcast_vector; + uint8_t l_hw423589_option1; - // Clear PBA CONFIG. This register is cleared as there are no chicken - // switches that need to be disabled. All other bits are set by OCC Firmware - FAPI_TRY(fapi2::putScom(i_target, PU_PBACFG, l_data64), - "Failed to clear PBA_CONFIG"); + // Setup PBA CONFIG + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, + i_target, + l_hw423589_option1)); + l_data64.flush<0>(); + + if (l_hw423589_option1) + { + l_data64.setBit<PU_PBACFG_CHSW_DIS_GROUP_SCOPE>(); + } + + FAPI_INF("Resetting PBACFG with value = 0x%16llX", uint64_t(l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_PBACFG, l_data64)); // Clear the PBA FIR + l_data64.flush<0>(); FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIR, l_data64), "Failed to clear PBA_FIR"); @@ -396,13 +407,13 @@ fapi2::ReturnCode pba_reset( PU_PBASLVCTL1_SCOM, PU_PBASLVCTL2_SCOM, PU_PBAFIR, - PU_PBACFG, PU_PBAERRRPT0 }; FAPI_IMP(">> pba_reset ..."); fapi2::buffer<uint64_t> l_data64; + uint8_t l_hw423589_option1; // Stop the BCDE and BCUE FAPI_TRY(pba_bc_stop(i_target), "pba_bc_stop() detected an error"); @@ -418,10 +429,24 @@ fapi2::ReturnCode pba_reset( } // Perform non-zero reset operations + // set PBACFG register + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, + i_target, + l_hw423589_option1)); + l_data64.flush<0>(); + + if (l_hw423589_option1) + { + l_data64.setBit<PU_PBACFG_CHSW_DIS_GROUP_SCOPE>(); + } + + FAPI_INF("Resetting PBACFG with value = 0x%16llX", uint64_t(l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_PBACFG, l_data64)); + // Reset PBAX errors via Configuration Register // Bit 2: PBAXCFG_SND_RESET // Bit 3: PBAXCFG_RCV_RESET - l_data64.setBit<2, 2>(); + l_data64.flush<0>().setBit<2, 2>(); FAPI_INF("Resetting PBAX errors via PBAX config register 0x%08llX with " "value = 0x%16llX", PU_PBAXCFG_SCOM, uint64_t(l_data64)); FAPI_TRY(fapi2::putScom(i_target, PU_PBAXCFG_SCOM, l_data64)); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_set_homer_bar.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_set_homer_bar.C index 40782bf0e..4c01367ca 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_set_homer_bar.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_set_homer_bar.C @@ -151,7 +151,7 @@ p9_pm_set_homer_bar( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_targe PBA_BAR0, i_mem_bar, i_mem_size, - p9pba::GROUP, 0); + p9pba::LOCAL_NODAL, 0); fapi2::current_err = l_rc; diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index e1e78a0a5..eea51af47 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5990,4 +5990,28 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW423589_OPTION1</id> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <description> + Disable MCD to workaround coherency issue HW423589 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> |