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authorLouis Stermole <stermole@us.ibm.com>2019-04-30 13:57:29 -0400
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-05-11 09:23:28 -0500
commit5fd2903850cb4329f8e1f4beb9f8cc94e2d4b3fe (patch)
tree504d51f6ae978f464ca90082409327deecae38ea /src
parente827b625b481712e1102ad5d277c6736584da76e (diff)
downloadtalos-hostboot-5fd2903850cb4329f8e1f4beb9f8cc94e2d4b3fe.tar.gz
talos-hostboot-5fd2903850cb4329f8e1f4beb9f8cc94e2d4b3fe.zip
Add debug params to exp_check_for_ready_wrap
Add parameters to specify number of attempts and delay between attempts for EXP_FW_STATUS commands Change-Id: I61e664d58352f392e176e132a7161d302d69c619 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76752 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76898 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C28
-rw-r--r--src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H49
2 files changed, 49 insertions, 28 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C
index 54c67f1b3..94a3a383e 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C
@@ -37,7 +37,6 @@
#include <lib/shared/exp_defaults.H>
#include <exp_check_for_ready.H>
#include <lib/i2c/exp_i2c.H>
-#include <generic/memory/lib/utils/poll.H>
#include <generic/memory/mss_git_data_helper.H>
extern "C"
@@ -51,32 +50,7 @@ extern "C"
{
mss::display_git_commit_info("exp_check_for_ready");
- // Using default parameters
- mss::poll_parameters l_poll_params;
-
- // From MSCC explorer firmware arch spec
- // 4.1.5: After power-up, the Explorer Chip will respond with NACK to all incoming I2C requests
- // from the HOST until the I2C slave interface is ready to receive commands.
- FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool
- {
- return mss::exp::i2c::is_ready(i_target) == fapi2::FAPI2_RC_SUCCESS;
- }),
- fapi2::MSS_EXP_I2C_POLLING_TIMEOUT().
- set_TARGET(i_target),
- "Failed to see an ACK from I2C -- polling timeout on %s",
- mss::c_str(i_target) );
-
- // We send the EXP_FW_STATUS command as a sanity check to see if it returns SUCCESS
- FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool
- {
- return mss::exp::i2c::fw_status(i_target) == fapi2::FAPI2_RC_SUCCESS;
- }),
- fapi2::MSS_EXP_STATUS_POLLING_TIMEOUT().
- set_TARGET(i_target),
- "Failled to see a successful return code -- polling timeout on %s",
- mss::c_str(i_target) );
-
- return fapi2::FAPI2_RC_SUCCESS;
+ FAPI_TRY(mss::exp::i2c::exp_check_for_ready_helper(i_target));
fapi_try_exit:
return fapi2::current_err;
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H
index d834b102a..8852e95ce 100644
--- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H
+++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -43,6 +43,7 @@
#include <lib/i2c/exp_i2c_fields.H>
#include <generic/memory/lib/utils/pos.H>
#include <generic/memory/lib/utils/endian_utils.H>
+#include <generic/memory/lib/utils/poll.H>
namespace mss
{
@@ -187,6 +188,52 @@ inline fapi2::ReturnCode is_ready(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CH
}
///
+/// @brief Helper function for exp_check_for_ready
+/// @param[in] i_target the controller
+/// @param[in] i_poll_count the number of times to run the fw_status command (default = 50)
+/// @param[in] i_delay delay in ns between fw_status command attempts (default = 200ns)
+/// @return FAPI2_RC_SUCCESS iff ok
+///
+inline fapi2::ReturnCode exp_check_for_ready_helper(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target,
+ const uint64_t i_poll_count = DEFAULT_POLL_LIMIT,
+ const uint64_t i_delay = 200)
+{
+ // Using using default parameters from class, with overrides for delay and poll_count
+ mss::poll_parameters l_poll_params(DELAY_10NS,
+ 200,
+ i_delay,
+ 200,
+ i_poll_count);
+
+ // From MSCC explorer firmware arch spec
+ // 4.1.5: After power-up, the Explorer Chip will respond with NACK to all incoming I2C requests
+ // from the HOST until the I2C slave interface is ready to receive commands.
+ FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool
+ {
+ return mss::exp::i2c::is_ready(i_target) == fapi2::FAPI2_RC_SUCCESS;
+ }),
+ fapi2::MSS_EXP_I2C_POLLING_TIMEOUT().
+ set_TARGET(i_target),
+ "Failed to see an ACK from I2C -- polling timeout on %s",
+ mss::c_str(i_target) );
+
+ // We send the EXP_FW_STATUS command as a sanity check to see if it returns SUCCESS
+ FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool
+ {
+ return mss::exp::i2c::fw_status(i_target) == fapi2::FAPI2_RC_SUCCESS;
+ }),
+ fapi2::MSS_EXP_STATUS_POLLING_TIMEOUT().
+ set_TARGET(i_target),
+ "Failed to see a successful return code -- polling timeout on %s",
+ mss::c_str(i_target) );
+
+ return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
+ return fapi2::current_err;
+}
+
+///
/// @brief Perform a register write operation on the given OCMB chip
/// @param[in] i_target the OCMB target
/// @param[in] i_addr The translated address on the OCMB chip
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