diff options
author | Matt Derksen <mderkse1@us.ibm.com> | 2019-04-02 16:59:58 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-04-10 11:39:02 -0500 |
commit | 5e672904032cd2be8c994c09a964fba373527f38 (patch) | |
tree | 74aace8f41d5740059dd72fa490694cdbe206173 /src | |
parent | 8941c2cd6251da7e090ef18201f6e3a0a8f5a597 (diff) | |
download | talos-hostboot-5e672904032cd2be8c994c09a964fba373527f38.tar.gz talos-hostboot-5e672904032cd2be8c994c09a964fba373527f38.zip |
Remove unused VPD sections from axone pnor layout
Remove Centaur VPD and DIMM JEDEC VPD sections.
Change-Id: I34b8d2f6cc3e8f94712405c44b3410a6b09a6d79
RTC:207995
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75425
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Glenn Miles <milesg@ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/build/buildpnor/pnorLayoutAxone.xml | 66 | ||||
-rwxr-xr-x | src/build/mkrules/hbfw/img/makefile | 16 |
2 files changed, 32 insertions, 50 deletions
diff --git a/src/build/buildpnor/pnorLayoutAxone.xml b/src/build/buildpnor/pnorLayoutAxone.xml index 4420b8cc1..150bab112 100644 --- a/src/build/buildpnor/pnorLayoutAxone.xml +++ b/src/build/buildpnor/pnorLayoutAxone.xml @@ -94,36 +94,18 @@ Layout Description <ecc/> </section> <section> - <description>DIMM JEDEC (288K)</description> - <eyeCatch>DJVPD</eyeCatch> - <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x31000</physicalOffset> - <physicalRegionSize>0x48000</physicalRegionSize> - <side>sideless</side> - <ecc/> - </section> - <section> <description>Module VPD (576K)</description> <eyeCatch>MVPD</eyeCatch> <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x79000</physicalOffset> + <physicalOffset>0x31000</physicalOffset> <physicalRegionSize>0x90000</physicalRegionSize> <side>sideless</side> <ecc/> </section> <section> - <description>Centaur VPD (288K)</description> - <eyeCatch>CVPD</eyeCatch> - <!--NOTE: MUST update standalone.simics if offset changes --> - <physicalOffset>0x109000</physicalOffset> - <physicalRegionSize>0x48000</physicalRegionSize> - <side>sideless</side> - <ecc/> - </section> - <section> <description>Hostboot Base (1MB)</description> <eyeCatch>HBB</eyeCatch> - <physicalOffset>0x151000</physicalOffset> + <physicalOffset>0xC1000</physicalOffset> <physicalRegionSize>0x100000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -132,7 +114,7 @@ Layout Description <section> <description>Hostboot Data (2MB)</description> <eyeCatch>HBD</eyeCatch> - <physicalOffset>0x251000</physicalOffset> + <physicalOffset>0x1C1000</physicalOffset> <physicalRegionSize>0x200000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -141,7 +123,7 @@ Layout Description <section> <description>Hostboot Extended image (14.22MB w/o ECC)</description> <eyeCatch>HBI</eyeCatch> - <physicalOffset>0x451000</physicalOffset> + <physicalOffset>0x3C1000</physicalOffset> <physicalRegionSize>0x1000000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -150,7 +132,7 @@ Layout Description <section> <description>SBE-IPL (Staging Area) (752K)</description> <eyeCatch>SBE</eyeCatch> - <physicalOffset>0x1451000</physicalOffset> + <physicalOffset>0x13C1000</physicalOffset> <physicalRegionSize>0xBC000</physicalRegionSize> <sha512perEC/> <sha512Version/> @@ -160,7 +142,7 @@ Layout Description <section> <description>HCODE Ref Image (1.125MB)</description> <eyeCatch>HCODE</eyeCatch> - <physicalOffset>0x150D000</physicalOffset> + <physicalOffset>0x147D000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -169,7 +151,7 @@ Layout Description <section> <description>Hostboot Runtime Services for Sapphire (7.0MB)</description> <eyeCatch>HBRT</eyeCatch> - <physicalOffset>0x162D000</physicalOffset> + <physicalOffset>0x159D000</physicalOffset> <physicalRegionSize>0x700000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -178,7 +160,7 @@ Layout Description <section> <description>Payload (19.875MB)</description> <eyeCatch>PAYLOAD</eyeCatch> - <physicalOffset>0x1D2D000</physicalOffset> + <physicalOffset>0x1C9D000</physicalOffset> <physicalRegionSize>0x13E0000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -187,7 +169,7 @@ Layout Description <section> <description>Special PNOR Test Space (36K)</description> <eyeCatch>TEST</eyeCatch> - <physicalOffset>0x310D000</physicalOffset> + <physicalOffset>0x307D000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <testonly/> <side>sideless</side> @@ -198,7 +180,7 @@ Layout Description from skipping header. Signing is forced in build pnor phase --> <description>Special PNOR Test Space with Header (36K)</description> <eyeCatch>TESTRO</eyeCatch> - <physicalOffset>0x3116000</physicalOffset> + <physicalOffset>0x3086000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <testonly/> @@ -209,7 +191,7 @@ Layout Description <section> <description>Hostboot Bootloader (28K)</description> <eyeCatch>HBBL</eyeCatch> - <physicalOffset>0x311F000</physicalOffset> + <physicalOffset>0x308F000</physicalOffset> <!-- Physical Size includes Header rounded to ECC valid size --> <!-- Max size of actual HBBL content is 20K and 22.5K with ECC --> <physicalRegionSize>0x7000</physicalRegionSize> @@ -220,7 +202,7 @@ Layout Description <section> <description>Global Data (36K)</description> <eyeCatch>GLOBAL</eyeCatch> - <physicalOffset>0x3126000</physicalOffset> + <physicalOffset>0x3096000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -228,7 +210,7 @@ Layout Description <section> <description>Ref Image Ring Overrides (20K)</description> <eyeCatch>RINGOVD</eyeCatch> - <physicalOffset>0x312F000</physicalOffset> + <physicalOffset>0x309F000</physicalOffset> <physicalRegionSize>0x5000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -236,7 +218,7 @@ Layout Description <section> <description>SecureBoot Key Transition Partition (16K)</description> <eyeCatch>SBKT</eyeCatch> - <physicalOffset>0x3134000</physicalOffset> + <physicalOffset>0x30A4000</physicalOffset> <physicalRegionSize>0x4000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -244,7 +226,7 @@ Layout Description <section> <description>OCC Lid (1.125M)</description> <eyeCatch>OCC</eyeCatch> - <physicalOffset>0x3138000</physicalOffset> + <physicalOffset>0x30A8000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -255,7 +237,7 @@ Layout Description <!-- We need 266KB per module sort, going to support 40 tables by default, plus ECC --> <eyeCatch>WOFDATA</eyeCatch> - <physicalOffset>0x3258000</physicalOffset> + <physicalOffset>0x31C8000</physicalOffset> <physicalRegionSize>0x600000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -264,7 +246,7 @@ Layout Description <section> <description>FIRDATA (12K)</description> <eyeCatch>FIRDATA</eyeCatch> - <physicalOffset>0x3858000</physicalOffset> + <physicalOffset>0x37C8000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -272,7 +254,7 @@ Layout Description <section> <description>Memory Data (128K)</description> <eyeCatch>MEMD</eyeCatch> - <physicalOffset>0x385B000</physicalOffset> + <physicalOffset>0x37CB000</physicalOffset> <physicalRegionSize>0x20000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -281,7 +263,7 @@ Layout Description <section> <description>Secureboot Test Load (12K)</description> <eyeCatch>TESTLOAD</eyeCatch> - <physicalOffset>0x387B000</physicalOffset> + <physicalOffset>0x37EB000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -290,7 +272,7 @@ Layout Description <section> <description>Centaur Hw Ref Image (12K)</description> <eyeCatch>CENHWIMG</eyeCatch> - <physicalOffset>0x387E000</physicalOffset> + <physicalOffset>0x37EE000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -299,7 +281,7 @@ Layout Description <section> <description>Secure Boot (144K)</description> <eyeCatch>SECBOOT</eyeCatch> - <physicalOffset>0x3881000</physicalOffset> + <physicalOffset>0x37F1000</physicalOffset> <physicalRegionSize>0x24000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -308,7 +290,7 @@ Layout Description <section> <description>Open CAPI Memory Buffer (OCMB) Firmware (300K)</description> <eyeCatch>OCMBFW</eyeCatch> - <physicalOffset>0x38A5000</physicalOffset> + <physicalOffset>0x3815000</physicalOffset> <physicalRegionSize>0x4B000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -318,7 +300,7 @@ Layout Description <section> <description>HDAT Data (16K)</description> <eyeCatch>HDAT</eyeCatch> - <physicalOffset>0x38F0000</physicalOffset> + <physicalOffset>0x3860000</physicalOffset> <physicalRegionSize>0x4000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -327,7 +309,7 @@ Layout Description <section> <description>Eeprom Cache(512K)</description> <eyeCatch>EECACHE</eyeCatch> - <physicalOffset>0x38F4000</physicalOffset> + <physicalOffset>0x3864000</physicalOffset> <physicalRegionSize>0x80000</physicalRegionSize> <side>sideless</side> <ecc/> diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile index 878c72b96..4adf9bdef 100755 --- a/src/build/mkrules/hbfw/img/makefile +++ b/src/build/mkrules/hbfw/img/makefile @@ -208,16 +208,16 @@ BUILD_TYPE_PARAMS = --build-type fspbuild .endif # Decide which images to use for each PNOR layout -GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,GLOBAL=EMPTY,CVPD=EMPTY,MVPD=EMPTY,DJVPD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY +GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,GLOBAL=EMPTY,MVPD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY GEN_STANDALONE_BIN_FILES = ${GEN_COMMON_BIN_FILES},TEST=EMPTY,TESTRO=EMPTY,TESTLOAD=EMPTY,PAYLOAD=EMPTY,FIRDATA=EMPTY .if (${FAKEPNOR} == "") # Parameters passed into GEN_PNOR_IMAGE_SCRIPT. .if (${PNOR_LAYOUT_SELECTED} == "STANDALONE") - GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P} + GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY .elif(${PNOR_LAYOUT_SELECTED} == "AXONE") GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},EECACHE=EMPTY,MEMD=${${ZZ_MEMD_IMG}:P} .else - GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P} + GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY .endif DEFAULT_PARAMS = --build-all --emit-eccless ${TARGET_TEST:b--test} ${HB_STANDALONE:b--hb-standalone} \ ${CONFIG_SECUREBOOT:b--secureboot} --systemBinFiles ${GEN_DEFAULT_BIN_FILES} \ @@ -476,13 +476,13 @@ gen_system_specific_images: build_sbe_partitions .PMAKE .if (${PNOR_LAYOUT_SELECTED} == "FSP") - HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG} + HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG} .else - HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG} + HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG} .endif -NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG} -CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG} -CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG} +NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG} +CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG} +CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG} AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG},EECACHE=${EECACHE_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG},MEMD=${MEMD_FINAL_IMG} |