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| author | Sangeetha T S <sangeet2@in.ibm.com> | 2016-10-20 01:09:14 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-30 21:44:58 -0400 |
| commit | 58fb5a63867402868431829b1c7aba2b2efddcd7 (patch) | |
| tree | 766b7c89f05560b60bfc84288863ca10d66bb3d7 /src | |
| parent | 565e4d6ae0cdc1ebac22f68de115f0c0a9e1d93c (diff) | |
| download | talos-hostboot-58fb5a63867402868431829b1c7aba2b2efddcd7.tar.gz talos-hostboot-58fb5a63867402868431829b1c7aba2b2efddcd7.zip | |
Host to have access to I2C engines while OCC reset
-Address comments on https://ralgit01.raleigh.ibm.com/gerrit1/#/c/30721
Change-Id: Idd1e9ca648bf4fab89c9627bddaec9c4eb1f77c9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31527
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31528
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C | 8 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C | 8 |
2 files changed, 7 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C index 9feb52b12..ff4fc1ec8 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_init.C @@ -127,7 +127,6 @@ fapi2::ReturnCode pm_init( FAPI_INF("Entering pm_init..."); fapi2::ReturnCode l_rc; - fapi2::buffer<uint64_t> l_data64; // ************************************************************************ // Initialize Cores and Quads @@ -212,13 +211,6 @@ fapi2::ReturnCode pm_init( FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After PGPE initialization")); */ - // Clear the OCC's PIB I2C engine locks. - // All other OCC owned flag bits are retained. - l_data64.setBit<17>().setBit<19>().setBit<21>(); - FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM1, l_data64), - "ERROR: Failed to write to OCC FLAG"); - - // ************************************************************************ // Start OCC PPC405 // ************************************************************************ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C index 62d9b6a75..b9be2b433 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C @@ -124,6 +124,12 @@ fapi2::ReturnCode p9_pm_reset( FAPI_TRY(l_rc, "ERROR: Failed to mask OCC,PBA & CME FIRs."); FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After masking FIRs")); + // Clear the OCC's PIB I2C engine locks. + // All other OCC owned flag bits are retained. + l_data64.setBit<17>().setBit<19>().setBit<21>(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM1, l_data64), + "ERROR: Failed to write to OCC FLAG"); + // ************************************************************************ // Halt the OCC PPC405 and reset it safely // ************************************************************************ @@ -156,7 +162,7 @@ fapi2::ReturnCode p9_pm_reset( // Reset the PSTATE GPE (Bring it to HALT) // ************************************************************************ FAPI_DBG("Executing p9_pm_pstate_gpe_init to reset PGPE"); - /* Enable once the procedure is available + /* TODO: RTC 157096 - Enable once the procedure is available FAPI_EXEC_HWP(l_rc, p9_pm_pstate_gpe_init, i_target, p9pm::PM_RESET); FAPI_TRY(l_rc, "ERROR: Failed to reset PGPE"); FAPI_TRY(p9_pm_glob_fir_trace(i_target, "After reset of PGPE")); |
