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| author | Andre Marin <aamarin@us.ibm.com> | 2017-01-13 11:58:40 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-01-16 10:52:40 -0500 |
| commit | 58457b8e9088159dd7cb91e9bed919fb72b07e49 (patch) | |
| tree | 058fcfac62dafb95235fa12e18907130018892fc /src | |
| parent | f287be6fdc7815cfb0c3b9e72eab3821cd112677 (diff) | |
| download | talos-hostboot-58457b8e9088159dd7cb91e9bed919fb72b07e49.tar.gz talos-hostboot-58457b8e9088159dd7cb91e9bed919fb72b07e49.zip | |
Move SEQ ODT Write Configuration from draminit_training to scominit
Request from lab for debugging ability to overwrite these registers before
running dramint_training.
Change-Id: I4b370422c2d38df4dc4e0c08344a37a0c6687078
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34851
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34861
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H | 4 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C | 12 |
2 files changed, 7 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H index 115e977e4..5d430dbfd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -384,6 +384,7 @@ inline fapi2::ReturnCode reset( const fapi2::Target<T>& i_target ) FAPI_TRY( reset_timing1(i_target) ); FAPI_TRY( reset_timing2(i_target) ); FAPI_TRY( reset_rd_wr_data(i_target) ); + FAPI_TRY( reset_odt_config(i_target) ); fapi_try_exit: return fapi2::current_err; @@ -394,4 +395,3 @@ fapi_try_exit: } // close namespace mss #endif - diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index ac77119aa..b8cdf227a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -130,13 +130,11 @@ extern "C" // The following registers must be configured to the correct operating environment: - // • Section 5.2.5.10 SEQ ODT Write Configuration {0-3} on page 422 - FAPI_TRY( mss::reset_odt_config(p) ); - // These are reset in phy_scominit - // • Section 5.2.6.1 WC Configuration 0 Register on page 434 - // • Section 5.2.6.2 WC Configuration 1 Register on page 436 - // • Section 5.2.6.3 WC Configuration 2 Register on page 438 + // Section 5.2.5.10 SEQ ODT Write Configuration {0-3} on page 422 + // Section 5.2.6.1 WC Configuration 0 Register on page 434 + // Section 5.2.6.2 WC Configuration 1 Register on page 436 + // Section 5.2.6.3 WC Configuration 2 Register on page 438 // Get our rank pairs. FAPI_TRY( mss::rank::get_rank_pairs(p, l_pairs) ); |
