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authorCHRISTINA L. GRAVES <clgraves@us.ibm.com>2017-02-07 18:04:28 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-03-10 16:47:25 -0500
commit57fcd0a64e52325588c8937040418f5ecfd1b76a (patch)
tree3b3afe0eec53e581c277952a96a02d83cf1ddffc /src
parent274fa593dad76e390d1c37129862c4a8dcde4f02 (diff)
downloadtalos-hostboot-57fcd0a64e52325588c8937040418f5ecfd1b76a.tar.gz
talos-hostboot-57fcd0a64e52325588c8937040418f5ecfd1b76a.zip
ADU HWP updates for CI support, performance
adjustments to support long running CI operations ignore autoinc mode for CI ttype include poll for data done prior to final status check ignore ADU operational/data hang reporting correctly report num_granules when running without autoinc performance enhancements: minimize SCOM operations for single shot transfers (15->9) reduce polling delays add simple test program to validate transfer sizes, measure perf Change-Id: Ic1f3890ff40f448fb1143d639d878896e90237fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36086 Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36800 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C145
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H20
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H4
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_build_smp_adu.C4
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C5
5 files changed, 98 insertions, 80 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
index 67c2fbd17..da7486900 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -163,8 +163,9 @@ extern "C"
const uint32_t ALTD_DATA_ECC_MASK = 0xFFFFull;
// ADU operation delay times for HW/sim
- const uint32_t PROC_ADU_UTILS_ADU_HW_NS_DELAY = 100000;
- const uint32_t PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY = 50000;
+ const uint32_t PROC_ADU_UTILS_ADU_OPER_HW_NS_DELAY = 10000;
+ const uint32_t PROC_ADU_UTILS_ADU_OPER_SIM_CYCLE_DELAY = 50000;
+ const uint32_t PROC_ADU_UTILS_ADU_STATUS_HW_NS_DELAY = 100;
const uint32_t PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY = 20000;
//---------------------------------------------------------------------------------
@@ -316,16 +317,14 @@ extern "C"
fapi2::ReturnCode rc;
fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
fapi2::buffer<uint64_t> altd_addr_reg_data(i_address);
- fapi2::buffer<uint64_t> altd_data_reg_data(0x0);
fapi2::buffer<uint64_t> altd_option_reg_data(0x0);
p9_ADU_oper_flag l_myAduFlag;
p9_ADU_oper_flag::OperationType_t l_operType;
p9_ADU_oper_flag::Transaction_size_t l_transSize;
- // Write to the altd_cmd_reg to set the fbc_locked bit
+ //this routine assumes the lock is held by the caller, preserve
+ //this locked state
altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>();
- FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
- "Error writing the lock bit to ALTD_CMD Register");
//Write the address into altd_addr_reg
FAPI_DBG("Write PU_ALTD_ADDR_REG 0x%.16llX, Value 0x%.16llX",
@@ -600,31 +599,28 @@ extern "C"
if (l_accessForceEccReg == true)
{
FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error reading the FORCE_ECC Register");
- }
- //if we want to write the itag bit set it
- if (l_itagMode == true)
- {
- eccIndex++;
- force_ecc_reg_data.setBit<ALTD_DATA_ITAG_BIT>();
- }
+ //if we want to write the itag bit set it
+ if (l_itagMode == true)
+ {
+ eccIndex++;
+ force_ecc_reg_data.setBit<ALTD_DATA_ITAG_BIT>();
+ }
- //if we want to write the ecc data get the data
- if (l_eccMode == true)
- {
- force_ecc_reg_data.insertFromRight < ALTD_DATA_TX_ECC_START_BIT,
- (ALTD_DATA_TX_ECC_END_BIT - ALTD_DATA_TX_ECC_START_BIT) + 1 >
- ((uint64_t)i_write_data[eccIndex]);
- }
+ //if we want to write the ecc data get the data
+ if (l_eccMode == true)
+ {
+ force_ecc_reg_data.insertFromRight < ALTD_DATA_TX_ECC_START_BIT,
+ (ALTD_DATA_TX_ECC_END_BIT - ALTD_DATA_TX_ECC_START_BIT) + 1 >
+ ((uint64_t)i_write_data[eccIndex]);
+ }
- //if we want to overwrite the ecc data
- if (l_overrideEccMode == true)
- {
- force_ecc_reg_data.setBit<ALTD_DATA_TX_ECC_OVERWRITE_BIT>();
- }
+ //if we want to overwrite the ecc data
+ if (l_overrideEccMode == true)
+ {
+ force_ecc_reg_data.setBit<ALTD_DATA_TX_ECC_OVERWRITE_BIT>();
+ }
- if (l_accessForceEccReg == true)
- {
FAPI_TRY(fapi2::putScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error writing to the FORCE_ECC Register");
}
@@ -643,10 +639,30 @@ extern "C"
FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG");
}
- //delay to allow time for the write to go through before we check the status
- FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
- PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
- "fapiDelay error");
+ //If this is a ci operation we want to poll the status register for completion
+ if (i_aduOper.getOperationType() == p9_ADU_oper_flag::CACHE_INHIBIT)
+ {
+ bool l_busyBitStatus = true;
+
+ for (uint32_t i = 0; i < 100000; i++)
+ {
+ FAPI_TRY(p9_adu_coherent_status_check(i_target, EXIT_ON_BUSY, false,
+ l_busyBitStatus),
+ "Error from p9_adu_coherent_status_check");
+
+ //If the data done bit is set (the data transfer is done we can go write the data
+ if (!l_busyBitStatus)
+ {
+ break;
+ }
+ }
+ }
+ else
+ {
+ //delay to allow time for the write to progress
+ FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_OPER_HW_NS_DELAY,
+ PROC_ADU_UTILS_ADU_OPER_SIM_CYCLE_DELAY), "fapiDelay error");
+ }
fapi_try_exit:
FAPI_DBG("Exiting...");
@@ -691,28 +707,47 @@ extern "C"
FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG");
}
- //delay to allow time for the read to go through before we get the data
- FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
- PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
- "fapiDelay error");
+ //If this is a ci operation we want to poll the status register for completion
+ if (i_aduOper.getOperationType() == p9_ADU_oper_flag::CACHE_INHIBIT)
+ {
+ bool l_busyBitStatus = true;
+ for (uint32_t i = 0; i < 100000; i++)
+ {
+ FAPI_TRY(p9_adu_coherent_status_check(i_target, EXIT_ON_BUSY, false,
+ l_busyBitStatus),
+ "Error from p9_adu_coherent_status_check");
+
+ //If the data done bit is set (the data transfer is done we can go read the data
+ if (!l_busyBitStatus)
+ {
+ break;
+ }
+ }
+ }
+ else
+ {
+ //delay to allow time for the read to progress
+ FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_OPER_HW_NS_DELAY,
+ PROC_ADU_UTILS_ADU_OPER_SIM_CYCLE_DELAY), "fapiDelay error");
+ }
//if we want to include the itag and ecc data collect them before the read
if ( l_itagMode || l_eccMode )
{
FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data),
"Error reading from the FORCE_ECC Register");
- }
- if (l_itagMode)
- {
- eccIndex = 9;
- o_read_data[8] = force_ecc_reg_data.getBit<ALTD_DATA_ITAG_BIT>();
- }
+ if (l_itagMode)
+ {
+ eccIndex = 9;
+ o_read_data[8] = force_ecc_reg_data.getBit<ALTD_DATA_ITAG_BIT>();
+ }
- if (l_eccMode)
- {
- o_read_data[eccIndex] = (force_ecc_reg_data >> (63 - ALTD_DATA_TX_ECC_END_BIT)) & ALTD_DATA_ECC_MASK;
+ if (l_eccMode)
+ {
+ o_read_data[eccIndex] = (force_ecc_reg_data >> (63 - ALTD_DATA_TX_ECC_END_BIT)) & ALTD_DATA_ECC_MASK;
+ }
}
//read data from altd_data_reg
@@ -764,11 +799,7 @@ extern "C"
fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
- FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
- "Error reading from ALTD_CMD Register");
-
//write altd_cmd_reg to clear the fbc_locked bit
- altd_cmd_reg_data.clearBit<ALTD_CMD_LOCK_BIT>();
FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
"Error clearing the fbc_locked bit from the ALTD_CMD Register");
@@ -790,6 +821,10 @@ extern "C"
for (int i = 0; i < 10; i++)
{
+ FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_STATUS_HW_NS_DELAY,
+ PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY),
+ "fapiDelay error");
+
l_statusError = false;
// Check the ALTD_STATUS_REG
FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_statusReg),
@@ -843,8 +878,6 @@ extern "C"
l_statusReg.getBit<ALTD_STATUS_AUTOINC_ERR_BIT>() ||
l_statusReg.getBit<ALTD_STATUS_COMMAND_ERR_BIT>() ||
l_statusReg.getBit<ALTD_STATUS_ADDRESS_ERR_BIT>() ||
- l_statusReg.getBit<ALTD_STATUS_PB_OP_HANG_ERR_BIT>() ||
- l_statusReg.getBit<ALTD_STATUS_PB_DATA_HANG_ERR_BIT>() ||
l_statusReg.getBit<ALTD_STATUS_PBINIT_MISSING_BIT>() ||
l_statusReg.getBit<ALTD_STATUS_ECC_CE_BIT>() ||
l_statusReg.getBit<ALTD_STATUS_ECC_UE_BIT>() ||
@@ -861,10 +894,6 @@ extern "C"
{
break;
}
-
- FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
- PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY),
- "fapiDelay error");
}
// If error, display trace
@@ -930,6 +959,8 @@ extern "C"
{
FAPI_DBG("Configuring lock manipulation control data buffer to perform lock acquisition");
lock_control.setBit(ALTD_CMD_LOCK_BIT);
+ lock_control.setBit<ALTD_CMD_RESET_FSM_BIT>();
+ lock_control.setBit<ALTD_CMD_CLEAR_STATUS_BIT>();
}
else
{
@@ -985,8 +1016,8 @@ extern "C"
}
// delay to provide time for ADU lock to be released
- FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
- PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
+ FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_STATUS_HW_NS_DELAY,
+ PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY),
"fapiDelay error");
// increment attempt count, loop again
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
index 39f556a51..afd0ba677 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -127,7 +127,7 @@ extern"C"
return iv_operType;
}
- /// @brief Set the Auto Increment option, for CI/DMA operations only.
+ /// @brief Set the Auto Increment option, for DMA operations only.
///
/// @param[in] i_value True: Enable auto inc; False: Disable
///
@@ -135,30 +135,16 @@ extern"C"
///
inline void setAutoIncrement(bool i_value)
{
- if ( (iv_operType != CACHE_INHIBIT) &&
- (iv_operType != DMA_PARTIAL) )
- {
- FAPI_ERR("WARNING: Set AUTOINC for non CI/DMA operation, Operation type 0x%.8X",
- iv_operType);
- }
-
iv_autoInc = i_value;
return;
}
- /// @brief Get the Auto Increment setting, for CI/DMA operations only.
+ /// @brief Get the Auto Increment setting, for DMA operations only.
///
/// @return iv_autoInc.
///
inline const bool getAutoIncrement(void)
{
- if ( (iv_operType != CACHE_INHIBIT) &&
- (iv_operType != DMA_PARTIAL) )
- {
- FAPI_ERR("WARNING: AUTOINC value is invalid for non CI/DMA operation, Operation type 0x%.8X",
- iv_operType);
- }
-
return iv_autoInc;
}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
index e2d0855c7..be63d82bd 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -125,7 +125,7 @@ extern "C"
// Shift positions
const uint64_t FLAG_ADU_TTYPE_SHIFT = 29;
const uint64_t FLAG_LOCK_TRIES_SHIFT = 16;
- const uint64_t FLAG_ADU_SIZE_SHIFT = 20;
+ const uint64_t FLAG_ADU_SIZE_SHIFT = 20;
} //extern "C"
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_build_smp_adu.C b/src/import/chips/p9/procedures/hwp/nest/p9_build_smp_adu.C
index 74fd2b774..bb0c4f57d 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_build_smp_adu.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_build_smp_adu.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -177,7 +177,7 @@ fapi2::ReturnCode p9_build_smp_adu_check_status(
l_ffdc_reg_data[i].resize(64 * l_targets_to_collect.size());
}
-// // extract FFDC data
+ // extract FFDC data
// for (std::vector<fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>*>::iterator t_iter = l_targets_to_collect.begin();
// t_iter != l_targets_to_collect.end();
// t_iter++)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
index 5fc8f098d..1a9d0bafc 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_htm_adu_ctrl.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016 */
+/* Contributors Listed Below - COPYRIGHT 2016,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -44,7 +44,8 @@
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
-const uint32_t P9_HTM_START_MAX_STATUS_POLLS = 100; // Status time-out
+// Status time-out
+const uint32_t P9_HTM_START_MAX_STATUS_POLLS = 100;
///
/// See doxygen in p9_htm_adu_ctrl.H
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