diff options
author | Stephen Glancy <sglancy@us.ibm.com> | 2019-05-14 16:14:02 -0400 |
---|---|---|
committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-05-16 13:49:20 -0500 |
commit | 4a2e3c2c2db553afe45e100a02c1d44b92cd1801 (patch) | |
tree | 0190efad97aabd5891f21c4840a2e1423b75cd81 /src | |
parent | 4cc19fda64c0b5892abc4be584ec0ce589a9040c (diff) | |
download | talos-hostboot-4a2e3c2c2db553afe45e100a02c1d44b92cd1801.tar.gz talos-hostboot-4a2e3c2c2db553afe45e100a02c1d44b92cd1801.zip |
Adds new attributes for 07MAY19 explorer specification
Change-Id: I7629340458d5cccd80777059dbc8b00aaa973e6c
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77362
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77370
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H | 40 | ||||
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml | 82 |
2 files changed, 108 insertions, 14 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 234bae431..48a565f3d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -47,6 +47,46 @@ namespace exp constexpr uint32_t OCMB_ADDR_SHIFT = 3; /// +/// @brief enum list for the indexes for the address delays +/// @note Taken from 07-MAY-19 firwmare document +/// +enum attr_delay_index +{ + ODT1 = 0, + ODT0 = 0, + CS_N0 = 0, + CS_N1 = 0, + ADDR13 = 1, + ADDR5 = 1, + BG0 = 1, + CKE1 = 1, + ADDR17 = 2, + ADDR7 = 2, + BA0 = 2, + ADDR16 = 2, + ADDR8 = 3, + BG1 = 3, + CID1 = 3, + CID0 = 3, + ADDR1 = 4, + ADDR9 = 4, + ADDR2 = 4, + CAPARITY = 4, + ADDR12 = 5, + ADDR3 = 5, + ADDR4 = 5, + ADDR0 = 5, + CKE0 = 6, + ADDR15 = 6, + ACT_N = 6, + ADDR10 = 6, + ADDR11 = 7, + ADDR6 = 7, + BA1 = 7, + ADDR14 = 7, +}; + +/// /// @brief enum list of explorer SPD derived attributes to set /// @note these attrs are strictly derived from SPD /// @warning wrapped in exp namesapce to be distinguished from diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index efb51e2f2..28f7c41ea 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -270,20 +270,6 @@ <mssAccessorName>exp_spd_taa_min</mssAccessorName> </attribute> - <attribute> - <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Enable Special mode for Emulation Support - </description> - <initToZero></initToZero> - <valueType>uint8</valueType> - <mssUnits>bool</mssUnits> - <enum>NORMAL = 0, EMULATION = 1</enum> - <writeable/> - <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> - </attribute> - <attribute> <id>ATTR_MSS_EXP_REORDER_QUEUE_SETTING</id> <targetType>TARGET_TYPE_OCMB_CHIP</targetType> @@ -300,6 +286,20 @@ </attribute> <attribute> + <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Enable Special mode for Emulation Support + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <mssUnits>bool</mssUnits> + <enum>NORMAL = 0, EMULATION = 1</enum> + <writeable/> + <mssAccessorName>exp_firmware_emulation_mode</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> @@ -346,4 +346,58 @@ <mssAccessorName>ocmb_ecid</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EXP_DFIMRL_CLK</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + timing parameter for the DFIMRL clock + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>exp_dfimrl_clk</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_ATXDLY_A</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[ADDRESS INDEX] + ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] + ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] + ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] + ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] + ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY + ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] + ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] + ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>8</array> + <mssAccessorName>exp_atxdly_a</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_ATXDLY_B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[ADDRESS INDEX] + ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] + ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] + ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] + ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] + ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY + ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] + ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] + ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>8</array> + <mssAccessorName>exp_atxdly_b</mssAccessorName> + </attribute> + </attributes> |