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| author | Dan Crowell <dcrowell@us.ibm.com> | 2019-12-17 15:40:48 -0600 |
|---|---|---|
| committer | Nicholas E Bofferding <bofferdn@us.ibm.com> | 2019-12-18 11:41:02 -0600 |
| commit | 4638dc513da1390ce3652f34c51f39ac454e8953 (patch) | |
| tree | 8273d2fd0dbc7f3a09befd82187efcc59cef9986 /src | |
| parent | 75c0908b91275dc10bd17cb0f10b452f32ce0b91 (diff) | |
| download | talos-hostboot-4638dc513da1390ce3652f34c51f39ac454e8953.tar.gz talos-hostboot-4638dc513da1390ce3652f34c51f39ac454e8953.zip | |
Add current istep into TI SRC
Word4 of the SRC is defined to be the 'last progress code' for
FSP SRCs. For Hostboot TIs, we currently leave that word zero.
This change will add the same data that we put into the scratch
register 5 into word4 so that we will have the failing istep for
any TI we encounter.
Change-Id: Iaf5ec835d45b1ea3a6ced20b5b7f7d07216c548e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88813
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Nicholas E Bofferding <bofferdn@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/kernel/terminate.H | 13 | ||||
| -rw-r--r-- | src/kernel/terminate.C | 11 | ||||
| -rw-r--r-- | src/usr/initservice/istepdispatcher/istepdispatcher.C | 4 |
3 files changed, 26 insertions, 2 deletions
diff --git a/src/include/kernel/terminate.H b/src/include/kernel/terminate.H index b80331495..ce634e5c8 100644 --- a/src/include/kernel/terminate.H +++ b/src/include/kernel/terminate.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -87,4 +87,15 @@ void termModifySRC(uint8_t i_moduleID, */ void termSetHbDump(void); +/** @fn termSetIstep + * + * @brief Set istep into progress code word of the SRC. + * + * @param[in] i_istep: Encoded istep value + * @param[out] NONE: + * + * @return Nothing + */ +void termSetIstep(uint32_t i_istep); + #endif diff --git a/src/kernel/terminate.C b/src/kernel/terminate.C index cb70e9be6..fb3e1d069 100644 --- a/src/kernel/terminate.C +++ b/src/kernel/terminate.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -128,4 +128,13 @@ void termSetHbDump(void) return; } + +void termSetIstep(uint32_t i_istep) +{ + // Set istep into progress code word of the SRC + kernel_TIDataArea.src.SRCword4 = i_istep; + return; +} + + #endif // BOOTLOADER diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index 973f7928b..61d359bef 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -93,6 +93,7 @@ #include <p9_perv_scom_addresses.H> // --------------------------- #include <initservice/extinitserviceif.H> +#include <kernel/terminate.H> namespace ISTEPS_TRACE @@ -2507,6 +2508,9 @@ errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock) Util::writeScratchReg( SPLESS::MBOX_SCRATCH_REG5, l_scratch5.data32 ); + //--- Push the scratch reg into kernel to be added into TI area + termSetIstep(l_scratch5.data32); + #ifdef CONFIG_ISTEP_LPC_PORT80_DEBUG // Starting port 80h value for hostboot isteps. Each step started will // increase the value by one. |
