Add 500us delay after RESET_n & turn on clks before RESET_n to meet JEDEC spec

Change-Id: I2f0830a6f281c8ab3ba2b53d52520e564a3e2652
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36456
Dev-Ready: KEVIN MCILVAIN <kmcilva@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36471
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 23 insertions, 9 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
index e99b252a9..1cfe8cd92 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H
@@ -41,7 +41,7 @@
 #include <p9_mc_scom_addresses.H>
 #include <p9_mc_scom_addresses_fld.H>
 #include <lib/mss_attribute_accessors.H>
-
+#include <lib/utils/conversions.H>
 #include <lib/shared/mss_const.H>
 #include <lib/utils/scom.H>
 #include <lib/dimm/rank.H>
@@ -575,6 +575,14 @@ fapi2::ReturnCode ddr_resetn( const fapi2::Target<T>& i_target, const bool i_sta
         FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) );
     }
 
+    // From the DDR4 JEDEC Spec (79-A): Power-up Initialization Sequence
+    // After RESET_n is de-asserted, wait for another 500us before CKE goes active.
+    // Set our delay (for HW and SIM)
+    {
+        constexpr uint64_t DELAY_500US = 5 * mss::DELAY_100US;
+        FAPI_TRY( fapi2::delay(static_cast<uint64_t>(DELAY_500US),
+                               mss::us_to_cycles(i_target, DELAY_500US)) );
+    }
     return fapi2::FAPI2_RC_SUCCESS;
 
 fapi_try_exit:
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C
index cac69b4d2..951013d97 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -48,11 +48,11 @@ using fapi2::FAPI2_RC_SUCCESS;
 
 extern "C"
 {
-///
-/// @brief Initialize dram
-/// @param[in] i_target, the McBIST of the ports of the dram you're initializing
-/// @return FAPI2_RC_SUCCESS iff ok
-///
+    ///
+    /// @brief Initialize dram
+    /// @param[in] i_target, the McBIST of the ports of the dram you're initializing
+    /// @return FAPI2_RC_SUCCESS iff ok
+    ///
     fapi2::ReturnCode p9_mss_draminit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target )
     {
         fapi2::buffer<uint64_t> l_data;
@@ -118,17 +118,23 @@ extern "C"
         for (const auto& p : l_mca)
         {
             FAPI_TRY( mss::draminit_entry_invariant(p) );
-            FAPI_TRY( mss::ddr_resetn(p, mss::HIGH) );
 
             // Begin driving mem clks, and wait 10ns (we'll do this outside the loop)
+            // From the RCD Spec, before the DRST_n (resetn) input is pulled HIGH the
+            // clock input signal must be stable.
             FAPI_TRY( mss::drive_mem_clks(p, PCLK_INITIAL_VALUE, NCLK_INITIAL_VALUE) );
+
+            // After RESET_n is de-asserted, wait for another 500us until CKE becomes active.
+            // During this time, the DRAM will start internal initialization; this will be done
+            // independently of external clocks.
+            FAPI_TRY( mss::ddr_resetn(p, mss::HIGH) );
         }
 
         // From the DDR4 JEDEC Spec (79-A): Power-up Initialization Sequence
-        // Lets find our max delay in ns
         {
             // Clocks (CK_t,CK_c) need to be started and stable for 10ns or 5tCK
             // (whichever is greater) before CKE goes active.
+            // Doing this once here than twice in drive_mem_clks
             constexpr uint64_t DELAY_5TCK = 5;
             const uint64_t l_delay_in_ns = std::max( static_cast<uint64_t>(mss::DELAY_10NS),
                                            mss::cycles_to_ns(i_target, DELAY_5TCK) );