Indirect Scom Error checking added

Also added a patch for the action files so that I
can allow the testcases to run.

Change-Id: I86e39b5b8efd31ba8ea3b037470f88be68ec5818
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/702
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

8 files changed, 688 insertions, 23 deletions

diff --git a/src/build/citest/etc/patches/p8_indScom_910431.act b/src/build/citest/etc/patches/p8_indScom_910431.act
new file mode 100644
index 000000000..534c52efe
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_indScom_910431.act
@@ -0,0 +1,196 @@
+#This file was generated by /gsa/rchgsa-h1/02/missyc/sandboxes/hostboot/src/simu/fsp/buildIndScom.pl for scomdef: p8_910431.scomdef
+
+#The following actions are used for Indirect SCOMs
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x020140BF]
+  WATCH=[REG(0x020140BF)]
+  CAUSE: TARGET=[REG(0x020140BF)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x020140BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x020140BF(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x020140BF(CONTENTSOF{INDSCOM_0x020140BF(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x020140BF(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x020140BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x020140BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020140BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x020140BF(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x020140BF(CONTENTSOF{INDSCOM_0x020140BF(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x020140BF)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x020140BF(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x020140BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301187F]
+  WATCH=[REG(0x0301187F)]
+  CAUSE: TARGET=[REG(0x0301187F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301187F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301187F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301187F(CONTENTSOF{INDSCOM_0x0301187F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301187F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301187F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301187F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301187F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301187F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301187F(CONTENTSOF{INDSCOM_0x0301187F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301187F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301187F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301187F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x08010C3F]
+  WATCH=[REG(0x08010C3F)]
+  CAUSE: TARGET=[REG(0x08010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x08010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x08010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x03010C3F]
+  WATCH=[REG(0x03010C3F)]
+  CAUSE: TARGET=[REG(0x03010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x03010C3F(CONTENTSOF{INDSCOM_0x03010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x03010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x03010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x03010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x03010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x03010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x03010C3F(CONTENTSOF{INDSCOM_0x03010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x03010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x03010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x03010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301103F]
+  WATCH=[REG(0x0301103F)]
+  CAUSE: TARGET=[REG(0x0301103F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301103F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301103F(CONTENTSOF{INDSCOM_0x0301103F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301103F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301103F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301103F(CONTENTSOF{INDSCOM_0x0301103F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301103F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301103F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301143F]
+  WATCH=[REG(0x0301143F)]
+  CAUSE: TARGET=[REG(0x0301143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301143F(CONTENTSOF{INDSCOM_0x0301143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301143F(CONTENTSOF{INDSCOM_0x0301143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0301183F]
+  WATCH=[REG(0x0301183F)]
+  CAUSE: TARGET=[REG(0x0301183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0301183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0301183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0301183F(CONTENTSOF{INDSCOM_0x0301183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0301183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0301183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0301183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0301183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0301183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0301183F(CONTENTSOF{INDSCOM_0x0301183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0301183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0301183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0301183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x020120BF]
+  WATCH=[REG(0x020120BF)]
+  CAUSE: TARGET=[REG(0x020120BF)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x020120BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x020120BF(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x020120BF(CONTENTSOF{INDSCOM_0x020120BF(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x020120BF(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x020120BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x020120BF(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x020120BF)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x020120BF(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x020120BF(CONTENTSOF{INDSCOM_0x020120BF(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x020120BF)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x020120BF(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x020120BF)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
diff --git a/src/build/citest/etc/patches/p8_indScom_910520.act b/src/build/citest/etc/patches/p8_indScom_910520.act
new file mode 100644
index 000000000..3c03fb738
--- /dev/null
+++ b/src/build/citest/etc/patches/p8_indScom_910520.act
@@ -0,0 +1,244 @@
+#This file was generated by /gsa/rchgsa-h1/02/missyc/sandboxes/hostboot/src/simu/fsp/buildIndScom.pl for scomdef: p8_910520.scomdef
+
+#The following actions are used for Indirect SCOMs
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x08010C3F]
+  WATCH=[REG(0x08010C3F)]
+  CAUSE: TARGET=[REG(0x08010C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x08010C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x08010C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x08010C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x08010C3F(CONTENTSOF{INDSCOM_0x08010C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x08010C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x08010C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x02011E3F]
+  WATCH=[REG(0x02011E3F)]
+  CAUSE: TARGET=[REG(0x02011E3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x02011E3F(CONTENTSOF{INDSCOM_0x02011E3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x02011E3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x02011E3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x02011E3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011E3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x02011E3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x02011E3F(CONTENTSOF{INDSCOM_0x02011E3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x02011E3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x02011E3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x02011E3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0901183F]
+  WATCH=[REG(0x0901183F)]
+  CAUSE: TARGET=[REG(0x0901183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0901183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0901183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0901183F(CONTENTSOF{INDSCOM_0x0901183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0901183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0901183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0901183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0901183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0901183F(CONTENTSOF{INDSCOM_0x0901183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0901183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0901183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0901183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401143F]
+  WATCH=[REG(0x0401143F)]
+  CAUSE: TARGET=[REG(0x0401143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401143F(CONTENTSOF{INDSCOM_0x0401143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401143F(CONTENTSOF{INDSCOM_0x0401143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0901143F]
+  WATCH=[REG(0x0901143F)]
+  CAUSE: TARGET=[REG(0x0901143F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0901143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0901143F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0901143F(CONTENTSOF{INDSCOM_0x0901143F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0901143F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0901143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0901143F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0901143F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0901143F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0901143F(CONTENTSOF{INDSCOM_0x0901143F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0901143F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0901143F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0901143F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x04011C3F]
+  WATCH=[REG(0x04011C3F)]
+  CAUSE: TARGET=[REG(0x04011C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x04011C3F(CONTENTSOF{INDSCOM_0x04011C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x04011C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x04011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x04011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x04011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x04011C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x04011C3F(CONTENTSOF{INDSCOM_0x04011C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x04011C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x04011C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x04011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x02011A3F]
+  WATCH=[REG(0x02011A3F)]
+  CAUSE: TARGET=[REG(0x02011A3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x02011A3F(CONTENTSOF{INDSCOM_0x02011A3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x02011A3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x02011A3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x02011A3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x02011A3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x02011A3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x02011A3F(CONTENTSOF{INDSCOM_0x02011A3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x02011A3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x02011A3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x02011A3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401183F]
+  WATCH=[REG(0x0401183F)]
+  CAUSE: TARGET=[REG(0x0401183F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401183F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401183F(CONTENTSOF{INDSCOM_0x0401183F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401183F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401183F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401183F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401183F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401183F(CONTENTSOF{INDSCOM_0x0401183F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401183F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401183F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401183F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x0401103F]
+  WATCH=[REG(0x0401103F)]
+  CAUSE: TARGET=[REG(0x0401103F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x0401103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x0401103F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x0401103F(CONTENTSOF{INDSCOM_0x0401103F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x0401103F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x0401103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x0401103F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x0401103F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x0401103F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x0401103F(CONTENTSOF{INDSCOM_0x0401103F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x0401103F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x0401103F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x0401103F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Indirect Scom Action for 0x09011C3F]
+  WATCH=[REG(0x09011C3F)]
+  CAUSE: TARGET=[REG(0x09011C3F)] OP=[BIT,OFF] BIT=[0] #Write
+  #bits 12-31 contain the indirect address.
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #bits 48-63 contain the indirect SCOM data
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(0xFF0000DD)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #write 48-63 6010420 to the IND REG
+  EFFECT: TARGET=[INDSCOM_0x09011C3F(CONTENTSOF{INDSCOM_0x09011C3F(0xFF0000AA)})] OP=[EQUALTO,BUFSTRING] DATA=[INDSCOM_0x09011C3F(0xFF0000DD]
+  #Turn on bits 32 and 38 to show successful write
+   EFFECT: TARGET=[REG(0x09011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 82000000]
+  
+  ## Read => if Bit 0 = 1 in SCOM reg, it's a read request
+  #bits 12-31 contain the indirect address
+  ELSE: TARGET=[INDSCOM_0x09011C3F(0xFF0000AA)] OP=[EQUALTO,BUF,MASK] DATA=[REG(0x09011C3F)] MASK=[LITERAL(64,000FFFFF 00000000)]
+  #Move bits 48-63 from IND SCOM reg to 0xFF0000DD scratch reg (for debug)
+  ELSE: TARGET=[INDSCOM_0x09011C3F(0xFF0000DD)]  OP=[EQUALTO,BUFSTRING,MASK]  DATA=[INDSCOM_0x09011C3F(CONTENTSOF{INDSCOM_0x09011C3F(0xFF0000AA)})] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Move bits 48-63 from 0xFF0000DD scratch reg to SCOM Reg
+  ELSE: TARGET=[REG(0x09011C3F)] OP=[EQUALTO,BUF,MASK] DATA=[INDSCOM_0x09011C3F(0xFF0000DD)] MASK=[LITERAL(64,00000000 0000FFFF)]
+  #Turn on bits 32, 38, 39 to show successful read
+  ELSE: TARGET=[REG(0x09011C3F)] OP=[OR,ON,BUF] DATA=[LITERAL(64,00000000 83000000]
+}
+
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index fdaef92ca..216b517ea 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -4,8 +4,16 @@ Enable ECCB-based LPC/PNOR access (temporary)
 -Files: p8_pnor.act
 -Coreq: associated changes are also in workarounds.presimsetup
 
+
 Update centaur.act for running DRAM hardware procedures
 -RTC: Story 38362 will be used to remove the patch
 -CQ: SW127616
 -Files: centaur.act
 -Coreq: the file is copied in place by the workarounds.presimsetup
+
+
+Update the Action Files to add behavior for Indirect SCOM error bits
+-RTC: task 38013  will be used to remove the patch
+-CMVC:  Defect 825800 was used to check in the changes in buildIndScom.pl
+-Files: p8_indScom_910431.act , p8_indScom_910520.act in the src/build/citest/etc/patches directory
+-Coreq: associated changes are also in workarounds.presimsetup that need to be removed.
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 7836ed2b0..0bba2c8b4 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -72,7 +72,7 @@ echo "  0xDDDD0001,64  # dummy to hold pnor data" >> $sb/simu/data/cec-chip/p8.c
 echo "END" >> $sb/simu/data/cec-chip/p8.chip
 echo "DONE" >> $sb/simu/data/cec-chip/p8.chip
 cp $HOSTBOOTROOT/src/build/citest/etc/patches/p8_pnor.act $sb/simu/data/cec-chip/
-#fixme
+#fixme Story 37972
 
 
 echo "+++ Copy new centaur.act for DRAM hardware procedures."
@@ -88,3 +88,8 @@ cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL.*/WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL env\/mamboa\/2011_11_10__4.2/' $sb/simu/data/simicsInfo
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYPLEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYPLEVEL env\/phypa\/simics-4.2.0\/simics-4.2.83\/ph120201a700.42/' $sb/simu/data/simicsInfo
 #sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL env\/phypa\/simics-4.2.0\/simics-4.2.82\/patches\/ph120201a700.42/' $sb/simu/data/simicsInfo
+
+# added this patch until defect 825800 is integrated and included in a hostboot bbuild.
+echo "+++ Add workaround for p8 Indirect SCOM action files."
+cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910431.act $sb/simu/data/cec-chip/p8_indScom_910431.act
+cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910520.act $sb/simu/data/cec-chip/p8_indScom_910520.act
diff --git a/src/include/usr/scom/scomreasoncodes.H b/src/include/usr/scom/scomreasoncodes.H
index 85ba58a59..33ee7d5e5 100644
--- a/src/include/usr/scom/scomreasoncodes.H
+++ b/src/include/usr/scom/scomreasoncodes.H
@@ -29,11 +29,11 @@ namespace SCOM
 {
     enum scomModuleId
     {
-        MOD_INVALID                = 0x00, /**< Invalid Id */
-        SCOM_TRANSLATE             = 0x01, /**< scomtrans.C : scomTranslate */
-        SCOM_PERFORM_TRANSLATE     = 0x02, /**< scomtrans.C : scomPerformTranslate */
-        SCOM_FIND_PARENT_TARGET    = 0x03, /**< scomtrans.C : scomfindParentTarget */
-
+        SCOM_PERFORM_OP                 = 0x00,
+        SCOM_TRANSLATE                  = 0x01,
+        SCOM_PERFORM_TRANSLATE          = 0x02,
+        SCOM_FIND_PARENT_TARGET         = 0x03,
+        SCOM_CHECK_INDIRECT_AND_DO_SCOM = 0x04,
     };
 
     enum scomReasonCode
@@ -41,8 +41,13 @@ namespace SCOM
         SCOM_INVALID_ADDR           = SCOM_COMP_ID | 0x01,
         SCOM_NO_MATCHING_PARENT     = SCOM_COMP_ID | 0x02,
         SCOM_TRANS_INVALID_TYPE     = SCOM_COMP_ID | 0x03,
-        SCOM_TRANS_UNSUPPORTED_XBUS = SCOM_COMP_ID | 0x04,
-        SCOM_TRANS_UNSUPPORTED_ABUS = SCOM_COMP_ID | 0x05,
+        SCOM_TRANS_UNSUPPORTED      = SCOM_COMP_ID | 0x04,
+        SCOM_INDIRECT_READ_FAIL     = SCOM_COMP_ID | 0x05,
+        SCOM_INDIRECT_READ_TIMEOUT  = SCOM_COMP_ID | 0x06,
+        SCOM_INDIRECT_WRITE_FAIL    = SCOM_COMP_ID | 0x07,
+        SCOM_INDIRECT_WRITE_TIMEOUT = SCOM_COMP_ID | 0x08,
+        SCOM_TRANS_UNSUPPORTED_XBUS = SCOM_COMP_ID | 0x09,
+        SCOM_TRANS_UNSUPPORTED_ABUS = SCOM_COMP_ID | 0x0A,
     };
 };
 
diff --git a/src/usr/scom/scom.C b/src/usr/scom/scom.C
index 07a5754db..0074c9a4e 100644
--- a/src/usr/scom/scom.C
+++ b/src/usr/scom/scom.C
@@ -36,6 +36,8 @@
 #include <errl/errlmanager.H>
 #include "scom.H"
 #include <scom/scomreasoncodes.H>
+#include <sys/time.h>
+
 
 // Trace definition
 trace_desc_t* g_trac_scom = NULL;
@@ -96,6 +98,12 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType,
 
     errlHndl_t l_err = NULL;
     mutex_t* l_mutex = NULL;
+    uint64_t elapsed_indScom_time_ns = 0;
+    bool l_indScomError = false;
+    uint64_t temp_io_buffer = 0;
+
+    //@todo - determine hwhat an appropriate timeout value 
+    enum { MAX_INDSCOM_TIMEOUT_NS = 100000 }; //=.1ms
 
     // If the indirect scom bit is 0, then doing a regular scom 
     if( (i_addr & 0x8000000000000000) == 0)
@@ -110,8 +118,8 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType,
     // We are performing an indirect scom.
     else
     {
-        uint64_t l_io_buffer;
-        uint64_t temp_scomAddr;
+        uint64_t l_io_buffer = 0;
+        uint64_t temp_scomAddr = 0;
 
         memcpy(&l_io_buffer, io_buffer, 8);
         memcpy(&temp_scomAddr, &i_addr, 8);
@@ -155,21 +163,112 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType,
                 return l_err;
 	    }
 
-            // Now perform the op requested using the passed in
-            // IO_Buffer to pass the read data back to caller. 
-            l_err = doScomOp(i_opType,
-                             i_target,
-                             io_buffer,
-                             io_buflen,
-                             i_accessType,
-                             i_addr);
+            // Need to check loop on read until either
+            // bit (32) = 1 or we have exceeded our max
+            // retries. 
+            do
+            {
+                // Now perform the op requested using the passed in
+                // IO_Buffer to pass the read data back to caller. 
+                l_err = doScomOp(i_opType,
+                                 i_target,
+                                 io_buffer,
+                                 io_buflen,
+                                 i_accessType,
+                                 i_addr);
+
+                if (l_err != NULL)
+                {
+                    break;
+                }
+
+                // if bit 32 is on indicating a complete bit
+                if ((*((uint64_t *)io_buffer) & SCOM_IND_COMPLETE_MASK) == SCOM_IND_COMPLETE_MASK)
+                {
+                    // check for bits 37-39 to be 011 indicating the read is valid
+                    if ((*((uint64_t *)io_buffer) & SCOM_IND_ERROR_MASK) == SCOM_IND_READ_SUCCESS_MASK)
+                    {
+                        // Clear out the other bits in the io_buffer
+                        // register to only return the read data to caller
+                        *((uint64_t *)io_buffer) &= 0x00000000000FFFF;
+
+                    }
+                    else
+                    {
+                      // indicate that we do have a indirect scom failure
+                      l_indScomError = true;
+                    }
+
+                    // break out because we got the complete bit.. 
+                    break;
+                }
+
+                nanosleep( 0, 10000 ); //sleep for 10,000 ns
+                elapsed_indScom_time_ns += 10000;
+
+            }while ( elapsed_indScom_time_ns <= MAX_INDSCOM_TIMEOUT_NS);
 
             mutex_unlock(l_mutex);
 
+            if (l_err == NULL)
+            {
+                if (l_indScomError == true)
+                {
+                    // got an indirect read error
+                    // the data buffer is in tempIoData
+                    TRACFCOMP(g_trac_scom,
+                              "INDIRECT SCOM READ= ERROR valid bits are not on..  type=0x%X",
+                              *((uint64_t *)io_buffer));
+
+                    /*@
+                     * @errortype
+                     * @moduleid     SCOM::CHECK_INDIRECT_AND_DO_SCOM
+                     * @reasoncode   SCOM::INDIRECT_SCOM_READ_FAIL
+                     * @userdata1    Address
+                     * @userdata2    io_buffer data 
+                     * @devdesc      Indirect SCOM Read error
+                     */
+                    l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                                                    SCOM_CHECK_INDIRECT_AND_DO_SCOM,
+                                                    SCOM_INDIRECT_READ_FAIL,
+                                                    i_addr,
+                                                    *((uint64_t *)io_buffer));
+
+                    //@TODO - add usr details to the errorlog when we have one to
+                    //        give better info regarding the fail..
+
+                }
+                // if we got a timeout, create an errorlog.
+                else  if(  elapsed_indScom_time_ns > MAX_INDSCOM_TIMEOUT_NS )
+                {
+                    // got an indirect read timeout
+                    TRACFCOMP(g_trac_scom,
+                              "INDIRECT SCOM READ=indirect read timout ..  type=0x%X",
+                              *((uint64_t *)io_buffer));
+
+
+                    /*@
+                     * @errortype
+                     * @moduleid     SCOM::CHECK_INDIRECT_AND_DO_SCOM
+                     * @reasoncode   SCOM::INDIRECT_SCOM_READ_TIMEOUT
+                     * @userdata1    Address
+                     * @userdata2    io_buffer data 
+                     * @devdesc      Indirect SCOM complete bit did not come on
+                     */
+                    l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                                                    SCOM_CHECK_INDIRECT_AND_DO_SCOM,
+                                                    SCOM_INDIRECT_READ_TIMEOUT,
+                                                    i_addr,
+                                                    *((uint64_t *)io_buffer));
+
+                    //@TODO - add usr details to the errorlog when we have one to
+                    //        give better info regarding the fail..
+
+                }
+            }
         }
         else //write
         {
-
             // Turn the read bit off. 
             l_io_buffer = l_io_buffer & 0x7FFFFFFFFFFFFFFF;
 
@@ -181,9 +280,107 @@ errlHndl_t checkIndirectAndDoScom(DeviceFW::OperationType i_opType,
                              io_buflen,
                              i_accessType,
                              i_addr);
-        }
-    }
 
+            // Need to check loop on read until either
+            // bit (32) = 1 or we have exceeded our max
+            // retries. 
+            do
+            {
+
+                memcpy(&temp_io_buffer, io_buffer, 8);
+
+                // Now perform the op requested using the passed in
+                // IO_Buffer to pass the read data back to caller. 
+                l_err = doScomOp(DeviceFW::READ,
+                                 i_target,
+                                 & temp_io_buffer,
+                                 io_buflen,
+                                 i_accessType,
+                                 i_addr);
+
+
+                if (l_err != NULL)
+                {
+                    break;
+                }
+
+                // if bit 32 is on indicating a complete bit
+                if ((temp_io_buffer & SCOM_IND_COMPLETE_MASK) == SCOM_IND_COMPLETE_MASK)
+                {
+                    // The write is valid when bits 37-39 are 010.. if not on return error
+                    //  check for bits 37-39 to not be 010 
+                    if ((temp_io_buffer & SCOM_IND_ERROR_MASK) != SCOM_IND_WRITE_SUCCESS_MASK)
+                    {
+                        // bits did not get turned on.. set error to true. 
+                        l_indScomError = true; 
+                    }
+
+                    // break out because we got the complete bit on 
+                    break;
+
+                }
+
+                nanosleep( 0, 10000 ); //sleep for 10,000 ns
+                elapsed_indScom_time_ns += 10000;
+
+            }while ( elapsed_indScom_time_ns <= MAX_INDSCOM_TIMEOUT_NS);
+
+            if (l_err == NULL)
+            {
+                // If the indirect scom has an error.
+                if (l_indScomError == true)
+                {
+                    // got an indirect write error
+                    TRACFCOMP(g_trac_scom, "INDIRECT SCOM WRITE= ERROR valid bits are not on..  type=0x%X", temp_io_buffer);
+
+                    /*@
+                     * @errortype
+                     * @moduleid     SCOM::CHECK_INDIRECT_AND_DO_SCOM
+                     * @reasoncode   SCOM::INDIRECT_SCOM_WRITE_FAIL
+                     * @userdata1    Address
+                     * @userdata2    io_buffer data
+                     * @devdesc      Indirect SCOM Write failed for this address
+                     */
+                    l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                                                    SCOM_CHECK_INDIRECT_AND_DO_SCOM,
+                                                    SCOM_INDIRECT_WRITE_FAIL,
+                                                    i_addr,
+                                                    temp_io_buffer);
+
+                    //@TODO - add usr details to the errorlog when we have one to
+                    //        give better info regarding the fail.. 
+
+                }
+                // if we got a timeout, create an errorlog.
+                else  if(  elapsed_indScom_time_ns > MAX_INDSCOM_TIMEOUT_NS )
+                {
+                    // got an indirect write timeout
+                    TRACFCOMP(g_trac_scom,
+                              "INDIRECT SCOM READ=indirect write timout ..  type=0x%X",
+                              temp_io_buffer);
+
+
+                    /*@
+                     * @errortype
+                     * @moduleid     SCOM::CHECK_INDIRECT_AND_DO_SCOM
+                     * @reasoncode   SCOM::INDIRECT_SCOM_WRITE_TIMEOUT
+                     * @userdata1    Address
+                     * @userdata2    io_buffer data 
+                     * @devdesc      Indirect SCOM write timeout, complete bit did not come one
+                     */
+                    l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                                                    SCOM_CHECK_INDIRECT_AND_DO_SCOM,
+                                                    SCOM_INDIRECT_WRITE_TIMEOUT,
+                                                    i_addr,
+                                                    temp_io_buffer);
+
+                    //@TODO - add usr details to the errorlog when we have one to
+                    //        give better info regarding the fail..
+
+                }
+            }
+        } // end of write
+    }
     return l_err;
 }
 
diff --git a/src/usr/scom/scom.H b/src/usr/scom/scom.H
index d4b76a165..778faab13 100644
--- a/src/usr/scom/scom.H
+++ b/src/usr/scom/scom.H
@@ -31,8 +31,20 @@
 
 namespace SCOM
 {
+    enum ScomErrorMask
+    {
+        SCOM_IND_COMPLETE_MASK = 0x0000000080000000,
+            // this mask if for bit 37-39 for a read/write
+        SCOM_IND_ERROR_MASK =  0x000000007000000,
+    };
 
 
+    enum ScomValidMask
+    {
+        SCOM_IND_WRITE_SUCCESS_MASK =  0x000000002000000,
+        SCOM_IND_READ_SUCCESS_MASK = 0x000000003000000,
+    };
+
 /**
  * @brief Performs a SCom operation
  * This function performs a SCOM operation by calling
diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H
index d5a3f6b9e..c455f5be6 100644
--- a/src/usr/scom/test/scomtest.H
+++ b/src/usr/scom/test/scomtest.H
@@ -942,8 +942,6 @@ public:
           //only run if the target exists
           if(test_data[x].target == NULL)
           {
-              TRACFCOMP( g_trac_scom, "MBA_MBS ScomTest before device write- TARGET = NULL x = %d", x);
-
               continue;
           }