add support for OBUS PLL buckets

p9_frequency_buckets.H
p9.obus.pll.scan.initfile
  document and support base frequencies
    1611 MHz - 25.78G, 156.25 MHz ref
    1250 MHz - 25G, 156.25 MHz ref
    1200 MHz - 19.2G, 133.33 MHz ref

pervasive_attributes.xml
  define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value

nest_attributes.xml
  define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency
  retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit bucket selection through FSP/BMC->SBE mailbox
  encode OBUS bucket selects in Scratch Reg2 bits 24:31

p9_sbe_chiplet_pll_initf.C
p9_sbe_chiplet_pll_initf_errors.xml
  scan correct ring image based on bucket selector attributes

p9_ringId.C
p9_ringId.H
p9_ring_id.h
  accomodate three copies of obX_pll_bndy (use ID previously reserved for
  obX_pll_func, which should not be necessary to scan init)

scan_procedures.mk
generateWrapper.pl
  initCompiler infrastructure changes to support build of bucket data

p9.fbc.ab_hp.scom.initfile
p9.fbc.ioo_tl.scom.initfile
p9_tod_setup.C
  updates to handle A,O frequency attribute changes

Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40165
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

13 files changed, 346 insertions, 127 deletions

diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H
index 7083cf766..892cc5f22 100644
--- a/src/import/chips/p9/common/include/p9_frequency_buckets.H
+++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -64,3 +64,16 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] =
     2666,
     2666
 };
+
+// constant definining number of OBUS PLL frequency options ('buckets')
+// to be built into unsigned HW image
+const uint8_t OBUS_PLL_FREQ_BUCKETS = 3;
+
+// OBUS PLL frequency in MHz
+// index is bucket number
+const uint32_t OBUS_PLL_FREQ_LIST[OBUS_PLL_FREQ_BUCKETS] =
+{
+    1611,
+    1250,
+    1200
+};
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_tl_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_tl_scom.C
index f93da83b0..1e11570ca 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_tl_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_tl_scom.C
@@ -81,18 +81,25 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                                             || (l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_1] != literal_0));
         uint64_t l_def_OBUS0_FBC_ENABLED = ((l_TGT0_ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG[literal_3] != literal_0)
                                             || (l_TGT0_ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG[literal_0] != literal_0));
-        fapi2::ATTR_FREQ_A_MHZ_Type l_TGT1_ATTR_FREQ_A_MHZ;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, TGT1, l_TGT1_ATTR_FREQ_A_MHZ));
+        fapi2::ATTR_FREQ_O_MHZ_Type l_TGT0_ATTR_FREQ_O_MHZ;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_O_MHZ, TGT0, l_TGT0_ATTR_FREQ_O_MHZ));
         fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT1_ATTR_FREQ_PB_MHZ;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, TGT1, l_TGT1_ATTR_FREQ_PB_MHZ));
-        uint64_t l_def_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT1_ATTR_FREQ_A_MHZ * literal_12));
-        uint64_t l_def_OBUS0_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS0_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_0] *
+                                           literal_12));
+        uint64_t l_def_OBUS0_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_0] * literal_10);
         uint64_t l_def_OBUS0_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_154);
-        uint64_t l_def_OBUS1_LO_LIMIT_D = l_TGT1_ATTR_FREQ_A_MHZ;
+        uint64_t l_def_OBUS1_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_1] *
+                                           literal_12));
+        uint64_t l_def_OBUS1_LO_LIMIT_D = l_TGT0_ATTR_FREQ_O_MHZ[literal_1];
         uint64_t l_def_OBUS1_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_12);
-        uint64_t l_def_OBUS2_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS2_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_2] *
+                                           literal_12));
+        uint64_t l_def_OBUS2_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_2] * literal_10);
         uint64_t l_def_OBUS2_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_74);
-        uint64_t l_def_OBUS3_LO_LIMIT_D = (l_TGT1_ATTR_FREQ_A_MHZ * literal_10);
+        uint64_t l_def_OBUS3_LO_LIMIT_R = ((l_TGT1_ATTR_FREQ_PB_MHZ * literal_10) > (l_TGT0_ATTR_FREQ_O_MHZ[literal_3] *
+                                           literal_12));
+        uint64_t l_def_OBUS3_LO_LIMIT_D = (l_TGT0_ATTR_FREQ_O_MHZ[literal_3] * literal_10);
         uint64_t l_def_OBUS3_LO_LIMIT_N = (l_TGT1_ATTR_FREQ_PB_MHZ * literal_95);
         fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE_Type l_TGT1_ATTR_PROC_FABRIC_SMP_OPTICS_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SMP_OPTICS_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_SMP_OPTICS_MODE));
@@ -129,7 +136,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS0_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS0_FBC_ENABLED && (l_def_OBUS0_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x36 - (l_def_OBUS0_LO_LIMIT_N / l_def_OBUS0_LO_LIMIT_D)) );
             }
@@ -143,7 +150,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS0_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS0_FBC_ENABLED && (l_def_OBUS0_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x36 - (l_def_OBUS0_LO_LIMIT_N / l_def_OBUS0_LO_LIMIT_D)) );
             }
@@ -167,7 +174,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS1_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS1_FBC_ENABLED && (l_def_OBUS1_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x2A - (l_def_OBUS1_LO_LIMIT_N / l_def_OBUS1_LO_LIMIT_D)) );
             }
@@ -181,7 +188,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS1_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS1_FBC_ENABLED && (l_def_OBUS1_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x2A - (l_def_OBUS1_LO_LIMIT_N / l_def_OBUS1_LO_LIMIT_D)) );
             }
@@ -205,7 +212,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS2_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS2_FBC_ENABLED && (l_def_OBUS2_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x1B - (l_def_OBUS2_LO_LIMIT_N / l_def_OBUS2_LO_LIMIT_D)) );
             }
@@ -219,7 +226,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS2_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS2_FBC_ENABLED && (l_def_OBUS2_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x1B - (l_def_OBUS2_LO_LIMIT_N / l_def_OBUS2_LO_LIMIT_D)) );
             }
@@ -243,7 +250,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<12, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS3_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS3_FBC_ENABLED && (l_def_OBUS3_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<4, 8, 56, uint64_t>((literal_0x22 - (l_def_OBUS3_LO_LIMIT_N / l_def_OBUS3_LO_LIMIT_D)) );
             }
@@ -257,7 +264,7 @@ fapi2::ReturnCode p9_fbc_ioo_tl_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(literal_0x40 );
             }
 
-            if ((l_def_OBUS3_FBC_ENABLED && (l_def_LO_LIMIT_R == literal_1)))
+            if ((l_def_OBUS3_FBC_ENABLED && (l_def_OBUS3_LO_LIMIT_R == literal_1)))
             {
                 l_scom_buffer.insert<36, 8, 56, uint64_t>((literal_0x22 - (l_def_OBUS3_LO_LIMIT_N / l_def_OBUS3_LO_LIMIT_D)) );
             }
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index a65c02a44..2378ccbd7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -27389,8 +27389,8 @@ fapi_try_exit:
 /// @param[out] uint32_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  The frequency of a processor's A link clocks, in MHz. This is the same for all
-/// chips in the system. Provided by the
+/// @note  The frequency of a processor's Abus, in MHz. This is the same for all chips in
+/// the system. Provided by the
 /// MRW.
 ///
 inline fapi2::ReturnCode freq_a_mhz(uint32_t& o_value)
@@ -27410,8 +27410,8 @@ fapi_try_exit:
 /// @param[out] uint32_t& reference to store the value
 /// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  The frequency of a processor's X link clocks, in MHz. This is the same for all
-/// chips in the system. Provided by the
+/// @note  The frequency of a processor's Xbus mesh clocks, in MHz. This is the same for
+/// all chips in the system. Provided by the
 /// MRW.
 ///
 inline fapi2::ReturnCode freq_x_mhz(uint32_t& o_value)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C
index 4f505e377..8b809dcb4 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C
@@ -1050,14 +1050,14 @@ fapi_try_exit:
 /// @brief Calculates the delay for a node in TOD-grid-cycles
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x XBUS frequency in MHz
-/// @param[in] i_freq_o OBUS frequency in MHz
+/// @param[in] i_freq_a OBUS frequency in MHz
 /// @param[out] o_node_delay => Delay of a single node in TOD-grid-cycles
 /// @return FAPI_RC_SUCCESS if TOD node delay is successfully calculated else
 ///         error
 fapi2::ReturnCode calculate_node_link_delay(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     uint32_t& o_node_delay)
 {
     fapi2::buffer<uint64_t> l_rt_delay_ctl_reg = 0;
@@ -1151,7 +1151,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS0),
                         "i_tod_node->i_bus_rx is set to OBUS0 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_0>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_1>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1168,7 +1168,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS1),
                         "i_tod_node->i_bus_rx is set to OBUS1 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_2>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_3>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1185,7 +1185,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS2),
                         "i_tod_node->i_bus_rx is set to OBUS2 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_4>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_5>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1202,7 +1202,7 @@ fapi2::ReturnCode calculate_node_link_delay(
                         .set_TARGET(*(i_tod_node->i_target))
                         .set_RX(OBUS3),
                         "i_tod_node->i_bus_rx is set to OBUS3 and it is not enabled");
-            l_bus_freq = i_freq_o;
+            l_bus_freq = i_freq_a;
             l_rt_delay_ctl_reg.setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_6>()
             .setBit<PB_OLINK_RT_DELAY_CTL_SET_LINK_7>();
             l_rt_delay_ctl_addr = PU_IOE_PB_OLINK_RT_DELAY_CTL_REG;
@@ -1275,14 +1275,14 @@ fapi_try_exit:
 ///        node delay)
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x XBUS frequency in MHz
-/// @param[in] i_freq_o OBUS frequency in MHz
+/// @param[in] i_freq_a OBUS frequency in MHz
 /// @param[out] o_longest_delay Longest delay in TOD-grid-cycles
 /// @return FAPI_RC_SUCCESS if a longest TOD delay was found in topology
 ///         else error
 fapi2::ReturnCode calculate_longest_topolopy_delay(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     uint32_t& o_longest_delay)
 {
     uint32_t l_node_delay = 0;
@@ -1292,7 +1292,7 @@ fapi2::ReturnCode calculate_longest_topolopy_delay(
 
     FAPI_TRY(calculate_node_link_delay(i_tod_node,
                                        i_freq_x,
-                                       i_freq_o,
+                                       i_freq_a,
                                        l_node_delay),
              "Error from calculate_node_link_delay!");
     o_longest_delay = l_node_delay;
@@ -1304,7 +1304,7 @@ fapi2::ReturnCode calculate_longest_topolopy_delay(
         tod_topology_node* l_tod_node = *l_child;
         FAPI_TRY(calculate_longest_topolopy_delay(l_tod_node,
                  i_freq_x,
-                 i_freq_o,
+                 i_freq_a,
                  l_node_delay),
                  "Error from calculate_longest_topology_delay!");
 
@@ -1325,14 +1325,14 @@ fapi_try_exit:
 /// @brief Updates the topology struct with the final delay values
 /// @param[in] i_tod_node Reference to TOD topology
 /// @param[in] i_freq_x  XBUS frequency in MHz
-/// @param[in] i_freq_o  OBUS frequency in MHz
+/// @param[in] i_freq_a  OBUS frequency in MHz
 /// @param[in] i_longest_delay Longest delay in the topology
 /// @return FAPI_RC_SUCCESS if o_int_path_delay was set for every node in the
 ///         topology else error
 fapi2::ReturnCode set_topology_delays(
     tod_topology_node* i_tod_node,
     const uint32_t i_freq_x,
-    const uint32_t i_freq_o,
+    const uint32_t i_freq_a,
     const uint32_t i_longest_delay)
 {
     FAPI_DBG("Start");
@@ -1350,7 +1350,7 @@ fapi2::ReturnCode set_topology_delays(
                 .set_PATH_DELAY(i_tod_node->o_int_path_delay)
                 .set_LONGEST_DELAY(i_longest_delay)
                 .set_XBUS_FREQ(i_freq_x)
-                .set_OBUS_FREQ(i_freq_o),
+                .set_OBUS_FREQ(i_freq_a),
                 "Invalid delay of %d calculated!");
 
     // Recurse on downstream nodes
@@ -1360,7 +1360,7 @@ fapi2::ReturnCode set_topology_delays(
     {
         FAPI_TRY(set_topology_delays(*l_child,
                                      i_freq_x,
-                                     i_freq_o,
+                                     i_freq_a,
                                      i_tod_node->o_int_path_delay),
                  "Error from set_topology_delays!");
     }
@@ -1380,33 +1380,33 @@ fapi2::ReturnCode calculate_node_delays(tod_topology_node* i_tod_node)
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     uint32_t l_longest_delay = 0;
     uint32_t l_freq_x = 0;
-    uint32_t l_freq_o = 0;
+    uint32_t l_freq_a = 0;
 
     FAPI_DBG("Start");
     // retrieve X-bus and A-bus frequencies
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_X_MHZ, FAPI_SYSTEM, l_freq_x),
              "Failure reading XBUS frequency attribute!");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, FAPI_SYSTEM, l_freq_o),
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_A_MHZ, FAPI_SYSTEM, l_freq_a),
              "Failure reading OBUS frequency attribute!");
 
     // multiply attribute (mesh speed) speed by link factor
     l_freq_x *= 8;
-    l_freq_o *= 16;
+    l_freq_a *= 16;
 
     // Bus frequencies are global for the system (i.e. A0 and A1 will always
     //  run with the same frequency)
-    FAPI_DBG("XBUS=%dMHz OBUS=%dMHz", l_freq_x, l_freq_o);
+    FAPI_DBG("XBUS=%dMHz OBUS=%dMHz", l_freq_x, l_freq_a);
 
     // Find the most-delayed path in the topology; this is the MDMT's delay
     FAPI_TRY(calculate_longest_topolopy_delay(i_tod_node,
              l_freq_x,
-             l_freq_o,
+             l_freq_a,
              l_longest_delay),
              "Error from calculate_longest_topology_delay!");
     FAPI_DBG("The longest delay is %d TOD-grid-cycles.", l_longest_delay);
     FAPI_TRY(set_topology_delays(i_tod_node,
                                  l_freq_x,
-                                 l_freq_o,
+                                 l_freq_a,
                                  l_longest_delay),
              "Error from set_topology_delays!");
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 62259674c..40790e3a9 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -58,6 +58,14 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT  = 17,
     ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT  = 18,
     ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT  = 19,
+    ATTR_OB0_PLL_BUCKET_STARTBIT       = 24,
+    ATTR_OB0_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB1_PLL_BUCKET_STARTBIT       = 26,
+    ATTR_OB1_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB2_PLL_BUCKET_STARTBIT       = 28,
+    ATTR_OB2_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB3_PLL_BUCKET_STARTBIT       = 30,
+    ATTR_OB3_PLL_BUCKET_LENGTH         = 2,
 
     // Scratch_reg_3
     ATTR_BOOT_FLAGS_STARTBIT           = 0,
@@ -66,14 +74,14 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     // Scratch_reg_4
     ATTR_BOOT_FREQ_MULT_STARTBIT       = 0,
     ATTR_BOOT_FREQ_MULT_LENGTH         = 16,
-    ATTR_NEST_PLL_BUCKET_STARTBIT      = 24,
-    ATTR_NEST_PLL_BUCKET_LENGTH        = 8,
     ATTR_CP_FILTER_BYPASS_BIT          = 16,
     ATTR_SS_FILTER_BYPASS_BIT          = 17,
     ATTR_IO_FILTER_BYPASS_BIT          = 18,
     ATTR_DPLL_BYPASS_BIT               = 19,
     ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT   = 20,
     ATTR_OBUS_RATIO_VALUE_BIT          = 21,
+    ATTR_NEST_PLL_BUCKET_STARTBIT      = 29,
+    ATTR_NEST_PLL_BUCKET_LENGTH        = 3,
 
     // Scratch_reg_5
     ATTR_PLL_MUX_STARTBIT              = 12,
@@ -147,6 +155,10 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch2_reg
     {
+        uint8_t l_ob0_pll_bucket;
+        uint8_t l_ob1_pll_bucket;
+        uint8_t l_ob2_pll_bucket;
+        uint8_t l_ob3_pll_bucket;
 
         FAPI_DBG("Reading Scratch_reg2");
         //Getting SCRATCH_REGISTER_2 register value
@@ -195,6 +207,17 @@ fapi2::ReturnCode p9_setup_sbe_config(const
             }
         }
 
+        FAPI_DBG("Reading OB PLL buckets");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket));
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket));
+
+        l_read_scratch_reg.insertFromRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
+        l_read_scratch_reg.insertFromRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
+
         FAPI_DBG("Setting up value of Scratch_reg2");
         //Setting SCRATCH_REGISTER_2 register value
         //CFAM.SCRATCH_REGISTER_2 = l_read_scratch_reg
@@ -254,7 +277,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
 
         l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
-        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);
+        l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1 & 0x7);
 
         l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
         l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index cbd788960..7d6d40b06 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -46,22 +46,36 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
+  <id>ATTR_FREQ_O_MHZ</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    The frequency of a processor's Obus mesh clocks, in MHz.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+  <writeable/>
+  <array>4</array>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
   <id>ATTR_FREQ_A_MHZ</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>
-    The frequency of a processor's A link clocks, in MHz.
+    The frequency of a processor's Abus, in MHz.
     This is the same for all chips in the system.
     Provided by the MRW.
   </description>
   <valueType>uint32</valueType>
   <platInit/>
+  <writeable/>
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_FREQ_X_MHZ</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>
-    The frequency of a processor's X link clocks, in MHz.
+    The frequency of a processor's Xbus mesh clocks, in MHz.
     This is the same for all chips in the system.
     Provided by the MRW.
   </description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index c3277e5c0..15ce68140 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -141,6 +141,46 @@
 </attribute>
 
 <attribute>
+  <id>ATTR_OB0_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS0 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB1_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS1 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB2_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS2 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB3_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS3 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
   <id>ATTR_BOOT_FREQ_MULT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>EQ boot frequency multiplier
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
index 09d8141b7..aab8eebc3 100755
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -33,4 +33,15 @@
     <ffdc>UNIT_POS</ffdc>
   </hwpError>
   <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_CHIPLET_PLL_INITF_UNSUPPORTED_OBUS_BUCKET</rc>
+    <description>Unsupported OBUS PLL bucket select</description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>OB0_BUCKET_INDEX</ffdc>
+    <ffdc>OB1_BUCKET_INDEX</ffdc>
+    <ffdc>OB2_BUCKET_INDEX</ffdc>
+    <ffdc>OB3_BUCKET_INDEX</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
 </hwpErrors>
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
index ccf7281af..1f4537cef 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
@@ -222,16 +222,17 @@ namespace OB0
 {
 const GenRingIdList RING_ID_LIST_COMMON[] =
 {
-    {"ob0_fure"            , 0x00, 0x09, 0x09, EKB_RING    , 0x0903700F},
-    {"ob0_gptr"            , 0x01, 0x09, 0x09, EKB_RING    , 0x09037002},
-    {"ob0_time"            , 0x02, 0x09, 0x09, VPD_RING    , 0x09037007},
-    {"ob0_pll_gptr"        , 0x03, 0x09, 0x09, EKB_RING    , 0x09030012},
-    {"ob0_pll_bndy"        , 0x04, 0x09, 0x09, EKB_RING    , 0x09030018},
-    {"ob0_pll_func"        , 0x05, 0x09, 0x09, EKB_RING    , 0x09030010},
+    {"ob0_fure"              , 0x00, 0x09, 0x09, EKB_RING    , 0x0903700F},
+    {"ob0_gptr"              , 0x01, 0x09, 0x09, EKB_RING    , 0x09037002},
+    {"ob0_time"              , 0x02, 0x09, 0x09, VPD_RING    , 0x09037007},
+    {"ob0_pll_gptr"          , 0x03, 0x09, 0x09, EKB_RING    , 0x09030012},
+    {"ob0_pll_bndy_bucket_1" , 0x04, 0x09, 0x09, EKB_RING    , 0x09030018},
+    {"ob0_pll_bndy_bucket_2" , 0x05, 0x09, 0x09, EKB_RING    , 0x09030018},
+    {"ob0_pll_bndy_bucket_3" , 0x06, 0x09, 0x09, EKB_RING    , 0x09030018},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"ob0_repr"            , 0x0a, 0x09, 0x09, VPD_RING    , 0x09037006},
+    {"ob0_repr"              , 0x0a, 0x09, 0x09, VPD_RING    , 0x09037006},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
 };
@@ -241,16 +242,17 @@ namespace OB1
 {
 const GenRingIdList RING_ID_LIST_COMMON[] =
 {
-    {"ob1_fure"            , 0x00, 0x0a, 0x0a, EKB_RING    , 0x0A03700F},
-    {"ob1_gptr"            , 0x01, 0x0a, 0x0a, EKB_RING    , 0x0A037002},
-    {"ob1_time"            , 0x02, 0x0a, 0x0a, VPD_RING    , 0x0A037007},
-    {"ob1_pll_gptr"        , 0x03, 0x0a, 0x0a, EKB_RING    , 0x0A030012},
-    {"ob1_pll_bndy"        , 0x04, 0x0a, 0x0a, EKB_RING    , 0x0A030018},
-    {"ob1_pll_func"        , 0x05, 0x0a, 0x0a, EKB_RING    , 0x0A030010},
+    {"ob1_fure"              , 0x00, 0x0a, 0x0a, EKB_RING    , 0x0A03700F},
+    {"ob1_gptr"              , 0x01, 0x0a, 0x0a, EKB_RING    , 0x0A037002},
+    {"ob1_time"              , 0x02, 0x0a, 0x0a, VPD_RING    , 0x0A037007},
+    {"ob1_pll_gptr"          , 0x03, 0x0a, 0x0a, EKB_RING    , 0x0A030012},
+    {"ob1_pll_bndy_bucket_1" , 0x04, 0x0a, 0x0a, EKB_RING    , 0x0A030018},
+    {"ob1_pll_bndy_bucket_2" , 0x05, 0x0a, 0x0a, EKB_RING    , 0x0A030018},
+    {"ob1_pll_bndy_bucket_3" , 0x06, 0x0a, 0x0a, EKB_RING    , 0x0A030018},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"ob1_repr"            , 0x0a, 0x0a, 0x0a, VPD_RING    , 0x0A037006},
+    {"ob1_repr"              , 0x0a, 0x0a, 0x0a, VPD_RING    , 0x0A037006},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
 };
@@ -260,16 +262,17 @@ namespace OB2
 {
 const GenRingIdList RING_ID_LIST_COMMON[] =
 {
-    {"ob2_fure"            , 0x00, 0x0b, 0x0b, EKB_RING    , 0x0B03700F},
-    {"ob2_gptr"            , 0x01, 0x0b, 0x0b, EKB_RING    , 0x0B037002},
-    {"ob2_time"            , 0x02, 0x0b, 0x0b, VPD_RING    , 0x0B037007},
-    {"ob2_pll_gptr"        , 0x03, 0x0b, 0x0b, EKB_RING    , 0x0B030012},
-    {"ob2_pll_bndy"        , 0x04, 0x0b, 0x0b, EKB_RING    , 0x0B030018},
-    {"ob2_pll_func"        , 0x05, 0x0b, 0x0b, EKB_RING    , 0x0B030010},
+    {"ob2_fure"              , 0x00, 0x0b, 0x0b, EKB_RING    , 0x0B03700F},
+    {"ob2_gptr"              , 0x01, 0x0b, 0x0b, EKB_RING    , 0x0B037002},
+    {"ob2_time"              , 0x02, 0x0b, 0x0b, VPD_RING    , 0x0B037007},
+    {"ob2_pll_gptr"          , 0x03, 0x0b, 0x0b, EKB_RING    , 0x0B030012},
+    {"ob2_pll_bndy_bucket_1" , 0x04, 0x0b, 0x0b, EKB_RING    , 0x0B030018},
+    {"ob2_pll_bndy_bucket_2" , 0x05, 0x0b, 0x0b, EKB_RING    , 0x0B030018},
+    {"ob2_pll_bndy_bucket_3" , 0x06, 0x0b, 0x0b, EKB_RING    , 0x0B030018},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"ob2_repr"            , 0x0a, 0x0b, 0x0b, VPD_RING    , 0x0B037006},
+    {"ob2_repr"              , 0x0a, 0x0b, 0x0b, VPD_RING    , 0x0B037006},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
 };
@@ -279,16 +282,17 @@ namespace OB3
 {
 const GenRingIdList RING_ID_LIST_COMMON[] =
 {
-    {"ob3_fure"            , 0x00, 0x0c, 0x0c, EKB_RING    , 0x0C03700F},
-    {"ob3_gptr"            , 0x01, 0x0c, 0x0c, EKB_RING    , 0x0C037002},
-    {"ob3_time"            , 0x02, 0x0c, 0x0c, VPD_RING    , 0x0C037007},
-    {"ob3_pll_gptr"        , 0x03, 0x0c, 0x0c, EKB_RING    , 0x0C030012},
-    {"ob3_pll_bndy"        , 0x04, 0x0c, 0x0c, EKB_RING    , 0x0C030018},
-    {"ob3_pll_func"        , 0x05, 0x0c, 0x0c, EKB_RING    , 0x0C030010},
+    {"ob3_fure"              , 0x00, 0x0c, 0x0c, EKB_RING    , 0x0C03700F},
+    {"ob3_gptr"              , 0x01, 0x0c, 0x0c, EKB_RING    , 0x0C037002},
+    {"ob3_time"              , 0x02, 0x0c, 0x0c, VPD_RING    , 0x0C037007},
+    {"ob3_pll_gptr"          , 0x03, 0x0c, 0x0c, EKB_RING    , 0x0C030012},
+    {"ob3_pll_bndy_bucket_1" , 0x04, 0x0c, 0x0c, EKB_RING    , 0x0C030018},
+    {"ob3_pll_bndy_bucket_2" , 0x05, 0x0c, 0x0c, EKB_RING    , 0x0C030018},
+    {"ob3_pll_bndy_bucket_3" , 0x06, 0x0c, 0x0c, EKB_RING    , 0x0C030018},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"ob3_repr"            , 0x0a, 0x0c, 0x0c, VPD_RING    , 0x0C037006},
+    {"ob3_repr"              , 0x0a, 0x0c, 0x0c, VPD_RING    , 0x0C037006},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID };
 };
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
index 93927e483..d3a1ddeaa 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
@@ -533,7 +533,9 @@ enum RingOffset
     ob0_time      = 2,
     ob0_pll_gptr  = 3,
     ob0_pll_bndy  = 4,
-    ob0_pll_func  = 5,
+    ob0_pll_bndy_bucket_1  = 4,
+    ob0_pll_bndy_bucket_2  = 5,
+    ob0_pll_bndy_bucket_3  = 6,
     // Instance Rings
     ob0_repr      = (0 | INSTANCE_RING_MARK)
 };
@@ -541,7 +543,7 @@ enum RingOffset
 static const CHIPLET_DATA g_ob0Data =
 {
     9,  // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
-    6,  // 6 common rings for OB Chiplet
+    7,  // 7 common rings for OB Chiplet
     1,  // 1 instance specific rings for each OB chiplet
     1
 };
@@ -563,7 +565,9 @@ enum RingOffset
     ob1_time      = 2,
     ob1_pll_gptr  = 3,
     ob1_pll_bndy  = 4,
-    ob1_pll_func  = 5,
+    ob1_pll_bndy_bucket_1  = 4,
+    ob1_pll_bndy_bucket_2  = 5,
+    ob1_pll_bndy_bucket_3  = 6,
     // Instance Rings
     ob1_repr      = (0 | INSTANCE_RING_MARK)
 };
@@ -571,7 +575,7 @@ enum RingOffset
 static const CHIPLET_DATA g_ob1Data =
 {
     10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
-    6,  // 6 common rings for OB Chiplet
+    7,  // 7 common rings for OB Chiplet
     1,  // 1 instance specific rings for each OB chiplet
     1
 };
@@ -594,7 +598,9 @@ enum RingOffset
     ob2_time      = 2,
     ob2_pll_gptr  = 3,
     ob2_pll_bndy  = 4,
-    ob2_pll_func  = 5,
+    ob2_pll_bndy_bucket_1  = 4,
+    ob2_pll_bndy_bucket_2  = 5,
+    ob2_pll_bndy_bucket_3  = 6,
     // Instance Rings
     ob2_repr      = (0 | INSTANCE_RING_MARK)
 };
@@ -602,7 +608,7 @@ enum RingOffset
 static const CHIPLET_DATA g_ob2Data =
 {
     11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
-    6,  // 6 common rings for OB Chiplet
+    7,  // 7 common rings for OB Chiplet
     1,  // 1 instance specific rings for each OB chiplet
     1
 };
@@ -624,7 +630,9 @@ enum RingOffset
     ob3_time      = 2,
     ob3_pll_gptr  = 3,
     ob3_pll_bndy  = 4,
-    ob3_pll_func  = 5,
+    ob3_pll_bndy_bucket_1  = 4,
+    ob3_pll_bndy_bucket_2  = 5,
+    ob3_pll_bndy_bucket_3  = 6,
     // Instance Rings
     ob3_repr      = (0 | INSTANCE_RING_MARK)
 };
@@ -632,7 +640,7 @@ enum RingOffset
 static const CHIPLET_DATA g_ob3Data =
 {
     12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
-    6,  // 10 common rings for OB Chiplet
+    7,  // 7 common rings for OB Chiplet
     1,  // 1 instance specific rings for each OB chiplet
     1
 };
@@ -999,37 +1007,37 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { OB0::ob0_time                      , "ob0_time"                    , OB0_TYPE   }, // 120
     { OB0::ob0_pll_gptr                  , "ob0_pll_gptr"                , OB0_TYPE   }, // 121
     { OB0::ob0_pll_bndy                  , "ob0_pll_bndy"                , OB0_TYPE   }, // 122
-    { OB0::ob0_pll_func                  , "ob0_pll_func"                , OB0_TYPE   }, // 123
-    { OB0::ob0_repr                      , "ob0_repr"                    , OB0_TYPE   }, // 124
-    { INVALID_RING                       , "invalid"                     , OB0_TYPE   }, // 125
-    { INVALID_RING                       , "invalid"                     , OB0_TYPE   }, // 126
+    { OB0::ob0_pll_bndy_bucket_1         , "ob0_pll_bndy_bucket_1"       , OB0_TYPE   }, // 123
+    { OB0::ob0_pll_bndy_bucket_2         , "ob0_pll_bndy_bucket_2"       , OB0_TYPE   }, // 124
+    { OB0::ob0_pll_bndy_bucket_3         , "ob0_pll_bndy_bucket_3"       , OB0_TYPE   }, // 125
+    { OB0::ob0_repr                      , "ob0_repr"                    , OB0_TYPE   }, // 126
     { OB1::ob1_fure                      , "ob1_fure"                    , OB1_TYPE   }, // 127
     { OB1::ob1_gptr                      , "ob1_gptr"                    , OB1_TYPE   }, // 128
     { OB1::ob1_time                      , "ob1_time"                    , OB1_TYPE   }, // 129
     { OB1::ob1_pll_gptr                  , "ob1_pll_gptr"                , OB1_TYPE   }, // 130
     { OB1::ob1_pll_bndy                  , "ob1_pll_bndy"                , OB1_TYPE   }, // 131
-    { OB1::ob1_pll_func                  , "ob1_pll_func"                , OB1_TYPE   }, // 132
-    { OB1::ob1_repr                      , "ob1_repr"                    , OB1_TYPE   }, // 133
-    { INVALID_RING                       , "invalid"                     , OB1_TYPE   }, // 134
-    { INVALID_RING                       , "invalid"                     , OB1_TYPE   }, // 135
+    { OB1::ob1_pll_bndy_bucket_1         , "ob1_pll_bndy_bucket_1"       , OB1_TYPE   }, // 132
+    { OB1::ob1_pll_bndy_bucket_2         , "ob1_pll_bndy_bucket_2"       , OB1_TYPE   }, // 133
+    { OB1::ob1_pll_bndy_bucket_3         , "ob1_pll_bndy_bucket_3"       , OB1_TYPE   }, // 134
+    { OB1::ob1_repr                      , "ob1_repr"                    , OB1_TYPE   }, // 135
     { OB2::ob2_fure                      , "ob2_fure"                    , OB2_TYPE   }, // 136
     { OB2::ob2_gptr                      , "ob2_gptr"                    , OB2_TYPE   }, // 137
     { OB2::ob2_time                      , "ob2_time"                    , OB2_TYPE   }, // 138
     { OB2::ob2_pll_gptr                  , "ob2_pll_gptr"                , OB2_TYPE   }, // 139
     { OB2::ob2_pll_bndy                  , "ob2_pll_bndy"                , OB2_TYPE   }, // 140
-    { OB2::ob2_pll_func                  , "ob2_pll_func"                , OB2_TYPE   }, // 141
-    { OB2::ob2_repr                      , "ob2_repr"                    , OB2_TYPE   }, // 142
-    { INVALID_RING                       , "invalid"                     , OB2_TYPE   }, // 143
-    { INVALID_RING                       , "invalid"                     , OB2_TYPE   }, // 144
+    { OB2::ob2_pll_bndy_bucket_1         , "ob2_pll_bndy_bucket_1"       , OB2_TYPE   }, // 141
+    { OB2::ob2_pll_bndy_bucket_2         , "ob2_pll_bndy_bucket_2"       , OB2_TYPE   }, // 142
+    { OB2::ob2_pll_bndy_bucket_3         , "ob2_pll_bndy_bucket_3"       , OB2_TYPE   }, // 143
+    { OB2::ob2_repr                      , "ob2_repr"                    , OB2_TYPE   }, // 144
     { OB3::ob3_fure                      , "ob3_fure"                    , OB3_TYPE   }, // 145
     { OB3::ob3_gptr                      , "ob3_gptr"                    , OB3_TYPE   }, // 146
     { OB3::ob3_time                      , "ob3_time"                    , OB3_TYPE   }, // 147
     { OB3::ob3_pll_gptr                  , "ob3_pll_gptr"                , OB3_TYPE   }, // 148
     { OB3::ob3_pll_bndy                  , "ob3_pll_bndy"                , OB3_TYPE   }, // 149
-    { OB3::ob3_pll_func                  , "ob3_pll_func"                , OB3_TYPE   }, // 150
-    { OB3::ob3_repr                      , "ob3_repr"                    , OB3_TYPE   }, // 151
-    { INVALID_RING                       , "invalid"                     , OB3_TYPE   }, // 152
-    { INVALID_RING                       , "invalid"                     , OB3_TYPE   }, // 153
+    { OB3::ob3_pll_bndy_bucket_1         , "ob3_pll_bndy_bucket_1"       , OB3_TYPE   }, // 150
+    { OB3::ob3_pll_bndy_bucket_2         , "ob3_pll_bndy_bucket_2"       , OB3_TYPE   }, // 151
+    { OB3::ob3_pll_bndy_bucket_3         , "ob3_pll_bndy_bucket_3"       , OB3_TYPE   }, // 152
+    { OB3::ob3_repr                      , "ob3_repr"                    , OB3_TYPE   }, // 153
     { PCI0::pci0_fure                    , "pci0_fure"                   , PCI0_TYPE  }, // 154
     { PCI0::pci0_gptr                    , "pci0_gptr"                   , PCI0_TYPE  }, // 155
     { PCI0::pci0_time                    , "pci0_time"                   , PCI0_TYPE  }, // 156
@@ -1257,37 +1265,37 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { OB0::ob0_time                      , OB0_TYPE   }, // 120
     { OB0::ob0_pll_gptr                  , OB0_TYPE   }, // 121
     { OB0::ob0_pll_bndy                  , OB0_TYPE   }, // 122
-    { OB0::ob0_pll_func                  , OB0_TYPE   }, // 123
-    { OB0::ob0_repr                      , OB0_TYPE   }, // 124
-    { INVALID_RING                       , OB0_TYPE   }, // 125
-    { INVALID_RING                       , OB0_TYPE   }, // 126
+    { OB0::ob0_pll_bndy_bucket_1         , OB0_TYPE   }, // 123
+    { OB0::ob0_pll_bndy_bucket_2         , OB0_TYPE   }, // 124
+    { OB0::ob0_pll_bndy_bucket_3         , OB0_TYPE   }, // 125
+    { OB0::ob0_repr                      , OB0_TYPE   }, // 126
     { OB1::ob1_fure                      , OB1_TYPE   }, // 127
     { OB1::ob1_gptr                      , OB1_TYPE   }, // 128
     { OB1::ob1_time                      , OB1_TYPE   }, // 129
     { OB1::ob1_pll_gptr                  , OB1_TYPE   }, // 130
     { OB1::ob1_pll_bndy                  , OB1_TYPE   }, // 131
-    { OB1::ob1_pll_func                  , OB1_TYPE   }, // 132
-    { OB1::ob1_repr                      , OB1_TYPE   }, // 133
-    { INVALID_RING                       , OB1_TYPE   }, // 134
-    { INVALID_RING                       , OB1_TYPE   }, // 135
+    { OB1::ob1_pll_bndy_bucket_1         , OB1_TYPE   }, // 132
+    { OB1::ob1_pll_bndy_bucket_2         , OB1_TYPE   }, // 133
+    { OB1::ob1_pll_bndy_bucket_3         , OB1_TYPE   }, // 134
+    { OB1::ob1_repr                      , OB1_TYPE   }, // 135
     { OB2::ob2_fure                      , OB2_TYPE   }, // 136
     { OB2::ob2_gptr                      , OB2_TYPE   }, // 137
     { OB2::ob2_time                      , OB2_TYPE   }, // 138
     { OB2::ob2_pll_gptr                  , OB2_TYPE   }, // 139
     { OB2::ob2_pll_bndy                  , OB2_TYPE   }, // 140
-    { OB2::ob2_pll_func                  , OB2_TYPE   }, // 141
-    { OB2::ob2_repr                      , OB2_TYPE   }, // 142
-    { INVALID_RING                       , OB2_TYPE   }, // 143
-    { INVALID_RING                       , OB2_TYPE   }, // 144
+    { OB2::ob2_pll_bndy_bucket_1         , OB2_TYPE   }, // 141
+    { OB2::ob2_pll_bndy_bucket_2         , OB2_TYPE   }, // 142
+    { OB2::ob2_pll_bndy_bucket_3         , OB2_TYPE   }, // 143
+    { OB2::ob2_repr                      , OB2_TYPE   }, // 144
     { OB3::ob3_fure                      , OB3_TYPE   }, // 145
     { OB3::ob3_gptr                      , OB3_TYPE   }, // 146
     { OB3::ob3_time                      , OB3_TYPE   }, // 147
     { OB3::ob3_pll_gptr                  , OB3_TYPE   }, // 148
     { OB3::ob3_pll_bndy                  , OB3_TYPE   }, // 149
-    { OB3::ob3_pll_func                  , OB3_TYPE   }, // 150
-    { OB3::ob3_repr                      , OB3_TYPE   }, // 151
-    { INVALID_RING                       , OB3_TYPE   }, // 152
-    { INVALID_RING                       , OB3_TYPE   }, // 153
+    { OB3::ob3_pll_bndy_bucket_1         , OB3_TYPE   }, // 150
+    { OB3::ob3_pll_bndy_bucket_2         , OB3_TYPE   }, // 151
+    { OB3::ob3_pll_bndy_bucket_3         , OB3_TYPE   }, // 152
+    { OB3::ob3_repr                      , OB3_TYPE   }, // 153
     { PCI0::pci0_fure                    , PCI0_TYPE  }, // 154
     { PCI0::pci0_gptr                    , PCI0_TYPE  }, // 155
     { PCI0::pci0_time                    , PCI0_TYPE  }, // 156
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
index bcd0b7c59..efd63394e 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
+++ b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
@@ -179,49 +179,53 @@ enum RingID
     ob0_gptr = 119,
     ob0_time = 120,
     ob0_pll_gptr = 121,
-    ob0_pll_bndy  = 122,
-    ob0_pll_func = 123,
+    ob0_pll_bndy = 122,
+    ob0_pll_bndy_bucket_1 = 123,
+    ob0_pll_bndy_bucket_2 = 124,
+    ob0_pll_bndy_bucket_3 = 125,
 
     // OB Chiplet Rings
     // OB0, OB1, OB2 and OB3 instance specific Ring
-    ob0_repr = 124,
-    // values 125-126 unused
+    ob0_repr = 126,
 
     ob1_fure = 127,
     ob1_gptr = 128,
     ob1_time = 129,
     ob1_pll_gptr = 130,
     ob1_pll_bndy  = 131,
-    ob1_pll_func = 132,
+    ob1_pll_bndy_bucket_1 = 132,
+    ob1_pll_bndy_bucket_2 = 133,
+    ob1_pll_bndy_bucket_3 = 134,
 
     // OB Chiplet Rings
     // OB0, OB1, OB2 and OB3 instance specific Ring
-    ob1_repr = 133,
-    // values 134-135 unused
+    ob1_repr = 135,
 
     ob2_fure = 136,
     ob2_gptr = 137,
     ob2_time = 138,
     ob2_pll_gptr = 139,
     ob2_pll_bndy  = 140,
-    ob2_pll_func = 141,
+    ob2_pll_bndy_bucket_1 = 141,
+    ob2_pll_bndy_bucket_2 = 142,
+    ob2_pll_bndy_bucket_3 = 143,
 
     // OB Chiplet Rings
     // OB0, OB1, OB2 and OB3 instance specific Ring
-    ob2_repr = 142,
-    // values 143-144 unused
+    ob2_repr = 144,
 
     ob3_fure = 145,
     ob3_gptr = 146,
     ob3_time = 147,
     ob3_pll_gptr = 148,
     ob3_pll_bndy  = 149,
-    ob3_pll_func = 150,
+    ob3_pll_bndy_bucket_1 = 150,
+    ob3_pll_bndy_bucket_2 = 151,
+    ob3_pll_bndy_bucket_3 = 152,
 
     // OB Chiplet Rings
     // OB0, OB1, OB2 and OB3 instance specific Ring
-    ob3_repr = 151,
-    // values 152-153 unused
+    ob3_repr = 153,
 
     // PCI Chiplet Rings
     // PCI0 Common Rings
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index f875ca903..8ee6cb0f4 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -2701,6 +2701,7 @@
     </uint32_t></simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
+    <writeable/><!-- Only because SBE needs it -->
     <hwpfToHbAttrMap>
         <id>ATTR_FREQ_A_MHZ</id>
         <macro>DIRECT</macro>
@@ -2708,6 +2709,95 @@
 </attribute>
 
 <attribute>
+    <id>FREQ_O_MHZ</id>
+    <description>
+    The frequency of a processor's Obus mesh clocks, in MHz.
+    Provided by the MRW.
+    </description>
+    <simpleType>
+       <uint32_t>
+       <default>1611</default>
+       </uint32_t>
+      <array>4</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/><!-- Only because SBE needs it -->
+    <hwpfToHbAttrMap>
+        <id>ATTR_FREQ_O_MHZ</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>OB0_PLL_BUCKET</id>
+  <description>
+      Select OBUS0 pll setting from one of the supported frequencies
+  </description>
+  <simpleType>
+      <uint8_t><default>1</default></uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <writeable/><!-- Only because SBE needs it -->
+  <hwpfToHbAttrMap>
+    <id>ATTR_OB0_PLL_BUCKET</id>
+    <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>OB1_PLL_BUCKET</id>
+  <description>
+      Select OBUS1 pll setting from one of the supported frequencies
+  </description>
+  <simpleType>
+      <uint8_t><default>1</default></uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <writeable/><!-- Only because SBE needs it -->
+  <hwpfToHbAttrMap>
+    <id>ATTR_OB1_PLL_BUCKET</id>
+    <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>OB2_PLL_BUCKET</id>
+  <description>
+      Select OBUS2 pll setting from one of the supported frequencies
+  </description>
+  <simpleType>
+      <uint8_t><default>1</default></uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <writeable/><!-- Only because SBE needs it -->
+  <hwpfToHbAttrMap>
+    <id>ATTR_OB2_PLL_BUCKET</id>
+    <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>OB3_PLL_BUCKET</id>
+  <description>
+      Select OBUS3 pll setting from one of the supported frequencies
+  </description>
+  <simpleType>
+      <uint8_t><default>1</default></uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <writeable/><!-- Only because SBE needs it -->
+  <hwpfToHbAttrMap>
+    <id>ATTR_OB3_PLL_BUCKET</id>
+    <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>FREQ_X_MHZ</id>
     <description>
         System attribute.
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 38085de50..0e9ac7d6d 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1100,6 +1100,11 @@
     <attribute><id>MC_SYNC_MODE</id></attribute>
     <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
     <attribute><id>OBUS_RATIO_VALUE</id></attribute>
+    <attribute><id>OB0_PLL_BUCKET</id></attribute>
+    <attribute><id>OB1_PLL_BUCKET</id></attribute>
+    <attribute><id>OB2_PLL_BUCKET</id></attribute>
+    <attribute><id>OB3_PLL_BUCKET</id></attribute>
+    <attribute><id>FREQ_O_MHZ</id></attribute>
     <attribute><id>FUNCTIONAL_EQ_EC_VALID</id></attribute>
     <attribute><id>FW_MODE_FLAGS_VALID</id></attribute>
     <attribute><id>ISTEP_MODE</id></attribute>