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author | Prachi Gupta <pragupta@us.ibm.com> | 2014-07-23 14:21:53 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-08-01 14:04:13 -0500 |
commit | 3a96a05d54054321d9428c0f177d411cbcd3bd0e (patch) | |
tree | 84100ac399e3d8719787bf49aaa297f6e6706c43 /src | |
parent | 96ca27951c620213afdb1bfe96f996fbeaf8a74b (diff) | |
download | talos-hostboot-3a96a05d54054321d9428c0f177d411cbcd3bd0e.tar.gz talos-hostboot-3a96a05d54054321d9428c0f177d411cbcd3bd0e.zip |
Created an error log when masterCore not found
Change-Id: I802225d8fbc8fde515df1a0bb271735562f504f8
RTC:107731
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/12416
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/include/usr/hwas/hwasplatreasoncodes.H | 5 | ||||
-rw-r--r-- | src/usr/hwas/hostbootIstep.C | 155 |
2 files changed, 103 insertions, 57 deletions
diff --git a/src/include/usr/hwas/hwasplatreasoncodes.H b/src/include/usr/hwas/hwasplatreasoncodes.H index 721863ba1..af7201809 100644 --- a/src/include/usr/hwas/hwasplatreasoncodes.H +++ b/src/include/usr/hwas/hwasplatreasoncodes.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2014 */ +/* Contributors Listed Below - COPYRIGHT 2014 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -46,6 +48,7 @@ namespace HWAS RC_TARGET_NOT_GARDABLE = HWAS_COMP_ID | 0x81, RC_GARD_REPOSITORY_FULL = HWAS_COMP_ID | 0x82, RC_BAD_CHIPID = HWAS_COMP_ID | 0x83, + RC_MASTER_CORE_NULL = HWAS_COMP_ID | 0x84, }; }; diff --git a/src/usr/hwas/hostbootIstep.C b/src/usr/hwas/hostbootIstep.C index fa64ab222..6b01b28fd 100644 --- a/src/usr/hwas/hostbootIstep.C +++ b/src/usr/hwas/hostbootIstep.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2014 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -151,77 +153,118 @@ void* host_discover_targets( void *io_pArgs ) void* host_gard( void *io_pArgs ) { TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_gard entry" ); - errlHndl_t errl; - // Check whether we're in MPIPL mode - TARGETING::Target* l_pTopLevel = NULL; - targetService().getTopLevelTarget( l_pTopLevel ); - HWAS_ASSERT(l_pTopLevel, "HWAS host_gard: no TopLevelTarget"); + do { + // Check whether we're in MPIPL mode + TARGETING::Target* l_pTopLevel = NULL; + targetService().getTopLevelTarget( l_pTopLevel ); + HWAS_ASSERT(l_pTopLevel, "HWAS host_gard: no TopLevelTarget"); - if (l_pTopLevel->getAttr<ATTR_IS_MPIPL_HB>()) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "MPIPL mode"); + if (l_pTopLevel->getAttr<ATTR_IS_MPIPL_HB>()) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "MPIPL mode"); - // we only want EX units to be processed - TARGETING::PredicateCTM l_exFilter(TARGETING::CLASS_UNIT, + // we only want EX units to be processed + TARGETING::PredicateCTM l_exFilter(TARGETING::CLASS_UNIT, TARGETING::TYPE_EX); - errl = collectGard(&l_exFilter); - } - else - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Normal IPL mode"); + errl = collectGard(&l_exFilter); + if (errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "collectGard returned error; breaking out"); + break; + } + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Normal IPL mode"); - errl = collectGard(); + errl = collectGard(); + if(errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "collectGard returned error; breaking out"); + break; + } - if (errl == NULL) - { - // check and see if we still have enough hardware to continue - errl = checkMinimumHardware(); + if (errl == NULL) + { + // check and see if we still have enough hardware to continue + errl = checkMinimumHardware(); + if(errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "check minimum hardware returned error; breaking out"); + break; + } + } + // If targets are deconfigured as a result of host_gard, they are + // done so using the PLID as the reason for deconfiguration. This + // triggers the reconfigure loop attribute to be set, which causes + // undesirable behavior, so we need to reset it here: + + // Read current value + TARGETING::ATTR_RECONFIGURE_LOOP_type l_reconfigAttr = + l_pTopLevel->getAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(); + // Turn off deconfigure bit + l_reconfigAttr &= ~TARGETING::RECONFIGURE_LOOP_DECONFIGURE; + // Write back to attribute + l_pTopLevel->setAttr<TARGETING::ATTR_RECONFIGURE_LOOP> + (l_reconfigAttr); } - // If targets are deconfigured as a result of host_gard, they are - // done so using the PLID as the reason for deconfiguration. This - // triggers the reconfigure loop attribute to be set, which causes - // undesirable behavior, so we need to reset it here: - - // Read current value - TARGETING::ATTR_RECONFIGURE_LOOP_type l_reconfigAttr = - l_pTopLevel->getAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(); - // Turn off deconfigure bit - l_reconfigAttr &= ~TARGETING::RECONFIGURE_LOOP_DECONFIGURE; - // Write back to attribute - l_pTopLevel->setAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(l_reconfigAttr); - } - // Send message to FSP sending HUID of EX chip associated with master core - msg_t * core_msg = msg_allocate(); - core_msg->type = SBE::MSG_IPL_MASTER_CORE; - const TARGETING::Target* l_masterCore = TARGETING::getMasterCore( ); - HWAS_ASSERT(l_masterCore, "HWAS host_gard: no masterCore found"); - // Get the EX chip associated with the master core as that is the chip that - // has the IS_MASTER_EX attribute associated with it - TARGETING::TargetHandleList targetList; - getParentAffinityTargets(targetList, + // Send message to FSP sending HUID of EX chip associated with + // master core + msg_t * core_msg = msg_allocate(); + core_msg->type = SBE::MSG_IPL_MASTER_CORE; + const TARGETING::Target* l_masterCore = TARGETING::getMasterCore( ); + + /*@ errorlog tag + * @errortype ERRL_SEV_CRITICAL_SYS_TERM + * @moduleid MOD_HOST_GARD + * @reasoncode RC_MASTER_CORE_NULL + * @userdata1 0 + * @userdata2 0 + * @devdesc HWAS host_gard: no masterCore found + */ + if (l_masterCore == NULL) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "No masterCore Found" ); + const bool hbSwError = true; + errl = new ERRORLOG::ErrlEntry + (ERRORLOG::ERRL_SEV_CRITICAL_SYS_TERM, + HWAS::MOD_HOST_GARD, + HWAS::RC_MASTER_CORE_NULL, + 0, 0, hbSwError); + break; + } + // Get the EX chip associated with the master core as that is the + // chip that + // has the IS_MASTER_EX attribute associated with it + TARGETING::TargetHandleList targetList; + getParentAffinityTargets(targetList, l_masterCore, TARGETING::CLASS_UNIT, TARGETING::TYPE_EX); - HWAS_ASSERT(targetList.size() == 1, + HWAS_ASSERT(targetList.size() == 1, "HWAS host_gard: Incorrect EX chip(s) associated with masterCore"); - core_msg->data[0] = 0; - core_msg->data[1] = TARGETING::get_huid( targetList[0] ); - core_msg->extra_data = NULL; - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + core_msg->data[0] = 0; + core_msg->data[1] = TARGETING::get_huid( targetList[0] ); + core_msg->extra_data = NULL; + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Sending MSG_MASTER_CORE message with HUID %08x", core_msg->data[1]); - errl = MBOX::send(MBOX::IPL_SERVICE_QUEUE,core_msg); - if (errl) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + errl = MBOX::send(MBOX::IPL_SERVICE_QUEUE,core_msg); + if (errl) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK"MBOX::send failed sending Master Core message"); - msg_free(core_msg); - - } - + msg_free(core_msg); + break; + } + } while (0); TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_gard exit" ); return errl; |