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| author | Brian Silver <bsilver@us.ibm.com> | 2016-03-11 14:43:25 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-03 16:01:51 -0500 |
| commit | 3a104012b92d305fe6f0a9fadf1939a3cc126a17 (patch) | |
| tree | 62fc266fe51dfdf079e0772001ea770d256cbbd6 /src | |
| parent | 03991067ed8552f7f4cdcb734c62d72b310af035 (diff) | |
| download | talos-hostboot-3a104012b92d305fe6f0a9fadf1939a3cc126a17.tar.gz talos-hostboot-3a104012b92d305fe6f0a9fadf1939a3cc126a17.zip | |
Change address translation registers to account for MCA odd ports
Change-Id: I4b06f2924f3febbb2d11660cba33d5bb6f6f2fc0
Original-Change-Id: I3c2dc6e8e888736c19fc716e5de23f9009d44343
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21949
Tested-by: Jenkins Server
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37391
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index ce65a3e1c..a04f432d7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -76,6 +76,14 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_INF("Setting up xlate registers for MCA%d (%d)", mss::pos(i_target), mss::index(i_target)); + // The addressing for the xlt registers is funky. We have a different unit0 address for units 0/2 + // than we do for 1/3. + const uint64_t& l_t0_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT0 : MCS_0_PORT02_MCP0XLT0; + const uint64_t& l_t1_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT1 : MCS_0_PORT02_MCP0XLT1; + const uint64_t& l_t2_address = mss::pos(i_target) % 2 ? MCS_0_PORT13_MCP0XLT2 : MCS_0_PORT02_MCP0XLT2; + + FAPI_DBG("xlate scoms registers 0x%016lx, 0x%016lx, 0x%016lx", l_t0_address, l_t1_address, l_t2_address); + // We enable the DIMM select bit for slot1 if we have two DIMM installed l_xlate.writeBit<MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE>(l_dimms.size() == 2); @@ -208,9 +216,9 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT1", l_xlate1); FAPI_DBG("HACK: Cramming 0x%016lx in for MCP0XLT2", l_xlate2); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), MCS_0_PORT02_MCP0XLT0, l_xlate) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), MCS_0_PORT02_MCP0XLT1, l_xlate1) ); - FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), MCS_0_PORT02_MCP0XLT2, l_xlate2) ); + FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t0_address, l_xlate) ); + FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t1_address, l_xlate1) ); + FAPI_TRY( mss::putScom(i_target.getParent<TARGET_TYPE_MCS>(), l_t2_address, l_xlate2) ); fapi_try_exit: return fapi2::current_err; |
