Support P8 mambo model and Murano proc.

RTC: 38206
Change-Id: Iab79041931db533ad6b6ebd057c1ef9fe4c4b8cc
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/714
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

12 files changed, 39 insertions, 23 deletions

diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 8a7ea500c..7836ed2b0 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -48,6 +48,11 @@ sed -i -e's/SETENV GFW_P8_MURANO_L3_MB_SIZE.*/SETENV GFW_P8_MURANO_L3_MB_SIZE 8/
 # Backing build already contains 910431.  Leave this workaround here for future scomdef files
 #sed -i -e's/SETENV GFW_P8_MURANO_MODEL_EC.*/SETENV GFW_P8_MURANO_MODEL_EC 910431/' $sb/simu/configs/P8_MURANO.config
 
+echo "+++ Enable P8 Mambo and 8-threads."
+sed -i -e's/SETENV GFW_P8_VENICE_ENABLE_P8_PROC.*/SETENV GFW_P8_VENICE_ENABLE_P8_PROC yes/' $sb/simu/configs/P8_VENICE.config
+sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_VENICE.config
+sed -i -e's/SETENV GFW_P8_MURANO_ENABLE_P8_PROC.*/SETENV GFW_P8_MURANO_ENABLE_P8_PROC yes/' $sb/simu/configs/P8_MURANO.config
+sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_MURANO.config
 
 #Note: Leave this here as an example
 #echo "+++ Some message about why you need to do this."
diff --git a/src/include/kernel/cpu.H b/src/include/kernel/cpu.H
index f308fb4be..b6fe66ef2 100644
--- a/src/include/kernel/cpu.H
+++ b/src/include/kernel/cpu.H
@@ -33,8 +33,8 @@
 #include <builtins.h>
 #include <sys/sync.h>
 
-// Thread ID support only, Power7 (4 threads).
-#define KERNEL_MAX_SUPPORTED_CPUS (4 * 8 * 4) // Sockets, cores, threads.
+// Thread ID support only, Power8 (8 threads).
+#define KERNEL_MAX_SUPPORTED_CPUS (8 * 16 * 8) // Sockets, cores, threads.
 
 class Scheduler;
 
diff --git a/src/include/sys/misc.h b/src/include/sys/misc.h
index 59b6c10bd..d07c5afff 100644
--- a/src/include/sys/misc.h
+++ b/src/include/sys/misc.h
@@ -64,8 +64,8 @@ enum ProcessorCoreType
     /** Power7+ */
     CORE_POWER7_PLUS,
 
-    /** Power8 "Salerno" (low-end) core */
-    CORE_POWER8_SALERNO,
+    /** Power8 "Murano" (low-end) core */
+    CORE_POWER8_MURANO,
     /** Power8 "Venice" (high-end) core */
     CORE_POWER8_VENICE,
 
diff --git a/src/kernel/basesegment.C b/src/kernel/basesegment.C
index 7b33eed7a..780c60792 100644
--- a/src/kernel/basesegment.C
+++ b/src/kernel/basesegment.C
@@ -52,13 +52,10 @@ void BaseSegment::_init()
     {
         case CORE_POWER7:
         case CORE_POWER7_PLUS:
+        case CORE_POWER8_MURANO:
         case CORE_POWER8_VENICE:
-            iv_physMemSize = (8*MEGABYTE);
-            break;
-
-        case CORE_POWER8_SALERNO:
         default:
-            iv_physMemSize = (4*MEGABYTE);
+            iv_physMemSize = (8*MEGABYTE);
             break;
     }
     // Base block is L3 cache physical memory size
diff --git a/src/kernel/cpuid.C b/src/kernel/cpuid.C
index d54dada3d..e75bc64b5 100644
--- a/src/kernel/cpuid.C
+++ b/src/kernel/cpuid.C
@@ -40,8 +40,6 @@ namespace CpuID
         //     1 nibble reserved.
         //     1 nibble minor DD.
 
-        // TODO: Salerno PVR support.
-
         switch(l_pvr & 0xFFFF0000)
         {
             case 0x003F0000:
@@ -51,6 +49,9 @@ namespace CpuID
                 return CORE_POWER7_PLUS;
 
             case 0x004B0000:
+                return CORE_POWER8_MURANO;
+
+            case 0x004D0000:
                 return CORE_POWER8_VENICE;
 
             default:
diff --git a/src/kernel/cpumgr.C b/src/kernel/cpumgr.C
index 626ad7f84..eb1ad3ac2 100644
--- a/src/kernel/cpumgr.C
+++ b/src/kernel/cpumgr.C
@@ -84,7 +84,7 @@ void CpuManager::init()
             break;
 
         case CORE_POWER8_VENICE:
-        case CORE_POWER8_SALERNO:
+        case CORE_POWER8_MURANO:
             threads = 8;
             break;
 
diff --git a/src/kernel/exception.C b/src/kernel/exception.C
index 6ce01bc96..78f43d581 100644
--- a/src/kernel/exception.C
+++ b/src/kernel/exception.C
@@ -205,7 +205,7 @@ void kernel_execute_softpatch()
         {
             case CORE_POWER7:
             case CORE_POWER7_PLUS:
-            case CORE_POWER8_SALERNO: // @TODO: Verify same procedure.
+            case CORE_POWER8_MURANO: // @TODO: Verify same procedure.
             case CORE_POWER8_VENICE:  // @TODO: Verify same procedure.
             case CORE_UNKNOWN:
                 p7_softpatch_denorm_assist(t->fp_context);
diff --git a/src/kernel/misc.C b/src/kernel/misc.C
index 082e45020..513844875 100644
--- a/src/kernel/misc.C
+++ b/src/kernel/misc.C
@@ -39,7 +39,7 @@ namespace KernelMisc
             register uint64_t scratch_address = 0; // Values from PervSpec
             switch(CpuID::getCpuType())
             {
-                case CORE_POWER8_SALERNO:
+                case CORE_POWER8_MURANO:
                 case CORE_POWER8_VENICE:
                     scratch_address = 0x40;
                     break;
@@ -60,8 +60,8 @@ namespace KernelMisc
         // dump whatever is left in g_tracBinary
         MAGIC_INSTRUCTION(MAGIC_CONTINUOUS_TRACE);
 
-        // See magic_instruction_callback() in 
-        // src/build/debug/simics-debug-framework.py 
+        // See magic_instruction_callback() in
+        // src/build/debug/simics-debug-framework.py
         // for exactly how this is handled.
         MAGIC_INSTRUCTION(MAGIC_SHUTDOWN);
 
diff --git a/src/lib/syscall_misc.C b/src/lib/syscall_misc.C
index ac9070a40..897012daa 100644
--- a/src/lib/syscall_misc.C
+++ b/src/lib/syscall_misc.C
@@ -54,7 +54,7 @@ size_t cpu_thread_count()
             threads = 4;
             break;
 
-        case CORE_POWER8_SALERNO:
+        case CORE_POWER8_MURANO:
         case CORE_POWER8_VENICE:
             threads = 8;
             break;
diff --git a/src/lib/syscall_mmio.C b/src/lib/syscall_mmio.C
index a875e560b..8b2e49f0f 100644
--- a/src/lib/syscall_mmio.C
+++ b/src/lib/syscall_mmio.C
@@ -66,7 +66,7 @@ static uint64_t mmio_scratch_base()
         case CORE_POWER7_PLUS:
             return 0x20;
 
-        case CORE_POWER8_SALERNO:
+        case CORE_POWER8_MURANO:
         case CORE_POWER8_VENICE:
         case CORE_UNKNOWN:
         default:
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index bb407bc02..43e7eaaa7 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -28,6 +28,7 @@
 #include <limits.h>
 #include <errl/errlentry.H>
 #include <sys/msg.h>
+#include <sys/misc.h>
 #include <intr/interrupt.H>
 #include <map>
 
@@ -50,7 +51,7 @@ namespace INTR
             /**
              * Constructor
              */
-            IntrRp() : 
+            IntrRp() :
                 iv_msgQ(NULL),
                 iv_baseAddr(0),
                 iv_masterCpu(0),
@@ -100,7 +101,7 @@ namespace INTR
 
             /**
              * cpu PIR register
-             * @note TODO P7 bits - thread 2, core 3, chip 2, node 3, 
+             * @note TODO P7 bits - thread 2, core 3, chip 2, node 3,
              *            P8 will be different. Need P8 book IV
              */
             struct PIR_t
@@ -136,7 +137,7 @@ namespace INTR
             errlHndl_t _init();
 
             /**
-             * Message handler 
+             * Message handler
              */
             void msgHandler();
 
@@ -173,7 +174,19 @@ namespace INTR
                 {
                     uint64_t offset = (i_pir.nodeId  * 8) + i_pir.chipId;
                     offset <<= 20;
-                    offset |= static_cast<uint64_t>(i_pir.coreId) << 14;
+                    switch (cpu_core_type())
+                    {
+                        case CORE_POWER7:
+                        case CORE_POWER7_PLUS:
+                            offset |= static_cast<uint64_t>(i_pir.coreId) << 14;
+                            break;
+
+                        case CORE_POWER8_MURANO:
+                        case CORE_POWER8_VENICE:
+                        default:
+                            offset |= static_cast<uint64_t>(i_pir.coreId) << 15;
+                            break;
+                    }
                     offset |= static_cast<uint64_t>(i_pir.threadId) << 12;
                     return offset;
                 }
diff --git a/src/usr/xscom/xscom.C b/src/usr/xscom/xscom.C
index 8ea937715..9ee6222f2 100644
--- a/src/usr/xscom/xscom.C
+++ b/src/usr/xscom/xscom.C
@@ -215,7 +215,7 @@ uint8_t getMaxChipsPerNode()
     // for both Salerno and Venice
     switch (l_coreType)
     {
-        case CORE_POWER8_SALERNO:
+        case CORE_POWER8_MURANO:
         case CORE_POWER8_VENICE:
         case CORE_UNKNOWN:
         default: