Additional changes to support new NPU_MMIO_BAR attributes

Change-Id: I4da9edd752f45d3066210d100ad8e280ffcdabdb
CQ:SW295054
Backport: release-fips830
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17077
Tested-by: Jenkins Server
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 121 insertions, 55 deletions

diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index 11d519077..e08b79629 100644
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -430,51 +430,6 @@ fapi::ReturnCode fapiPlatGetProcPcieBarSize (
 
 /**
  * @brief This function is called by the FAPI_ATTR_GET macro when getting
- * ATTR_PROC_NPU_MMIO_BAR_ENABLE
- * It should not be called directly.
- *
- *  @param[in]  i_pTarget       Target pointer
- *  @param[out] o_mmioBarEnable NPU MMIO Bar Enable
- *                          @note:  the array size of 4,2 was pulled from
- *                          the xml file and is not expected to change.
- *  @return     ReturnCode. Zero on success, else platform specified error
- */
-fapi::ReturnCode fapiPlatGetNpuMmioBarEnable (
-                                    const fapi::Target * i_pTarget,
-                                    uint8_t    (&o_mmioBarEnable) [4][2] );
-
-/**
- * @brief This function is called by the FAPI_ATTR_GET macro when getting
- * ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR
- * It should not be called directly.
- *
- *  @param[in]  i_pTarget         Target pointer
- *  @param[out] o_mmioBarBaseAddr NPU MMIO Bar Base Address
- *                          @note:  the array size of 4,2 was pulled from
- *                          the xml file and is not expected to change.
- *  @return     ReturnCode. Zero on success, else platform specified error
- */
-fapi::ReturnCode fapiPlatGetNpuMmioBarBaseAddr (
-                                    const fapi::Target * i_pTarget,
-                                    uint64_t    (&o_mmioBarBaseAddr) [4][2] );
-
-/**
- * @brief This function is called by the FAPI_ATTR_GET macro when getting
- * ATTR_PROC_NPU_MMIO_BAR_SIZE
- * It should not be called directly.
- *
- *  @param[in]  i_pTarget       Target pointer
- *  @param[out] o_mmioBarSize   NPU MMIO Bar Size
- *                          @note:  the array size of 4,2 was pulled from
- *                          the xml file and is not expected to change.
- *  @return     ReturnCode. Zero on success, else platform specified error
- */
-fapi::ReturnCode fapiPlatGetNpuMmioBarSize (
-                                    const fapi::Target * i_pTarget,
-                                    uint64_t    (&o_mmioBarSize) [4][2] );
-
-/**
- * @brief This function is called by the FAPI_ATTR_GET macro when getting
  * ATTR_EX_L2_SINGLE_MEMBER_ENABLE. It should not be called directly.
  *
  *  @param[in]  i_pTarget Target MB pointer
@@ -1235,15 +1190,6 @@ fapi::ReturnCode fapiPlatGetRCDCntlWord015 (const fapi::Target * i_pTarget,
 #define ATTR_PROC_PCIE_BAR_SIZE_GETMACRO( ID, PTARGET, VAL )   \
     fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
     fapi::platAttrSvc::fapiPlatGetProcPcieBarSize (PTARGET, VAL )
-#define ATTR_PROC_NPU_MMIO_BAR_ENABLE_GETMACRO( ID, PTARGET, VAL )   \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetNpuMmioBarEnable (PTARGET, VAL )
-#define ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_GETMACRO( ID, PTARGET, VAL )   \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetNpuMmioBarBaseAddr (PTARGET, VAL )
-#define ATTR_PROC_NPU_MMIO_BAR_SIZE_GETMACRO( ID, PTARGET, VAL )   \
-    fapi::AttrOverrideSync::getAttrOverrideFunc(fapi::ID, PTARGET, &VAL) ? fapi::FAPI_RC_SUCCESS : \
-    fapi::platAttrSvc::fapiPlatGetNpuMmioBarSize (PTARGET, VAL )
 
 //------------------------------------------------------------------------------
 //  MACROS to support enable attributes in p8_xip_customize_attributes.xml
diff --git a/src/usr/targeting/common/processMrw.pl b/src/usr/targeting/common/processMrw.pl
index 0469779eb..351584169 100644
--- a/src/usr/targeting/common/processMrw.pl
+++ b/src/usr/targeting/common/processMrw.pl
@@ -580,7 +580,7 @@ sub setupBars
     my $proc   = $targetObj->getAttribute($target, "FABRIC_CHIP_ID");
     $targetObj->{TOPOLOGY}->{$node}->{$proc}++;
 
-    my @bars=("FSP_BASE_ADDR","PSI_BRIDGE_BASE_ADDR",
+    my @bars=("NPU_MMIO_BAR_BASE_ADDR","FSP_BASE_ADDR","PSI_BRIDGE_BASE_ADDR",
               "INTP_BASE_ADDR","PHB_BASE_ADDRS","PCI_BASE_ADDRS_32",
               "PCI_BASE_ADDRS_64","RNG_BASE_ADDR","IBSCOM_PROC_BASE_ADDR");
 
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 003c303c7..ec256dedd 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -2789,6 +2789,116 @@
 
 <!-- ===== Processor Chip Attributes ===== -->
 
+<enumerationType>
+    <id>NPU_MMIO_BAR_ENABLE</id>
+    <description>Enumeration indicating whether MMIO BAR is enabled or not to be
+        used with ATTR_PROC_NPU_MMIO_BAR_ENABLE</description>
+    <enumerator>
+        <name>DISABLE</name>
+        <value>0</value>
+    </enumerator>
+    <enumerator>
+        <name>ENABLE</name>
+        <value>1</value>
+    </enumerator>
+</enumerationType>
+
+<attribute>
+    <id>NPU_MMIO_BAR_ENABLE</id>
+    <description>NPU MMIO BAR enables
+        creator: platform
+        consumer: proc_setup_bars
+        firmware notes: none
+            first dimension: unit number (0:3)
+            second dimension: BAR number (0:1)
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+<attribute>
+    <id>NPU_MMIO_BAR_BASE_ADDR</id>
+    <description>NPU MMIO BAR base address values
+        creator: platform
+        consumer: proc_setup_bars
+        firmware notes:
+            64-bit address representing BAR RA
+            NOTE: BAR register covers RA 14:51
+            first dimension: unit number (0:3)
+            second dimension: BAR number (0:1)
+    </description>
+    <simpleType>
+        <uint64_t>
+            <default>0</default>
+        </uint64_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<enumerationType>
+    <id>NPU_MMIO_BAR_SIZE</id>
+    <description>Enumeration indicating the BAR size
+        used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description>
+    <enumerator>
+        <name>2_MB</name>
+        <value>0x0000000000200000</value>
+    </enumerator>
+    <enumerator>
+        <name>1_MB</name>
+        <value>0x0000000000100000</value>
+    </enumerator>
+    <enumerator>
+        <name>512_KB</name>
+        <value>0x0000000000080000</value>
+    </enumerator>
+    <enumerator>
+        <name>256_KB</name>
+        <value>0x0000000000040000</value>
+    </enumerator>
+    <enumerator>
+        <name>128_KB</name>
+        <value>0x0000000000020000</value>
+    </enumerator>
+    <enumerator>
+        <name>64_KB</name>
+        <value>0x0000000000010000</value>
+    </enumerator>
+</enumerationType>
+<attribute>
+    <id>NPU_MMIO_BAR_SIZE</id>
+    <description>NPU MMIO BAR size values
+        creator: platform
+        consumer: proc_setup_bars
+        firmware notes: none
+            first dimension: unit number (0:3)
+            second dimension: BAR number (0:1)
+    </description>
+    <simpleType>
+        <uint64_t>
+            <default>0</default>
+        </uint64_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 <attribute>
     <id>FSP_BASE_ADDR</id>
     <description>Base Address of FSP IO Region</description>
diff --git a/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml b/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
index ae7e3402e..eab4d4e5e 100644
--- a/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NAPLES.system.xml
@@ -420,6 +420,9 @@
     </attribute>
     <attribute><id>VPD_REC_NUM</id><default>0</default></attribute>
 
+    <attribute><id>NPU_MMIO_BAR_BASE_ADDR</id>
+        <default>0x0003FFF000000000</default>
+    </attribute>
     <attribute><id>FSP_BASE_ADDR</id>
         <default>0x0003FFE000000000</default>
     </attribute>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 20190a9c8..15d7921d1 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -545,6 +545,10 @@
     </attribute>
 
     <!-- From PHYP Memory Map -->
+
+    <attribute><id>NPU_MMIO_BAR_ENABLE</id></attribute>
+    <attribute><id>NPU_MMIO_BAR_BASE_ADDR</id></attribute>
+    <attribute><id>NPU_MMIO_BAR_SIZE</id></attribute>
     <attribute><id>FSP_BASE_ADDR</id></attribute>
     <attribute><id>FSP_BAR_SIZE</id></attribute>
     <attribute><id>FSP_MMIO_MASK_SIZE</id></attribute>
diff --git a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
index 3c3302a1e..14263aa79 100644
--- a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml
@@ -357,6 +357,9 @@
     </attribute>
     <attribute><id>VPD_REC_NUM</id><default>0</default></attribute>
 
+    <attribute><id>NPU_MMIO_BAR_BASE_ADDR</id>
+        <default>0x0003FFF000000000</default>
+    </attribute>
     <attribute><id>FSP_BASE_ADDR</id>
         <default>0x0003FFE000000000</default>
     </attribute>