Make MURANO config work in Simics

This is work for Task 38048
-Updated bbuild to an 810 build with the latest Simics support
-Pulled support for Salerno from build tools
-Changed DEFAULT_MACHINE to MURANO
-Updated testcases to follow error logging guidelines
-Fixed up some FSI error handling bugs
-Disabled FSI loopback on VENICE (fix with Task 39187)
-Disabled a few testcases (see Impediment 39188)

Verified both MURANO and VENICE configurations

Change-Id: Ie7761f49c9e653489c8c4dad261b1c8852fa7548
RTC: 35596
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/791
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

20 files changed, 130 insertions, 598 deletions

diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild
index a3dc4f4e1..5bd980097 100644
--- a/src/build/citest/etc/bbuild
+++ b/src/build/citest/etc/bbuild
@@ -1 +1 @@
-/esw/fips760/Builds/b0229a_1209.760
+/esw/fips810/Builds/b0315a_1211.810
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 44eb1a37c..8e14b6f12 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -27,3 +27,7 @@
 ##    to setup the sandbox
 ##
 
+
+echo "+++ FIXME Temporarily copying cec-chip.so to eliminate verbose errors"
+rm  $sb/../simics/amd64-linux/lib/cec-chip.so
+cp /afs/rch/usr8/dsanner/public/fsi2host.correct/bin/cec-chip.so $sb/../simics/amd64-linux/lib/
diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup
index 0bba2c8b4..ca5f0a717 100755
--- a/src/build/citest/etc/workarounds.presimsetup
+++ b/src/build/citest/etc/workarounds.presimsetup
@@ -27,13 +27,6 @@
 ##    to setup the sandbox
 ##
 
-echo "+++ Copy desired SALERNO config file to sandbox and modify L3 to 8MB."
-mkdir -p $sb/simu/configs
-cp --update $BACKING_BUILD/src/simu/configs/P8_SALERNO.config $sb/simu/configs
-sed -i -e's/SETENV GFW_P8_SALERNO_L3_MB_SIZE.*/SETENV GFW_P8_SALERNO_L3_MB_SIZE 8/' $sb/simu/configs/P8_SALERNO.config
-# Backing build already contains 910431.  Leave this workaround here for future scomdef files
-#sed -i -e's/SETENV GFW_P8_SALERNO_MODEL_EC.*/SETENV GFW_P8_SALERNO_MODEL_EC 910431/' $sb/simu/configs/P8_SALERNO.config
-
 echo "+++ Copy desired VENICE config file to sandbox and modify L3 to 8MB."
 mkdir -p $sb/simu/configs
 cp --update $BACKING_BUILD/src/simu/configs/P8_VENICE.config $sb/simu/configs
@@ -61,35 +54,20 @@ sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREA
 #echo "WSALIAS HOSTBOOT_LEVEL FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo
 #echo "WSALIAS HOSTBOOT_LEVEL SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo
 
-echo "+++ Add some scom regs and actions for ECCB fakeout."
-mkdir -p $sb/simu/data/cec-chip/
-cp --update $BACKING_BUILD/src/simu/data/cec-chip/p8.chip $sb/simu/data/cec-chip/p8.chip.orig
-grep -v DONE $sb/simu/data/cec-chip/p8.chip.orig > $sb/simu/data/cec-chip/p8.chip
-echo "ACTIONS=p8_pnor.act   #workarounds.presimsetup" >> $sb/simu/data/cec-chip/p8.chip
-echo "SCOMREGS           #workarounds.presimsetup" >> $sb/simu/data/cec-chip/p8.chip
-echo "  0xDDDD0000,64  # dummy to hold pnor address" >> $sb/simu/data/cec-chip/p8.chip
-echo "  0xDDDD0001,64  # dummy to hold pnor data" >> $sb/simu/data/cec-chip/p8.chip
-echo "END" >> $sb/simu/data/cec-chip/p8.chip
-echo "DONE" >> $sb/simu/data/cec-chip/p8.chip
-cp $HOSTBOOTROOT/src/build/citest/etc/patches/p8_pnor.act $sb/simu/data/cec-chip/
-#fixme Story 37972
-
-
 echo "+++ Copy new centaur.act for DRAM hardware procedures."
 mkdir -p $sb/simu/data/cec-chip/
 cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip/
-#fixme
-
-
-# Leaving this here as an example for the future
-#echo "+++ Update to new phyp and mambo level."
-#mkdir -p $sb/simu/data
-#cp --update $BACKING_BUILD/src/simu/data/simicsInfo $sb/simu/data/simicsInfo
-#sed -i -e's/^WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL.*/WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL env\/mamboa\/2011_11_10__4.2/' $sb/simu/data/simicsInfo
-#sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYPLEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYPLEVEL env\/phypa\/simics-4.2.0\/simics-4.2.83\/ph120201a700.42/' $sb/simu/data/simicsInfo
-#sed -i -e's/^WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL.*/WSALIAS HOSTBOOT_LEVEL PHYP_PATCH_LEVEL env\/phypa\/simics-4.2.0\/simics-4.2.82\/patches\/ph120201a700.42/' $sb/simu/data/simicsInfo
+#fixme with Story 38362
 
 # added this patch until defect 825800 is integrated and included in a hostboot bbuild.
 echo "+++ Add workaround for p8 Indirect SCOM action files."
 cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910431.act $sb/simu/data/cec-chip/p8_indScom_910431.act
 cp --update $HOSTBOOTROOT/src/build/citest/etc/patches/p8_indScom_910520.act $sb/simu/data/cec-chip/p8_indScom_910520.act
+
+# Leaving this here as an example for the future
+echo "+++ Update to new phyp and mambo level."
+mkdir -p $sb/simu/data
+cp --update $BACKING_BUILD/src/simu/data/simicsInfo $sb/simu/data/simicsInfo
+#sed -i -e's/^WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL.*/WSALIAS HOSTBOOT_LEVEL MAMBOLEVEL env\/mamboa\/2011_11_10__4.2/' $sb/simu/data/simicsInfo
+sed -i -e's/^WSALIAS DEFAULT PHYPLEVEL.*/WSALIAS DEFAULT PHYPLEVEL env\/phypa\/simics-4.2.0\/simics-4.2.85\/ph120319a700.42/' $sb/simu/data/simicsInfo
+sed -i -e's/^WSALIAS DEFAULT PHYP_PATCH_LEVEL.*/WSALIAS DEFAULT PHYP_PATCH_LEVEL env\/phypa\/simics-4.2.0\/simics-4.2.85\/patches\/ph120319a700.42/' $sb/simu/data/simicsInfo 
diff --git a/src/build/tools/cpfiles.pl b/src/build/tools/cpfiles.pl
index 3a7781b0f..5e68a77bf 100755
--- a/src/build/tools/cpfiles.pl
+++ b/src/build/tools/cpfiles.pl
@@ -84,7 +84,6 @@ my %files = ("src/build/tools/hb-parsedump.pl" => "rsv",
              "img/hbicore.bin.modinfo" => "rsv",
              "img/hbicore_test.bin.modinfo" => "rsv",
              "img/pnor.toc" => "rsv",
-             "img/simics_SALERNO_targeting.bin" => "rs",
              "img/simics_VENICE_targeting.bin" => "rs",
              "img/simics_MURANO_targeting.bin" => "rs",
              "img/vbu_targeting.bin" => "rv",
diff --git a/src/build/tools/hb b/src/build/tools/hb
index 0ea3cdad7..5e2e513a6 100755
--- a/src/build/tools/hb
+++ b/src/build/tools/hb
@@ -118,7 +118,7 @@ hb_helptext()
         echo "  Requires the hostboot image to be 'prime'd into the workspace."
         echo
         echo "  Environment Variables:"
-        echo "      MACHINE: Alternate simics machine type (default SALERNO)"
+        echo "      MACHINE: Alternate simics machine type (default VENICE)"
         echo "      SIMICSOPTIONS: Additional options to always pass to the"
         echo "                     start simics script, such as '-nre'."
         echo
diff --git a/src/kernel/pagemgr.C b/src/kernel/pagemgr.C
index 6b36a1054..858215ecf 100644
--- a/src/kernel/pagemgr.C
+++ b/src/kernel/pagemgr.C
@@ -26,6 +26,8 @@
 #include <kernel/console.H>
 #include <arch/ppc.H>
 #include <util/locked/pqueue.H>
+#include <kernel/task.H>
+#include <kernel/taskmgr.H>
 
 size_t PageManager::cv_coalesce_count = 0;
 size_t PageManager::cv_low_page_count = -1;
@@ -118,7 +120,8 @@ void* PageManager::_allocatePage(size_t n)
     if (NULL == page)
     {
 	// TODO: Add abort instead.
-	printk("Insufficient memory for allocation of size %zd!\n", n);
+        task_t* t = TaskManager::getCurrentTask();
+	printk("Insufficient memory for alloc of size %zd on tid=%d!\n", n, t->tid);
 	while(1);
     }
 
diff --git a/src/usr/errl/errlmanager.C b/src/usr/errl/errlmanager.C
index 48bc22325..45a1fd3ca 100644
--- a/src/usr/errl/errlmanager.C
+++ b/src/usr/errl/errlmanager.C
@@ -129,6 +129,7 @@ void ErrlManager::commitErrLog(errlHndl_t& io_err, compId_t i_committerComp )
             break;
         }
 
+        TRACFCOMP(g_trac_errl, "commitErrLog() called by %.4X for plid=0x%X, Reasoncode=%.4X", i_committerComp, io_err->plid(), io_err->reasonCode() );
 
         // lock sem
         mutex_lock(&iv_mutex);
diff --git a/src/usr/errl/test/errltest.H b/src/usr/errl/test/errltest.H
index 9fbc02fcc..2abca0d09 100644
--- a/src/usr/errl/test/errltest.H
+++ b/src/usr/errl/test/errltest.H
@@ -251,7 +251,7 @@ public:
 
 
             // Commit error log with different component ID.
-            errlCommit(l_err, FSI_COMP_ID);
+            errlCommit(l_err, CXXTEST_COMP_ID);
 
             // Make sure error log has been deleted by manager
             if (l_err != NULL)
diff --git a/src/usr/errl/test/errluserdetailtest.H b/src/usr/errl/test/errluserdetailtest.H
index 5ac4e9084..8fb1f3ed5 100644
--- a/src/usr/errl/test/errluserdetailtest.H
+++ b/src/usr/errl/test/errluserdetailtest.H
@@ -73,7 +73,7 @@ public:
         ErrlUserDetailsString(l_pString).addToLog(l_errl);
 
         // commit the errorlog
-        errlCommit(l_errl, HBERRL_COMP_ID);
+        errlCommit(l_errl, CXXTEST_COMP_ID);
     }
 
 };
diff --git a/src/usr/fsi/fsidd.C b/src/usr/fsi/fsidd.C
index fef1e47b0..94423c3da 100644
--- a/src/usr/fsi/fsidd.C
+++ b/src/usr/fsi/fsidd.C
@@ -716,8 +716,12 @@ errlHndl_t FsiDD::read(const FsiAddrInfo_t& i_addrInfo,
         l_mutex
             = (i_addrInfo.opbTarg)->getHbMutexAttr<TARGETING::ATTR_FSI_MASTER_MUTEX>();
 
-        mutex_lock(l_mutex);
-        need_unlock = true;
+        // skip the mutex lock if we're already inside a previous operation
+        if( !iv_ffdcCollection )
+        {
+            mutex_lock(l_mutex);
+            need_unlock = true;
+        }
 
         // always read/write 64 bits to SCOM
         size_t scom_size = sizeof(uint64_t);
@@ -790,8 +794,12 @@ errlHndl_t FsiDD::write(const FsiAddrInfo_t& i_addrInfo,
         l_mutex
             = (i_addrInfo.opbTarg)->getHbMutexAttr<TARGETING::ATTR_FSI_MASTER_MUTEX>();
 
-        mutex_lock(l_mutex);
-        need_unlock = true;
+        // skip the mutex lock if we're already inside a previous operation
+        if( !iv_ffdcCollection )
+        {
+            mutex_lock(l_mutex);
+            need_unlock = true;
+        }
 
         // write the OPB command register
         TRACUCOMP(g_trac_fsi, "FsiDD::write> ScomWRITE : opbaddr=%.16llX, data=%.16llX", opbaddr, fsicmd );
@@ -908,6 +916,7 @@ errlHndl_t FsiDD::handleOpbErrors(const FsiAddrInfo_t& i_addrInfo,
                 TRACFCOMP( g_trac_fsi, "MDTRB0(1DC) = %.8X", data );
             }
 
+            //MAGIC_INSTRUCTION(MAGIC_BREAK);
             iv_ffdcCollection = false;
         }
 
@@ -1059,7 +1068,7 @@ errlHndl_t FsiDD::genFullFsiAddr(FsiAddrInfo_t& io_addrInfo)
     //pull the FSI info out for this target
     FsiChipInfo_t fsi_info = getFsiInfo( io_addrInfo.fsiTarg );
 
-    TRACUCOMP( g_trac_fsi, "target=%llX : Link Id=%.8X", target_to_uint64(io_addrInfo.fsiTarg), i_fsiInfo.linkid.id );
+    TRACUCOMP( g_trac_fsi, "target=%llX : Link Id=%.8X", target_to_uint64(io_addrInfo.fsiTarg), fsi_info.linkid.id );
 
     //FSI master is the master proc, find the port
     if( fsi_info.master == iv_master )
diff --git a/src/usr/fsi/test/fsiddtest.H b/src/usr/fsi/test/fsiddtest.H
index 815fabfc1..12b6edb68 100644
--- a/src/usr/fsi/test/fsiddtest.H
+++ b/src/usr/fsi/test/fsiddtest.H
@@ -66,7 +66,6 @@ class FsiDDTest : public CxxTest::TestSuite
             TRACFCOMP(g_trac_fsi, "FsiDDTest::test_init> Error from device : RC=%X", l_err->reasonCode() );
             TS_FAIL( "FsiDDTest::test_init> ERROR : Unexpected error log from initMaster" );
             errlCommit(l_err,FSI_COMP_ID);
-            delete l_err;
         }
 
         TRACFCOMP( g_trac_fsi, "FsiDDTest::test_init> %d/%d fails", fails, total );
@@ -199,8 +198,7 @@ class FsiDDTest : public CxxTest::TestSuite
             //** Master Control Space
             // version number
             { PROC0, 0x003074, 0x91010800, false, true }, //CMFSI MVER
-            { PROC0, 0x003474, 0x91010800, false, true }, //MFSI MVER
-            //@fixme - should be 0x92010800 but Simics is wrong
+            { PROC0, 0x003474, 0x92010800, false, true }, //MFSI MVER
 
             //** Slave Regs (cheating)
             { PROC0, 0x080000, 0xC0010EA0, false, false }, //Config Table entry for slave0 off MFSI-0 
@@ -297,7 +295,6 @@ class FsiDDTest : public CxxTest::TestSuite
                 TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from read1" );
                 fails++;
                 errlCommit(l_err,FSI_COMP_ID);
-                delete l_err;
             }
 
             TRACDCOMP( g_trac_fsi, "READ Reg 0x%X = 0x%X", test_data[x].addr, read_data[x] );
@@ -325,7 +322,6 @@ class FsiDDTest : public CxxTest::TestSuite
                     TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from write1" );
                     fails++;
                     errlCommit(l_err,FSI_COMP_ID);
-                    delete l_err;
                 }
             }
         }
@@ -350,7 +346,6 @@ class FsiDDTest : public CxxTest::TestSuite
                 TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from read2" );
                 fails++;
                 errlCommit(l_err,FSI_COMP_ID);
-                delete l_err;
             }
         }
 
@@ -390,7 +385,6 @@ class FsiDDTest : public CxxTest::TestSuite
                     TS_FAIL( "FsiDDTest::test_readWrite> ERROR : Unexpected error log from write1" );
                     fails++;
                     errlCommit(l_err,FSI_COMP_ID);
-                    delete l_err;
                 }
             }
         }
@@ -443,7 +437,6 @@ class FsiDDTest : public CxxTest::TestSuite
             if( l_err )
             {
                 errlCommit(l_err,FSI_COMP_ID);
-                delete l_err;
             }
         }
 
diff --git a/src/usr/initservice/test/initservicetest.H b/src/usr/initservice/test/initservicetest.H
index bfb751954..d912a6e88 100644
--- a/src/usr/initservice/test/initservicetest.H
+++ b/src/usr/initservice/test/initservicetest.H
@@ -114,8 +114,7 @@ public:
         if ( l_errl  )
         {
             TS_TRACE( "SUCCESS: startTask returned an errorlog.\n");
-            //  clean up
-            errlCommit( l_errl, INITSVC_COMP_ID );
+            delete l_errl; //delete expected log
         }
         else
         {
@@ -176,7 +175,7 @@ public:
         if ( l_errl )
         {
             TS_TRACE( "SUCCESS: startTask returned an error log.\n");
-            errlCommit( l_errl, INITSVC_COMP_ID );
+            delete l_errl; //delete expected log
         }
         else
         {
diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H
index c0fab1492..48d2496f8 100644
--- a/src/usr/intr/test/intrtest.H
+++ b/src/usr/intr/test/intrtest.H
@@ -44,7 +44,6 @@ class IntrTest: public CxxTest::TestSuite
          */
         void test_verifyState( void )
         {
-
             // TODO Temporaritly DISABLE in VBU until P8 support is verfied
             if( TARGETING::is_vpo() )
             {
diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H
index c455f5be6..7d88b0da0 100644
--- a/src/usr/scom/test/scomtest.H
+++ b/src/usr/scom/test/scomtest.H
@@ -151,7 +151,6 @@ public:
               TS_FAIL( "ScomTest::test_FSISCOMreadWrite_proc> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
       }
 
@@ -177,7 +176,6 @@ public:
               TS_FAIL( "ScomTest::test_FSISCOMreadWrite_proc> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if(read_data[x] != test_data[x].data)
           {
@@ -273,6 +271,8 @@ public:
       // write all the test registers
       for( uint64_t x = 0; x < NUM_ADDRS; x++ )
       {
+          TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
+
           //only run if the target exists
           if(test_data[x].target == NULL)
           {
@@ -292,13 +292,14 @@ public:
               TS_FAIL( "ScomTest::test_FSISCOMreadWrite_centaur> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
       }
 
       // read all the test registers
       for( uint64_t x = 0; x < NUM_ADDRS; x++ )
       {
+          TRACFCOMP(g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> x=%d, addr=%.8X, target=%p", x,  test_data[x].addr, test_data[x].target );
+
           //only run if the target exists
           if(test_data[x].target == NULL)
           {
@@ -318,7 +319,6 @@ public:
               TS_FAIL( "ScomTest::test_FSISCOMreadWrite_centaur> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if(read_data[x] != test_data[x].data)
           {
@@ -438,7 +438,6 @@ public:
               TS_FAIL( "ScomTest::test_IndirectScom_proc> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
       }
 
@@ -470,7 +469,6 @@ public:
               TS_FAIL( "ScomTest::test_IndirectScomreadWrite_proc> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
           {
@@ -595,18 +593,18 @@ public:
                                DEVICE_SCOM_ADDRESS(test_data[x].addr) );
           if( l_err )
           {
-            // last 2 writes have expected failure conditions.
-            if ((x == NUM_ADDRS-1) || (x == NUM_ADDRS-2))
-	    {
-                TRACDCOMP( g_trac_scom, "ScomTest::test_translate_EX.. Expected Error log returned> " );
-            }
-            else
-            {
-              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_scom_EX> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
-              TS_FAIL( "ScomTest::test_translate_EX> ERROR : Unexpected error log from write1" );
-              fails++;
-              errlCommit(l_err,SCOM_COMP_ID);
-             }
+              // last 2 writes have expected failure conditions.
+              if ((x == NUM_ADDRS-1) || (x == NUM_ADDRS-2))
+              {
+                  TRACDCOMP( g_trac_scom, "ScomTest::test_translate_EX.. Expected Error log returned> " );
+              }
+              else
+              {
+                  TRACFCOMP(g_trac_scom, "ScomTest::test_translate_scom_EX> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+                  TS_FAIL( "ScomTest::test_translate_EX> ERROR : Unexpected error log from write1" );
+                  fails++;
+                  errlCommit(l_err,SCOM_COMP_ID);
+              }
 
               delete l_err;
           }
@@ -641,7 +639,6 @@ public:
               TS_FAIL( "ScomTest::test_translate_scom_EX> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if((read_data[x]) != (test_data[x].data))
           {
@@ -786,17 +783,17 @@ public:
                                DEVICE_SCOM_ADDRESS(test_data[x].addr) );
           if( l_err )
           {
-            if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
-            {
-                TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Error log returned> x = %d", x );
-            }
-            else
-            {
-              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
-              TS_FAIL( "ScomTest::test_Translate_SCOM_mcs> ERROR : Unexpected error log from write1" );
-              fails++;
-              errlCommit(l_err,SCOM_COMP_ID);
-             }
+              if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+              {
+                  TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Error log returned> x = %d", x );
+              }
+              else
+              {
+                  TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+                  TS_FAIL( "ScomTest::test_Translate_SCOM_mcs> ERROR : Unexpected error log from write1" );
+                  fails++;
+                  errlCommit(l_err,SCOM_COMP_ID);
+              }
 
               delete l_err;
           }
@@ -830,7 +827,6 @@ public:
               TS_FAIL( "ScomTest::test_TranslateScom_MCS> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if((read_data[x]) != (test_data[x].data))
           {
@@ -954,18 +950,18 @@ public:
                                DEVICE_SCOM_ADDRESS(test_data[x].addr) );
           if( l_err )
           {
-            // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected.
-            if (x == (NUM_ADDRS-1))
-            {
-                TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x );
-            }
-            else
-	    {
-              TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
-              TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" );
-              fails++;
-              errlCommit(l_err,SCOM_COMP_ID);
-             }
+              // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected.
+              if (x == (NUM_ADDRS-1))
+              {
+                  TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Errorlog Returned> x = %d", x );
+              }
+              else
+              {
+                  TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x,  test_data[x].addr, l_err->reasonCode() );
+                  TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" );
+                  fails++;
+                  errlCommit(l_err,SCOM_COMP_ID);
+              }
 
               delete l_err;
           }
@@ -1000,7 +996,6 @@ public:
               TS_FAIL( "ScomTest::test_TranslateScom_MBA_MBS> ERROR : Unexpected error log from write1" );
               fails++;
               errlCommit(l_err,SCOM_COMP_ID);
-              delete l_err;
           }
           else if((read_data[x]) != (test_data[x].data))
           {
diff --git a/src/usr/targeting/test/targetingtest.H b/src/usr/targeting/test/targetingtest.H
index bc5e0008c..93e0aca4a 100644
--- a/src/usr/targeting/test/targetingtest.H
+++ b/src/usr/targeting/test/targetingtest.H
@@ -1507,7 +1507,7 @@ class TargetingTestSuite: public CxxTest::TestSuite
         ErrlUserDetailsTarget(l_pTarget1).addToLog(l_err);
         ErrlUserDetailsTarget(l_pTarget2).addToLog(l_err);
 
-        errlCommit(l_err, TARG_COMP_ID);
+        errlCommit(l_err, CXXTEST_COMP_ID);
 
         TS_TRACE(EXIT_MRK "testErrlTargetFFDC");
     }
diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile
index ebcbec44c..800d928bd 100644
--- a/src/usr/targeting/xmltohb/makefile
+++ b/src/usr/targeting/xmltohb/makefile
@@ -36,7 +36,6 @@ XMLTOHB_SOURCE_TARGETS =    \
 
 XMLTOHB_SYSTEM_BINARIES = \
    vbu_targeting.bin \
-   simics_SALERNO_targeting.bin \
    simics_VENICE_targeting.bin \
    simics_MURANO_targeting.bin 
 
diff --git a/src/usr/targeting/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/xmltohb/simics_MURANO.system.xml
index 1b5edada4..56935a1cd 100644
--- a/src/usr/targeting/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/xmltohb/simics_MURANO.system.xml
@@ -111,7 +111,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -125,6 +125,14 @@
         <id>AFFINITY_PATH</id>
         <default>affinity:sys-0/node-0/proc-0</default>
     </attribute>
+    <attribute>
+        <id>FABRIC_NODE_ID</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>FABRIC_CHIP_ID</id>
+        <default>0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p0 EX units -->
@@ -539,7 +547,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -574,6 +582,14 @@
         <id>FSI_OPTION_FLAGS</id>
         <default>0</default>
     </attribute>
+    <attribute>
+        <id>FABRIC_NODE_ID</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>FABRIC_CHIP_ID</id>
+        <default>1</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p1 EX units -->
@@ -953,7 +969,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -988,6 +1004,14 @@
         <id>FSI_OPTION_FLAGS</id>
         <default>0</default>
     </attribute>
+    <attribute>
+        <id>FABRIC_NODE_ID</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>FABRIC_CHIP_ID</id>
+        <default>2</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p2 EX units -->
@@ -1368,7 +1392,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -1403,6 +1427,14 @@
         <id>FSI_OPTION_FLAGS</id>
         <default>0</default>
     </attribute>
+    <attribute>
+        <id>FABRIC_NODE_ID</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>FABRIC_CHIP_ID</id>
+        <default>3</default>
+    </attribute>
 </targetInstance>
 
 <!-- Murano n0p3 EX units -->
diff --git a/src/usr/targeting/xmltohb/simics_SALERNO.mrw.xml b/src/usr/targeting/xmltohb/simics_SALERNO.mrw.xml
deleted file mode 100644
index f000ee349..000000000
--- a/src/usr/targeting/xmltohb/simics_SALERNO.mrw.xml
+++ /dev/null
@@ -1,22 +0,0 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/targeting/xmltohb/simics_SALERNO.mrw.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
diff --git a/src/usr/targeting/xmltohb/simics_SALERNO.system.xml b/src/usr/targeting/xmltohb/simics_SALERNO.system.xml
deleted file mode 100644
index 5de483d2c..000000000
--- a/src/usr/targeting/xmltohb/simics_SALERNO.system.xml
+++ /dev/null
@@ -1,462 +0,0 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/targeting/xmltohb/simics_SALERNO.system.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2011
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
-
-<attributes>
-
-<!-- =====================================================================
-     HOST BOOT TARGET INSTANCES 
-     Contains target instance declarations for the Simics SALERNO 
-     configuration
-
-     * Config has 1-8 Salerno chips
-     ================================================================= -->
-
-<targetInstance>
-    <id>sys0</id>
-    <type>sys-sys-power8</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0</default>
-    </attribute> 
-    <attribute>
-        <id>PROC_EPS_TABLE_TYPE</id>
-        <default>EPS_TYPE_LE</default>
-    </attribute>
-    <attribute>
-        <id>PROC_FABRIC_PUMP_MODE</id>
-        <default>MODE1</default>
-    </attribute>
-    <attribute>
-        <id>PROC_X_BUS_WIDTH</id>
-        <default>W8BYTE</default>
-    </attribute>
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0</id>
-    <type>enc-node-power8</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0</default>
-    </attribute>  
-</targetInstance>
-
-
-
-<!-- Salerno n0p0 : start -->
-<targetInstance>
-    <id>sys0node0proc0</id>
-    <type>chip-processor-salerno</type>
-    <attribute><id>SCOM_SWITCHES</id>
-        <default>
-            <field><id>useFsiScom</id><value>0</value></field>
-            <field><id>useXscom</id><value>1</value></field>
-            <field><id>useInbandScom</id><value>0</value></field>
-            <field><id>reserved</id><value>0</value></field>
-        </default>
-    </attribute>
-    <attribute>
-        <id>XSCOM_CHIP_INFO</id>
-        <default>
-            <field><id>nodeId</id><value>0</value></field>
-            <field><id>chipId</id><value>0</value></field>
-        </default>
-    </attribute>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0</default>
-    </attribute>
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex0</id>
-    <type>unit-ex-salerno</type>
-        <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex1</id>
-    <type>unit-ex-salerno</type>
-        <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-1</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-1</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex2</id>
-    <type>unit-ex-salerno</type>
-        <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-2</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-2</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex3</id>
-    <type>unit-ex-salerno</type>
-        <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-3</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-3</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex4</id>
-    <type>unit-ex-salerno</type>
-        <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-4</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-4</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex5</id>
-    <type>unit-ex-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-5</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-5</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex0core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-0/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-0/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex1core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-1/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-1/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex2core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-2/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-2/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex3core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-3/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-3/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex4core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-4/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-4/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0ex5core0</id>
-    <type>unit-core-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/ex-5/core-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/ex-5/core-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0mcs0</id>
-    <type>unit-mcs-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/mcs-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0</default>
-    </attribute>
-    <attribute>
-        <id>CHIP_UNIT</id>
-        <default>0</default>
-    </attribute>
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0mcs0mba0</id>
-    <type>unit-mba-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/mcs-0/mba-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0/mba-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0mcs0mba1</id>
-    <type>unit-mba-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/mcs-0/mba-1</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0/mba-1</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0mcs0mba0port0</id>
-    <type>unit-memport-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/mcs-0/mba-0/mem_port-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0/mba-0/mem_port-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0mcs0mba1port0</id>
-    <type>unit-memport-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/mcs-0/mba-1/mem_port-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0/mba-1/mem_port-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0pervasive0</id>
-    <type>unit-pervasive-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/pervasive-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/pervasive-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0powerbus0</id>
-    <type>unit-powerbus-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/powerbus-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/powerbus-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0pci0</id>
-    <type>unit-pci-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/pci-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/pci-0</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0pci1</id>
-    <type>unit-pci-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/pci-1</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/pci-1</default>
-    </attribute>  
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0pci2</id>
-    <type>unit-pci-salerno</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-0/pci-2</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/pci-2</default>
-    </attribute>  
-</targetInstance>
-<!-- Salerno n0p0 : finish -->
-
-
-
-<!-- Temporary target used for FSI wrap-back testing -->
-<targetInstance>
-    <id>sys0node0proc0wrap</id>
-    <type>chip-processor-salerno</type>
-    <attribute><id>SCOM_SWITCHES</id>
-        <default>
-            <field><id>useFsiScom</id><value>1</value></field>
-            <field><id>useXscom</id><value>0</value></field>
-            <field><id>useInbandScom</id><value>0</value></field>
-            <field><id>reserved</id><value>0</value></field>
-        </default>
-    </attribute>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/proc-9</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-9</default>
-    </attribute>  
-
-    <!-- FSI is connected via wrapback to itself over MFSI-0 -->
-    <attribute>
-        <id>FSI_MASTER_CHIP</id>
-        <default>physical:sys-0/node-0/proc-0</default>
-    </attribute>
-    <attribute>
-        <id>FSI_MASTER_TYPE</id>
-        <default>MFSI</default>
-    </attribute>
-    <attribute>
-        <id>FSI_MASTER_PORT</id>
-        <default>0</default>
-    </attribute>
-    <attribute>
-        <id>FSI_SLAVE_CASCADE</id>
-        <default>0</default>
-    </attribute>
-    <attribute>
-        <id>FSI_OPTION_FLAGS</id>
-        <default>0</default>
-    </attribute>
-</targetInstance>
-
-<targetInstance>
-    <id>sys0node0proc0dimm0</id>
-    <type>lcard-dimm</type>
-    <attribute>
-        <id>PHYS_PATH</id>
-        <default>physical:sys-0/node-0/dimm-0</default>
-    </attribute>
-    <attribute>
-        <id>AFFINITY_PATH</id>
-        <default>affinity:sys-0/node-0/proc-0/mcs-0/mbs-0/mba-0/mem_port-0/dimm-0</default>
-    </attribute>
-    <attribute>
-        <id>EEPROM_ADDR_INFO0</id>
-        <default>
-            <field><id>i2cMasterPath</id><value>physical:sys-0/node-0/proc-0</value></field>
-            <field><id>port</id><value>0</value></field>
-            <field><id>devAddr</id><value>0x50</value></field>
-            <field><id>engine</id><value>0</value></field>
-        </default>
-    </attribute>
-</targetInstance>
-
-</attributes>
diff --git a/src/usr/targeting/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/xmltohb/simics_VENICE.system.xml
index 9b3573cb1..12306583b 100644
--- a/src/usr/targeting/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/xmltohb/simics_VENICE.system.xml
@@ -110,7 +110,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -518,7 +518,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -947,7 +947,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -1377,7 +1377,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -1806,7 +1806,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -2235,7 +2235,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -2664,7 +2664,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -3093,7 +3093,7 @@
         </default>
     </attribute>
     <attribute>
-        <id>XSCOM_CHIP_INFO</id>
+        <id>XSCOM_CHIP_INFO</id><!-- @fixme: Story 35529 -->
         <default>
             <field><id>nodeId</id><value>0</value></field>
             <field><id>chipId</id><value>0</value></field>
@@ -8962,7 +8962,10 @@
 
 <!-- Centaur n0p63 : end -->
 
-<!-- @fixme : Temporary target used for FSI wrap-back testing -->
+<!-- Remove this until Simics model works again : 
+     @fixme with Task 39187
+
+Target used for FSI wrap-back testing
 <targetInstance>
     <id>sys0node0proc0wrap</id>
     <type>chip-processor-venice</type>
@@ -8983,7 +8986,7 @@
         <default>affinity:sys-0/node-0/proc-9</default>
     </attribute>
 
-    <!-- FSI is connected via wrapback to itself over MFSI-0 -->
+    FSI is connected via wrapback to itself over MFSI-0
     <attribute>
         <id>FSI_MASTER_CHIP</id>
         <default>physical:sys-0/node-0/proc-0</default>
@@ -9006,6 +9009,8 @@
     </attribute>
 </targetInstance>
 
+-->
+
 
 <!-- DIMMS
      id/physical is sys-0/node-0/dimm-[d]