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authorMarty Gloff <mgloff@us.ibm.com>2015-11-23 11:23:56 -0600
committerPatrick Williams <iawillia@us.ibm.com>2015-12-11 15:30:28 -0600
commit23b7fc8c77faa26a540c889900482bfc18b3ca52 (patch)
tree4b26d34d3011a65542ecac88a25b0316da56af35 /src
parentd0edb877c861c146e97745604a2d1933a4844130 (diff)
downloadtalos-hostboot-23b7fc8c77faa26a540c889900482bfc18b3ca52.tar.gz
talos-hostboot-23b7fc8c77faa26a540c889900482bfc18b3ca52.zip
P9 - Fake trigger for memory expansion
Read attributes for the memory base and size Invoke Simics action to create mainstore Invoke Simics action to exit cache contained mode and unmap L3 cache Change-Id: Ic8aeb7e768b4e4a0b487c1a22b069c91dfe3d674 RTC:132577 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22277 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Christian Geddes <crgeddes@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/usr/isteps/istep14/call_proc_exit_cache_contained.C68
1 files changed, 66 insertions, 2 deletions
diff --git a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C
index 0703ae0bf..7478f3b65 100644
--- a/src/usr/isteps/istep14/call_proc_exit_cache_contained.C
+++ b/src/usr/isteps/istep14/call_proc_exit_cache_contained.C
@@ -39,6 +39,12 @@
#include <intr/interrupt.H>
#include <isteps/hwpf_reasoncodes.H>
+// @TODO RTC:134082 remove below block
+// Add P9 - Fake trigger for memory expansion
+#include <kernel/console.H> // printk status
+#include <devicefw/userif.H>
+// @TODO RTC:134082 remove above block
+
using namespace ISTEP;
using namespace ISTEP_ERROR;
using namespace ERRORLOG;
@@ -69,7 +75,6 @@ void* call_proc_exit_cache_contained (void *io_pArgs)
assert( l_sys != NULL );
//@TODO RTC:133831 Commenting out due to missing attributes
-#if 0
errlHndl_t l_errl = NULL;
uint8_t l_mpipl = l_sys->getAttr<ATTR_IS_MPIPL_HB>();
ATTR_PAYLOAD_BASE_type payloadBase = 0;
@@ -223,7 +228,67 @@ void* call_proc_exit_cache_contained (void *io_pArgs)
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"SUCCESS : call_proc_exit_cache_contained" );
+ // @TODO RTC:134082 remove below block
+#if 1
+ // Add P9 - Fake trigger for memory expansion
+ TARGETING::Target* l_masterProc = NULL;
+ TARGETING::targetService()
+ .masterProcChipTargetHandle( l_masterProc );
+
+ uint64_t l_top_addr = get_top_mem_addr();
+ uint64_t l_bottom_addr = get_bottom_mem_addr();
+ uint64_t l_mem_size = l_top_addr - l_bottom_addr;
+
+ // aggregate scom data to write
+ uint64_t l_data[] = {l_bottom_addr, // Memory Base Address
+ l_mem_size, // Memory Size in bytes
+ 1}; // Memory Valid
+ uint64_t l_addr = 0x05000000;
+ size_t scom_size = sizeof(uint64_t);
+
+ for(uint8_t i = 0;
+ i < sizeof(l_data) / sizeof(uint64_t);
+ i++)
+ {
+ l_errl = deviceWrite( l_masterProc,
+ &(l_data[i]),
+ scom_size,
+ DEVICE_SCOM_ADDRESS(l_addr+i) );
+ if( l_errl ) { break; }
+ }
+
+ if ( l_errl )
+ {
+ // Create IStep error log and cross reference to error that
+ // occurred
+ l_stepError.addErrorDetails( l_errl );
+
+ // Commit Error
+ errlCommit( l_errl, HWPF_COMP_ID );
+ }
+
+ printk("Fake Memory now set up.\n");
+ // exit cache contained mode
+ l_errl = deviceWrite( l_masterProc,
+ &(l_data[2]),
+ scom_size,
+ DEVICE_SCOM_ADDRESS(l_addr+3) );
+
+ if ( l_errl )
+ {
+ // Create IStep error log and cross reference to error that
+ // occurred
+ l_stepError.addErrorDetails( l_errl );
+
+ // Commit Error
+ errlCommit( l_errl, HWPF_COMP_ID );
+ }
+
+ printk("Cache contained mode has been exited.\n");
+ // End of Add P9 - Fake trigger for memory expansion
+#endif
+ // @TODO RTC:134082 remove above block
// Call the function to extend VMM to 32MEG
int rc = mm_extend();
@@ -272,7 +337,6 @@ void* call_proc_exit_cache_contained (void *io_pArgs)
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_proc_exit_cache_contained exit" );
-#endif
// @@@@@ END CUSTOM BLOCK: @@@@@
// end task, returning any errorlogs to IStepDisp
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