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authorThi Tran <thi@us.ibm.com>2014-02-12 14:09:28 -0600
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-02-13 14:29:07 -0600
commit22d0abdb176f9b26f1b52339a44107875fe37f22 (patch)
tree58cbfeff36b0571a1099c86c4b6f809380270256 /src
parenteb21a7e10fa560dabbe2fd4d02a168371479e422 (diff)
downloadtalos-hostboot-22d0abdb176f9b26f1b52339a44107875fe37f22.tar.gz
talos-hostboot-22d0abdb176f9b26f1b52339a44107875fe37f22.zip
INITPROC: Hostboot SW245693 HWPs week of 02/04/2014
Change-Id: If201831cf2aa7a28d675646af8ad4670a88d2e75 CQ:SW245693 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/8800 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/usr/hwpf/hwp/centaur_ec_attributes.xml38
-rwxr-xr-xsrc/usr/hwpf/hwp/include/common_scom_addresses.H11
-rwxr-xr-xsrc/usr/hwpf/hwp/include/p8_scom_addresses.H24
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile6
-rw-r--r--src/usr/hwpf/hwp/p8_slw_registers.xml27
5 files changed, 97 insertions, 9 deletions
diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
index 56de022c3..7d6d2f5e1 100644
--- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml
+++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
@@ -22,7 +22,24 @@
<!-- IBM_PROLOG_END_TAG -->
<attributes>
<!-- ********************************************************************* -->
- <!-- $Id: centaur_ec_attributes.xml,v 1.17 2014/01/21 15:19:37 yctschan Exp $ -->
+ <!-- $Id: centaur_ec_attributes.xml,v 1.20 2014/01/31 15:09:24 yctschan Exp $ -->
+ <attribute>
+ <id>ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685</id>
+ <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+ <description>
+ Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it allow RCE to be reported even if we also have chip marks or symbol marks in place. MBSTR(60)=1 and MBSECC(16)=1, DD2 is set.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_CENTAUR</name>
+ <ec>
+ <value>0x20</value>
+ <test>GREATER_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+
<attribute>
<id>ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ</id>
<targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -323,4 +340,23 @@ The getMBvpdSlopeInterceptData Attribute Accessor, if it does not find a matchin
</chipEcFeature>
</attribute>
+ <attribute>
+ <id>ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES</id>
+ <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+ <description>
+ Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, mss_unmask_errors.C will use the DD2 FIR bit definitions when setting FIR action regs and masks.
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_CENTAUR</name>
+ <ec>
+ <value>0x20</value>
+ <test>GREATER_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+
+
+
</attributes>
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 6f36a055c..60f7936f9 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2012,2013 */
+/* COPYRIGHT International Business Machines Corp. 2012,2014 */
/* */
/* p1 */
/* */
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: common_scom_addresses.H,v 1.48 2013/11/04 14:31:08 kahnevan Exp $
+// $Id: common_scom_addresses.H,v 1.49 2014/01/30 16:19:26 mfred Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
@@ -373,6 +373,8 @@ CONST_UINT64_T( TP_CLK_REGION_0x01030006 , ULL(0x01030006) );
CONST_UINT64_T( TP_CLK_SCANSEL_0x01030007 , ULL(0x01030007) );
CONST_UINT64_T( TP_CLK_STATUS_0x01030008 , ULL(0x01030008) );
+CONST_UINT64_T( TP_CC_ERROR_STATUS_0x01030009 , ULL(0x01030009) );
+CONST_UINT64_T( TP_CC_PROTECT_MODE_0x010303FE , ULL(0x010303FE) );
//------------------------------------------------------------------------------
// TP FIR
@@ -456,6 +458,8 @@ CONST_UINT64_T( NEST_OPCG_CNTL3_0x02030005 , ULL(0x02030005) );
CONST_UINT64_T( NEST_CLK_REGION_0x02030006 , ULL(0x02030006) );
CONST_UINT64_T( NEST_CLK_SCANSEL_0x02030007 , ULL(0x02030007) );
CONST_UINT64_T( NEST_CLK_STATUS_0x02030008 , ULL(0x02030008) );
+CONST_UINT64_T( NEST_CC_ERROR_STATUS_0x02030009 , ULL(0x02030009) );
+CONST_UINT64_T( NEST_CC_PROTECT_MODE_0x020303FE , ULL(0x020303FE) );
//------------------------------------------------------------------------------
// NEST FIR
@@ -638,6 +642,9 @@ This section is automatically updated by CVS when you check in this file.
Be sure to create CVS comments when you commit so that they can be included here.
$Log: common_scom_addresses.H,v $
+Revision 1.49 2014/01/30 16:19:26 mfred
+Add some clock control regs for FFDC.
+
Revision 1.48 2013/11/04 14:31:08 kahnevan
Added missing addresses used by proc_perv_registers.xml
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index c529b6d1f..6e4668366 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: p8_scom_addresses.H,v 1.171 2014/01/20 22:17:37 jdavidso Exp $
+// $Id: p8_scom_addresses.H,v 1.173 2014/02/10 14:36:30 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
@@ -1116,9 +1116,17 @@ CONST_UINT64_T( NX_AS_MMIO_BAR_0x0201309E , ULL(0x0201309E) );
CONST_UINT64_T( NX_CAPP_FIR_0x02013000 , ULL(0x02013000) );
CONST_UINT64_T( NX_CAPP_FIR_AND_0x02013001 , ULL(0x02013001) );
+CONST_UINT64_T( NX_CAPP_DEBUG_CTRL_0x02013011 , ULL(0x02013011) );
+
+CONST_UINT64_T( NX_PB_DEBUG_0x02013090 , ULL(0x02013090) );
+CONST_UINT64_T( NX_DEBUG_SNAPSHOT0_0x020130A4 , ULL(0x020130A4) );
+CONST_UINT64_T( NX_DEBUG_SNAPSHOT1_0x020130A5 , ULL(0x020130A5) );
+
CONST_UINT64_T( NX_DMA_ENG_FIR_0x02013100 , ULL(0x02013100) );
CONST_UINT64_T( NX_DMA_ENG_FIR_AND_0x02013101 , ULL(0x02013101) );
+CONST_UINT64_T( NX_DEBUGMUX_CTRL_0x0201310A , ULL(0x0201310A) );
+
CONST_UINT64_T( NX_CQ_FIR_0x02013080 , ULL(0x02013080) );
CONST_UINT64_T( NX_CQ_FIR_AND_0x02013081 , ULL(0x02013081) );
@@ -1214,6 +1222,8 @@ CONST_UINT64_T( X_OPCG_CNTL3_0x04030005 , ULL(0x04030005) );
CONST_UINT64_T( X_CLK_REGION_0x04030006 , ULL(0x04030006) );
CONST_UINT64_T( X_CLK_SCANSEL_0x04030007 , ULL(0x04030007) );
CONST_UINT64_T( X_CLK_STATUS_0x04030008 , ULL(0x04030008) );
+CONST_UINT64_T( X_CC_ERROR_STATUS_0x04030009 , ULL(0x04030009) );
+CONST_UINT64_T( X_CC_PROTECT_MODE_0x040303FE , ULL(0x040303FE) );
//------------------------------------------------------------------------------
// X-BUS FIR
@@ -1304,6 +1314,8 @@ CONST_UINT64_T( A_OPCG_CNTL3_0x08030005 , ULL(0x08030005) );
CONST_UINT64_T( A_CLK_REGION_0x08030006 , ULL(0x08030006) );
CONST_UINT64_T( A_CLK_SCANSEL_0x08030007 , ULL(0x08030007) );
CONST_UINT64_T( A_CLK_STATUS_0x08030008 , ULL(0x08030008) );
+CONST_UINT64_T( A_CC_ERROR_STATUS_0x08030009 , ULL(0x08030009) );
+CONST_UINT64_T( A_CC_PROTECT_MODE_0x080303FE , ULL(0x080303FE) );
//------------------------------------------------------------------------------
// A-BUS FIR
@@ -1448,6 +1460,8 @@ CONST_UINT64_T( PCIE_OPCG_CNTL3_0x09030005 , ULL(0x09030005) );
CONST_UINT64_T( PCIE_CLK_REGION_0x09030006 , ULL(0x09030006) );
CONST_UINT64_T( PCIE_CLK_SCANSEL_0x09030007 , ULL(0x09030007) );
CONST_UINT64_T( PCIE_CLK_STATUS_0x09030008 , ULL(0x09030008) );
+CONST_UINT64_T( PCIE_CC_ERROR_STATUS_0x09030009 , ULL(0x09030009) );
+CONST_UINT64_T( PCIE_CC_PROTECT_MODE_0x090303FE , ULL(0x090303FE) );
//------------------------------------------------------------------------------
// PCIE-BUS FIR
@@ -1762,6 +1776,8 @@ CONST_UINT64_T( EX_OPCG_CNTL3_0x10030005 , ULL(0x10030005) );
CONST_UINT64_T( EX_CLK_REGION_0x10030006 , ULL(0x10030006) );
CONST_UINT64_T( EX_CLK_SCANSEL_0x10030007 , ULL(0x10030007) );
CONST_UINT64_T( EX_CLK_STATUS_0x10030008 , ULL(0x10030008) );
+CONST_UINT64_T( EX_CC_ERROR_STATUS_0x10030009 , ULL(0x10030009) );
+CONST_UINT64_T( EX_CC_PROTECT_MODE_0x100303FE , ULL(0x100303FE) );
//------------------------------------------------------------------------------
// EX FIR
@@ -2040,6 +2056,12 @@ This section is automatically updated by CVS when you check in this file.
Be sure to create CVS comments when you commit so that they can be included here.
$Log: p8_scom_addresses.H,v $
+Revision 1.173 2014/02/10 14:36:30 jmcgill
+add NX addresses for debug bus/NXD trace collection
+
+Revision 1.172 2014/01/30 16:19:24 mfred
+Add some clock control regs for FFDC.
+
Revision 1.171 2014/01/20 22:17:37 jdavidso
Added additional pmc registers for SW239845.
diff --git a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
index d816f15d8..d64f72599 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.as.scom.initfile,v 1.5 2013/03/19 14:16:52 mikos Exp $
+#-- $Id: p8.as.scom.initfile,v 1.6 2014/01/29 23:19:32 kscarp Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2013
@@ -121,10 +121,10 @@ scom 0x020130C6 {
#--- Action 1
scom 0x020130C7 {
scom_data ;
- 0x0040000010800000 ;
+ 0x0000000000000000 ;
}
#--- Mask
scom 0x020130C3 {
scom_data ;
- 0x60BD600DEF600000 ;
+ 0xFFFFFFFFFFE00000 ;
}
diff --git a/src/usr/hwpf/hwp/p8_slw_registers.xml b/src/usr/hwpf/hwp/p8_slw_registers.xml
index effd87ead..7cdd21639 100644
--- a/src/usr/hwpf/hwp/p8_slw_registers.xml
+++ b/src/usr/hwpf/hwp/p8_slw_registers.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
-<!-- COPYRIGHT International Business Machines Corp. 2013 -->
+<!-- COPYRIGHT International Business Machines Corp. 2013,2014 -->
<!-- -->
<!-- p1 -->
<!-- -->
@@ -20,7 +20,7 @@
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
-<!-- $Id: p8_slw_registers.xml,v 1.3 2013/12/05 21:22:27 stillgs Exp $ -->
+<!-- $Id: p8_slw_registers.xml,v 1.5 2014/02/10 04:46:50 stillgs Exp $ -->
<!-- Definition of SLW registers to collect on some errors -->
<hwpErrors>
<registerFfdc>
@@ -76,4 +76,27 @@
<scomRegister>PBA_CONFIG_0x0201084B</scomRegister>
<scomRegister>PBA_SLVCTL2_0x00064006</scomRegister>
</registerFfdc>
+ <registerFfdc>
+ <id>REG_FFDC_PROC_SLW_OHA_REGISTERS</id>
+ <scomRegister>EX_OHA_RO_STATUS_REG_0x1002000B</scomRegister>
+ <scomRegister>EX_OHA_MODE_REG_RWx1002000D</scomRegister>
+ <scomRegister>EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011</scomRegister>
+ <scomRegister>EX_OHA_RO_STATUS_REG_0x1002000B</scomRegister>
+ <scomRegister>EX_OHA_AISS_IO_REG_0x10020014</scomRegister>
+ </registerFfdc>
+ <registerFfdc>
+ <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id>
+ <scomRegister>EX_GP3_0x100F0012</scomRegister>
+ <scomRegister>EX_PMGP0_0x100F0100</scomRegister>
+ <scomRegister>EX_PMGP1_0x100F0103</scomRegister>
+ <scomRegister>EX_PFET_CTL_REG_0x100F0106</scomRegister>
+ <scomRegister>EX_PFET_STAT_REG_0x100F0107</scomRegister>
+ <scomRegister>EX_PFET_CTL_REG_0x100F010E</scomRegister>
+ <scomRegister>EX_PMSTATEHISTPERF_REG_0x100F0113</scomRegister>
+ <scomRegister>EX_PCBS_FSM_MONITOR1_REG_0x100F0170</scomRegister>
+ <scomRegister>EX_PCBS_FSM_MONITOR2_REG_0x100F0171</scomRegister>
+ <scomRegister>EX_PMErr_REG_0x100F0109</scomRegister>
+ <scomRegister>EX_PCBS_DPLL_STATUS_REG_100F0161</scomRegister>
+ <scomRegister>EX_DPLL_CPM_PARM_REG_0x100F0152</scomRegister>
+ </registerFfdc>
</hwpErrors>
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