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authorChristian Geddes <crgeddes@us.ibm.com>2017-09-27 17:26:46 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-10-09 17:10:47 -0400
commit1debaa8fe82fc20a46a3abce41b65a6f1e605486 (patch)
treedb7d8be7d6ba432fa1bc96c5ebf0767622bcc651 /src
parentfb91c96d1158b58a698615e2bdef1217e39ea0e0 (diff)
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Clear INT_PC registers on MPIPL when initializing intrrp
During MPIPL the SBE issues a sync_reset command to the XIVE logic. There is an issue in the HW logic that is leaving some of the INT_PC registers filled in. We need to make sure those are cleared before reinitializing the interrupt resource provide for MPIPL Change-Id: I7a8134d067e3758095e910d739702636da0e8a79 RTC: 172905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46836 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/usr/intr/intrrp.C39
-rw-r--r--src/usr/intr/intrrp.H9
2 files changed, 42 insertions, 6 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C
index cc9a18ba1..6e8d00f55 100644
--- a/src/usr/intr/intrrp.C
+++ b/src/usr/intr/intrrp.C
@@ -127,6 +127,10 @@ errlHndl_t IntrRp::resetIntpForMpipl()
break;
}
+ // Clear out the PC registers that did not get properly cleared during
+ // the SBE steps of MPIPL
+ clearIntPcRegs();
+
//Reset PSIHB Interrupt Space
TRACFCOMP(g_trac_intr, "Reset PSIHB Interrupt Space");
@@ -392,6 +396,35 @@ void IntrRp::enableLsiInterrupts()
TRACDCOMP(g_trac_intr, "IntrRp:: enableLsiInterrupts() exit");
}
+/**
+ * Clear INT_PC registers that didn't get cleared by the HW reset
+ * during the SBE steps of the MPIPL
+ */
+void IntrRp::clearIntPcRegs()
+{
+ TRACDCOMP(g_trac_intr, "IntrRp:: clearIntPcRegs() enter");
+ //The XIVE HW is expecting these MMIO accesses to come from the
+ // core/thread they were setup (master core, thread 0)
+ // These functions will ensure this code executes there
+ task_affinity_pin();
+ task_affinity_migrate_to_master();
+
+ uint64_t * l_vsdTableAddr =
+ iv_masterHdlr->xiveIcBarAddr + XIVE_IC_PC_VSD_TABLE_ADDR_OFFSET;
+ *l_vsdTableAddr = 0x0000000000000000;
+
+ uint64_t * l_vsdTableData =
+ iv_masterHdlr->xiveIcBarAddr + XIVE_IC_PC_VSD_TABLE_DATA_OFFSET;
+ *l_vsdTableData = 0x0000000000000000;
+
+ uint64_t * l_blockModeAddr =
+ iv_masterHdlr->xiveIcBarAddr + XIVE_IC_PC_VPD_BLOCK_MODE_OFFSET;
+ *l_blockModeAddr = 0x0000000000000000;
+
+ //MMIO Complete, rest of code can run on any thread
+ task_affinity_unpin();
+ TRACDCOMP(g_trac_intr, "IntrRp:: clearIntPcRegs() exit");
+}
void IntrRp::acknowledgeInterrupt()
@@ -1853,7 +1886,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err; //errl comp already shutdown. Log error and continue
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error masking all interrupt sources.");
}
@@ -1874,7 +1906,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err;
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error re-enabling VPC Pull Err");
}
//Disable common interrupt BARs
@@ -1883,7 +1914,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err; //errl cmp already shutdown. Log error + continue
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error disabling Common Interrupt BARs");
}
}
@@ -1902,7 +1932,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err;
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error re-enabling VPC Pull Err");
}
@@ -1911,7 +1940,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err; //errl cmp already shutdown. Log error + continue
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error disabling Common"
" Interrupt BARs for master proc");
}
@@ -1922,7 +1950,6 @@ void IntrRp::shutDown(uint64_t i_status)
if (l_err)
{
delete l_err; //errl cmp already shutdown. Log error + continue
- l_err = nullptr;
TRACFCOMP(g_trac_intr, "IntrRp::shutDown() Error disabling Master Interrupt BARs");
}
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index ecebf7e67..f211e3347 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -200,6 +200,9 @@ namespace INTR
XIVE_IC_LSI_EOI_OFFSET =
XIVE_IC_ESB_EOI_OFFSET/sizeof(uint64_t),
XIVE_IC_VPC_PULL_ERR = 0x0000000200000000,
+ XIVE_IC_PC_VSD_TABLE_ADDR_OFFSET = 0x488 / sizeof(uint64_t),
+ XIVE_IC_PC_VSD_TABLE_DATA_OFFSET = 0x490 / sizeof(uint64_t),
+ XIVE_IC_PC_VPD_BLOCK_MODE_OFFSET = 0x4A8 / sizeof(uint64_t),
//XIVE IVPE (Presentation Engine) Constants
XIVE_IVPE_TM_BAR1_SCOM_ADDR = 0x05013012,
@@ -402,6 +405,12 @@ namespace INTR
void enableLsiInterrupts();
/**
+ * Clear INT_PC registers that didn't get cleared by the HW reset
+ * during the SBE steps of the MPIPL
+ */
+ void clearIntPcRegs();
+
+ /**
* Clear bit 3 of the PSIHB Control/Status register to disable
PSI interrupts from interrupting the CEC.
*/
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