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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-03-21 17:20:59 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-02-01 09:54:55 -0500 |
| commit | 1d70cbbeba50649f8a6b29d0902a1702885959b2 (patch) | |
| tree | f4ae81d2ea7a3205b8fd45d3cef77866f92db7e3 /src | |
| parent | d226d009365f13a32425af12c62eaf4940b8c4bb (diff) | |
| download | talos-hostboot-1d70cbbeba50649f8a6b29d0902a1702885959b2.tar.gz talos-hostboot-1d70cbbeba50649f8a6b29d0902a1702885959b2.zip | |
cresp address error handling updates
This commit sets up the FBC trace arrays to stop on a combined response
address error, for MPIPL FFDC collection.
It also adjusts the FIR configuration for several units, to trigger
a system checkstop (based on their own LFIR) if they master a command
which recieves a combined response address error cresp, and we do
not support MPIPL from that condition. Unlike in past projects, the
FBC level cresp address error FIR bit cannot be set to checkstop (in order
to support MPIPL scenarios where the unacknowledged access eminates from
the core)
FIR action bits modified:
PSIHB bits 15:20
PBA bit 1
Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f
CQ: SW411054
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52635
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C index 1128dec32..71360bf4e 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_psi_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,7 @@ constexpr uint64_t literal_0xFE00000000000000 = 0xFE00000000000000; constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000; constexpr uint64_t literal_0b00111111000000100000011011111 = 0b00111111000000100000011011111; constexpr uint64_t literal_0b00000000000000000000000000000 = 0b00000000000000000000000000000; -constexpr uint64_t literal_0b11000000001010011111100100000 = 0b11000000001010011111100100000; +constexpr uint64_t literal_0b11000000001010000000000100000 = 0b11000000001010000000000100000; constexpr uint64_t literal_0x000 = 0x000; constexpr uint64_t literal_0b00000 = 0b00000; @@ -78,7 +78,7 @@ fapi2::ReturnCode p9_psi_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { FAPI_TRY(fapi2::getScom( TGT0, 0x5012907ull, l_scom_buffer )); - l_scom_buffer.insert<0, 29, 35, uint64_t>(literal_0b11000000001010011111100100000 ); + l_scom_buffer.insert<0, 29, 35, uint64_t>(literal_0b11000000001010000000000100000 ); FAPI_TRY(fapi2::putScom(TGT0, 0x5012907ull, l_scom_buffer)); } { |
