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| author | Luke Mulkey <lwmulkey@us.ibm.com> | 2017-08-17 09:51:18 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2017-08-24 12:32:47 -0400 |
| commit | 1bbe8d05010f4837119b0e80c2b474304b375031 (patch) | |
| tree | 002957e76af80c0e3ee7d3697e5db9c7195d9cd9 /src | |
| parent | 07440fe370a0d58a806375ff0f78995f1c8828a2 (diff) | |
| download | talos-hostboot-1bbe8d05010f4837119b0e80c2b474304b375031.tar.gz talos-hostboot-1bbe8d05010f4837119b0e80c2b474304b375031.zip | |
Cumulus DIMM SPD accessors
Change-Id: Ibbb4d4757ad863d27ce544cdbbf1c7988d5fbd29
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44738
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44929
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
4 files changed, 803 insertions, 152 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C new file mode 100644 index 000000000..29acdb082 --- /dev/null +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C @@ -0,0 +1,463 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9s_mss_attr_cleanup.C +/// @brief Decode SPD and populate attrs +/// +// *HWP HWP Owner: Thomas Sand <trsand@us.ibm.com> +// *HWP HWP Backup: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +// std lib +#include <map> +#include <vector> + +#include <p9c_mss_attr_cleanup.H> + +#include <fapi2_spd_access.H> +#include <attribute_ids.H> + +#include <lib/shared/dimmConsts.H> + +using fapi2::TARGET_TYPE_DIMM; +using fapi2::FAPI2_RC_SUCCESS; + +enum factory_byte_offset +{ + REVISION = 1, ///< SPD Revision + DRAM_DEVICE_TYPE = 2, ///< SPD DRAM Interface Type + MODULE_TYPE = 3, ///< SPD DIMM Type + SDRAM_DENSITY = 4, ///< SPD SDRAM Density + SDRAM_ADDRESSING = 5, ///< SPD SDRAM Addressing + SDRAM_PACKING_TYPE = 6, ///< SPD SDRAM Addressing + SDRAM_OPTIONAL_FEATURES = 7,///< SPD SDRAM Optional Features + SDRAM_THERMAL_OPTIONS = 8, ///< SPD SDRAM Thermal and Refresh Options + SDRAM_OTHER_OPT_FEATURES = 9, ///< + SDRAM_SEC_PACKAGE_FEAT = 10, ///< + MODULE_NOMINAL_VOLTAGE = 11, /// + MODULE_ORGANIZATION = 12, ///< + MODULE_MEMORY_BUS_WIDTH = 13, + MODULE_THERMAL_SENSOR = 14, + + TIMEBASE = 17, + TCKMIN = 18, + TCKMAX_DDR4 = 19, + CAS_LATENCIES_SUPPORTED_BYTE1 = 20, + CAS_LATENCIES_SUPPORTED_BYTE2 = 21, + CAS_LATENCIES_SUPPORTED_BYTE3 = 23, + CAS_LATENCIES_SUPPORTED_BYTE4 = 23, + TAAMIN = 24, + TRCDMIN = 25, + TRPMIN = 26, + TRAS_TRCMIN_HIGH = 27, + TRASMIN_LOW = 28, + TRCMIN_LOW = 29, + TRFC1MIN_DDR4_LOW = 30, + TRFC1MIN_DDR4_HIGH = 31, + TRFC2MIN_DDR4_LOW = 32, + TRFC2MIN_DDR4_HIGH = 33, + TRFC4MIN_DDR4_LOW = 34, + TRFC4MIN_DDR4_HIGH = 35, + TFAWMIN_HIGH = 36, + TFAWMIN_LOW = 37, + TRRDSMIN_DDR4 = 38, + TRRDLMIN_DDR4 = 39, + TCCDLMIN_DDR4 = 40, + + FINE_OFFSET_TCCDLMIN_DDR4 = 117, + FINE_OFFSET_TRRDLMIN_DDR4 = 118, + FINE_OFFSET_TRRDSMIN_DDR4 = 119, + FINE_OFFSET_TRCMIN = 120, + FINE_OFFSET_TRPMIN = 121, + FINE_OFFSET_TRCDMIN = 122, + FINE_OFFSET_TAAMIN = 123, + FINE_OFFSET_TCKMAX_DDR4 = 124, + FINE_OFFSET_TCKMIN = 125, + CRC_BASE_CONFIG_DDR4_LOW = 126, + CRC_BASE_CONFIG_DDR4_HIGH = 127, + MODULE_SPECIFIC_SECTION = 128, + + ADDR_MAP_REG_TO_DRAM = 136, // and 137 + + MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE_LOW = 320, + MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE_HIGH = 321, + MODULE_ID_MODULE_MANUFACTURING_LOCATION = 322, + MODULE_ID_MODULE_MANUFACTURING_DATE_YEAR = 323, + MODULE_ID_MODULE_MANUFACTURING_DATE_WEEK = 324, + MODULE_ID_MODULE_SERIAL_NUMBER_BYTE1 = 325, + MODULE_ID_MODULE_SERIAL_NUMBER_BYTE2 = 326, + MODULE_ID_MODULE_SERIAL_NUMBER_BYTE3 = 327, + MODULE_ID_MODULE_SERIAL_NUMBER_BYTE4 = 328, + MODULE_PART_NUMBER = 329, // 329-348 + + MODULE_REVISION_CODE = 349, + DRAM_MANUFACTURER_JEDEC_ID_CODE_LSB = 350, + DRAM_MANUFACTURER_JEDEC_ID_CODE_MSB = 351, + DRAM_STEPPING_DDR4 = 352, + + DRAM_STEPPING_DDR4_LSB = 382, + DRAM_STEPPING_DDR4_MSB = 383 +}; + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +/// +/// @brief Programatic over-rides related to effective config, including data +/// from module VPD +/// @param[in] i_target, the controller (e.g., MCS) +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode +p9c_mss_attr_cleanup(const fapi2::Target<TARGET_TYPE_DIMM>& i_dimm) +{ + FAPI_INF("Start"); + + fapi2::ReturnCode l_rc; + size_t l_size = 0; + uint8_t l_spd_byte1 = 0; + uint8_t l_spd_byte2 = 0; + uint8_t l_spd_byte3 = 0; + uint8_t l_spd_byte4 = 0; + uint8_t l_work_byte = 0; + uint8_t l_work2_byte = 0; + uint32_t l_work_word = 0; + // DQ SPD Attribute + uint8_t l_dqData[DIMM_DQ_SPD_DATA_SIZE] {0}; + + // Get the size of the factory + FAPI_TRY( fapi2::getSPD(i_dimm, nullptr, l_size), + "Failed to retrieve SPD blob size"); + FAPI_INF("Get SPD Data size 0x%X ", l_size); + { + // "Container" for SPD data + std::vector<uint8_t> l_spd(l_size); + // Retrieve SPD data + FAPI_TRY( fapi2::getSPD(i_dimm, l_spd.data(), l_size), + "Failed to retrieve SPD data" ); + FAPI_INF("Get SPD Data byte 0 0x%X ", l_spd[0]); + + + // Brute force pull the data from the SPD and set it in + // REVISION = 1 + l_spd_byte1 = l_spd[REVISION]; + FAPI_INF("ATTR_CEN_SPD_REVISION 0x%X ", l_spd_byte1); + + // DRAM_DEVICE_TYPE + l_spd_byte1 = l_spd[DRAM_DEVICE_TYPE]; + + if(l_spd_byte1 == 0x0c) + { + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_DRAM_DEVICE_TYPE, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_DRAM_DEVICE_TYPE" ); + FAPI_INF("Set ATTR_CEN_SPD_DRAM_DEVICE_TYPE 0x%X ", l_spd_byte1); + + // MODULE_TYPE + l_spd_byte1 = l_spd[MODULE_TYPE]; + l_work_byte = l_spd_byte1 & 0xF; // bits 3-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_MODULE_TYPE, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_MODULE_TYPE" ); + FAPI_INF("Set ATTR_CEN_SPD_MODULE_TYPE 0x%X ", l_work_byte); + l_work_byte = (l_spd_byte1 & 0x80) >> 7; // bit 7 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_CUSTOM, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_CUSTOM" ); + FAPI_INF("Set ATTR_CEN_SPD_CUSTOM 0x%X ", l_work_byte); + + // SDRAM_DENSITY = 4 + l_spd_byte1 = l_spd[SDRAM_DENSITY]; + l_work_byte = l_spd_byte1 & 0xF; // bits 3-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_DENSITY, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_DENSITY" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_DENSITY 0x%X ", l_work_byte); + l_work_byte = (l_spd_byte1 & 0x30) >> 4; // bits 5-4 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_BANKS, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_BANKS" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_BANKS 0x%X ", l_work_byte); + + // SDRAM_ADDRESSING = 5 + l_spd_byte1 = l_spd[SDRAM_ADDRESSING]; + l_work_byte = l_spd_byte1 & 0x7; // bits 2-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_COLUMNS, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_COLUMNS" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_COLUMNS 0x%X ", l_work_byte); + l_work_byte = (l_spd_byte1 & 0x38) >> 3; // bits 5-3 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_ROWS, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_ROWS" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_ROWS 0x%X ", l_work_byte); + + // SDRAM_PACKING_TYPE = 6 + l_spd_byte1 = l_spd[SDRAM_PACKING_TYPE]; + l_work_byte = (l_spd_byte1 & 0x80) >> 7; // bit 7 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_DEVICE_TYPE, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_DEVICE_TYPE" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_DEVICE_TYPE 0x%X ", l_work_byte); + l_work_byte = (l_spd_byte1 & 0x70) >> 4; // bits 6-4 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_DIE_COUNT, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_DIE_COUNT" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_DIE_COUNT 0x%X ", l_work_byte); + l_work_byte = l_spd_byte1 & 0x03; // bits 1-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING 0x%X ", l_work_byte); + + // SDRAM_OPTIONAL_FEATURES = 7 + l_spd_byte1 = l_spd[SDRAM_OPTIONAL_FEATURES]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_OPTIONAL_FEATURES, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_SDRAM_OPTIONAL_FEATURES" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_OPTIONAL_FEATURES 0x%X ", l_spd_byte1); + + // SDRAM_THERMAL_OPTIONS = 8 + l_spd_byte1 = l_spd[SDRAM_THERMAL_OPTIONS]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS" ); + FAPI_INF("Set ATTR_CEN_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS 0x%X ", l_spd_byte1); + + // MODULE_NOMINAL_VOLTAGE = 11 + l_spd_byte1 = l_spd[MODULE_NOMINAL_VOLTAGE]; + l_work_byte = l_spd_byte1 & 0x3; // bits 1-0 + + if (1 == l_work_byte) + { + l_work2_byte = fapi2::ENUM_ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2V; + } + else if (2 == l_work_byte) + { + l_work2_byte = fapi2::ENUM_ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE_END1_2V; + } + else if (3 == l_work_byte) + { + l_work2_byte = fapi2::ENUM_ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE_END1_2V | + fapi2::ENUM_ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2V; + } + + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE, i_dimm, l_work2_byte), + "Failed to set ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE" ); + FAPI_INF("Set ATTR_CEN_SPD_MODULE_NOMINAL_VOLTAGE 0x%X ", l_work2_byte); + + // MODULE_ORGANIZATION = 12 + l_spd_byte1 = l_spd[MODULE_ORGANIZATION]; + l_work_byte = l_spd_byte1 & 0x7; // bits 2-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_DRAM_WIDTH, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_DRAM_WIDTH" ); + FAPI_INF("Set ATTR_CEN_SPD_DRAM_WIDTH 0x%X ", l_work_byte); + l_work_byte = (l_spd_byte1 & 0x38) >> 3; // bits 5-3 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_NUM_RANKS, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_NUM_RANKS" ); + FAPI_INF("Set ATTR_CEN_SPD_NUM_RANKS 0x%X ", l_work_byte); + + // MODULE_MEMORY_BUS_WIDTH = 13 + l_spd_byte1 = l_spd[MODULE_MEMORY_BUS_WIDTH]; + l_work_byte = l_spd_byte1 & 0x1F; // bits 4-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_MODULE_MEMORY_BUS_WIDTH, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_MODULE_MEMORY_BUS_WIDTH" ); + FAPI_INF("Set ATTR_CEN_SPD_MODULE_MEMORY_BUS_WIDTH 0x%X ", l_work_byte); + + // MODULE_THERMAL_SENSOR = 14 + l_spd_byte1 = l_spd[MODULE_THERMAL_SENSOR]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_MODULE_THERMAL_SENSOR, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_MODULE_THERMAL_SENSOR" ); + FAPI_INF("Set ATTR_CEN_SPD_MODULE_THERMAL_SENSOR 0x%X ", l_spd_byte1); + + // TIMEBASE = 17, + l_spd_byte1 = l_spd[MODULE_THERMAL_SENSOR]; + l_work_byte = (l_spd_byte1 & 0x0C) >> 2; // bits 3-2 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TIMEBASE_MTB_DDR4, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_TIMEBASE_MTB_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TIMEBASE_MTB_DDR4 0x%X ", l_work_byte); + l_work_byte = l_spd_byte1 & 0x3; // bits 1-0 + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TIMEBASE_FTB_DDR4, i_dimm, l_work_byte), + "Failed to set ATTR_CEN_SPD_TIMEBASE_FTB_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TIMEBASE_FTB_DDR4 0x%X ", l_work_byte); + + // TCKMIN = 18 + l_spd_byte1 = l_spd[TCKMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TCKMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TCKMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TCKMIN 0x%X ", l_spd_byte1); + + // TCKMAX_DDR4 = 19 + l_spd_byte1 = l_spd[TCKMAX_DDR4]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TCKMAX_DDR4, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TCKMAX_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TCKMAX_DDR4 0x%X ", l_spd_byte1); + + // CAS_LATENCIES_SUPPORTED = Bytes 20-23 + l_spd_byte1 = l_spd[CAS_LATENCIES_SUPPORTED_BYTE1]; + l_spd_byte2 = l_spd[CAS_LATENCIES_SUPPORTED_BYTE2]; + l_spd_byte3 = l_spd[CAS_LATENCIES_SUPPORTED_BYTE3]; + l_spd_byte4 = l_spd[CAS_LATENCIES_SUPPORTED_BYTE4]; + l_work_word = (l_spd_byte4 << 24) | (l_spd_byte3 << 16) | (l_spd_byte2 << 8) | l_spd_byte1; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_CAS_LATENCIES_SUPPORTED, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_CAS_LATENCIES_SUPPORTED" ); + FAPI_INF("Set ATTR_CEN_SPD_CAS_LATENCIES_SUPPORTED 0x%X ", l_work_word); + + // TAAMIN = 24 + l_spd_byte1 = l_spd[TAAMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TAAMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TAAMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TAAMIN 0x%X ", l_spd_byte1); + + // TRCDMIN = 25 + l_spd_byte1 = l_spd[TRCDMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRCDMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TRCDMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TRCDMIN 0x%X ", l_spd_byte1); + + // TRPMIN = 26 + l_spd_byte1 = l_spd[TRPMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRPMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TRPMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TRPMIN 0x%X ", l_spd_byte1); + + // TRAS_TRCMIN_HIGH = 27, + // TRASMIN_LOW = 28 + l_spd_byte1 = l_spd[TRAS_TRCMIN_HIGH]; + l_spd_byte2 = l_spd[TRASMIN_LOW]; + l_work_word = ((l_spd_byte1 & 0xF0) << 4) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRASMIN, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TRASMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TRASMIN 0x%X ", l_work_word); + + // TRCMIN_LOW = 29, + l_spd_byte2 = l_spd[TRCMIN_LOW]; + l_work_word = ((l_spd_byte1 & 0xF) << 8) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRCMIN, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TRCMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TRCMIN 0x%X ", l_work_word); + + // TRFC1MIN_DDR4_LOW = 30 + // TRFC1MIN_DDR4_HIGH = 31 + l_spd_byte1 = l_spd[TRFC1MIN_DDR4_HIGH]; + l_spd_byte2 = l_spd[TRFC1MIN_DDR4_LOW]; + l_work_word = (l_spd_byte1 << 8) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRFC1MIN_DDR4, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TRFC1MIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TRFC1MIN_DDR4 0x%X ", l_work_word); + + // TRFC2MIN_DDR4_LOW = 32, + // TRFC2MIN_DDR4_HIGH = 33, + l_spd_byte1 = l_spd[TRFC2MIN_DDR4_HIGH]; + l_spd_byte2 = l_spd[TRFC2MIN_DDR4_LOW]; + l_work_word = (l_spd_byte1 << 8) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRFC2MIN_DDR4, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TRFC2MIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TRFC2MIN_DDR4 0x%X ", l_work_word); + + // TRFC4MIN_DDR4_LOW = 34, + // TRFC4MIN_DDR4_HIGH = 35, + l_spd_byte1 = l_spd[TRFC4MIN_DDR4_HIGH]; + l_spd_byte2 = l_spd[TRFC4MIN_DDR4_LOW]; + l_work_word = (l_spd_byte1 << 8) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRFC4MIN_DDR4, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TRFC4MIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TRFC4MIN_DDR4 0x%X ", l_work_word); + + // TFAWMIN_HIGH = 36 + // TFAWMIN_LOW = 37, + l_spd_byte1 = l_spd[TFAWMIN_HIGH]; + l_spd_byte2 = l_spd[TFAWMIN_LOW]; + l_work_word = (l_spd_byte1 << 8) | l_spd_byte2; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TFAWMIN, i_dimm, l_work_word), + "Failed to set ATTR_CEN_SPD_TFAWMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_TFAWMIN 0x%X ", l_work_word); + + // TRRDSMIN_DDR4 = 38 + l_spd_byte1 = l_spd[TRRDSMIN_DDR4]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRRDSMIN_DDR4, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TRRDSMIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TRRDSMIN_DDR4 0x%X ", l_spd_byte1); + + // TRRDLMIN_DDR4 = 39 + l_spd_byte1 = l_spd[TRRDLMIN_DDR4]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TRRDLMIN_DDR4, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TRRDLMIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TRRDLMIN_DDR4 0x%X ", l_spd_byte1); + + // TCCDLMIN_DDR4 = 40,ATTR_CEN_SPD_TCCDLMIN_DDR4 + l_spd_byte1 = l_spd[TCCDLMIN_DDR4]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_TCCDLMIN_DDR4, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_TCCDLMIN_DDR4" ); + FAPI_INF("Set ATTR_CEN_SPD_TCCDLMIN_DDR4 0x%X ", l_spd_byte1); + + // FINE_OFFSET_TRCMIN = 120 + l_spd_byte1 = l_spd[FINE_OFFSET_TRCMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_FINE_OFFSET_TRCMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_FINE_OFFSET_TRCMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_FINE_OFFSET_TRCMIN 0x%X ", l_spd_byte1); + + // FINE_OFFSET_TRPMIN = 121 + l_spd_byte1 = l_spd[FINE_OFFSET_TRPMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_FINE_OFFSET_TRPMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_FINE_OFFSET_TRPMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_FINE_OFFSET_TRPMIN 0x%X ", l_spd_byte1); + + // FINE_OFFSET_TRCDMIN = 122 + l_spd_byte1 = l_spd[FINE_OFFSET_TRCDMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_FINE_OFFSET_TRCDMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_FINE_OFFSET_TRCDMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_FINE_OFFSET_TRCDMIN 0x%X ", l_spd_byte1); + + // FINE_OFFSET_TAAMIN = 123 + l_spd_byte1 = l_spd[FINE_OFFSET_TAAMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_FINE_OFFSET_TAAMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_FINE_OFFSET_TAAMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_FINE_OFFSET_TAAMIN 0x%X ", l_spd_byte1); + + // FINE_OFFSET_TCKMAX_DDR4 = 124 + // FINE_OFFSET_TCKMIN = 125 + l_spd_byte1 = l_spd[FINE_OFFSET_TCKMIN]; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_FINE_OFFSET_TCKMIN, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_FINE_OFFSET_TCKMIN" ); + FAPI_INF("Set ATTR_CEN_SPD_FINE_OFFSET_TCKMIN 0x%X ", l_spd_byte1); + + l_spd_byte1 = l_spd[ADDR_MAP_REG_TO_DRAM]; + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_ADDR_MAP_REG_TO_DRAM, i_dimm, l_spd_byte1), + "Failed to set ATTR_CEN_SPD_ADDR_MAP_REG_TO_DRAM"); + FAPI_INF("Set ATTR_CEN_SPD_ADDR_MAP_REG_TO_DRAM 0x%X ", l_spd_byte1); + + // Reset ATTR_CEN_SPD_BAD_DQ_DATA + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_CEN_SPD_BAD_DQ_DATA, i_dimm, l_dqData), + "Failed to set ATTR_CEN_SPD_BAD_DQ_DATA" ); + FAPI_INF("Set ATTR_CEN_SPD_BAD_DQ_DATA 0x%X ", l_dqData); + + } + else + { + FAPI_INF("DDR3 detected, skipping SPD collection. Contact lwmulkey@us.ibm.com for more info."); + } + } +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.H new file mode 100644 index 000000000..c36199888 --- /dev/null +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9c_mss_attr_cleanup.H +/// @brief Decode SPD and set attrs +/// +// *HWP HWP Owner: Thomas Sand <trsand@us.ibm.com> +// *HWP FW Owner: Luke Mulkey <lwmulkey@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __P9C_MSS_ATTR_CLEANUP__ +#define __P9C_MSS_ATTR_CLEANUP__ + +#include <fapi2.H> + +// Lx version 1 parsing/extraction constants +// section offsets +constexpr uint8_t Lx_V1_R_OFFSET_TO_F0S = 24; +constexpr uint8_t Lx_V1_R_OFFSET_TO_F1S = 82; +constexpr uint8_t Lx_V1_R_OFFSET_TO_F2S = 140; +constexpr uint8_t Lx_V1_R_OFFSET_TO_F3S = 198; + +typedef fapi2::ReturnCode (*p9c_mss_attr_cleanup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&); + +extern "C" +{ + +/// +/// @brief Programatic over-rides related to effective config +/// @param[in] i_target, the controller (e.g., MCS) +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode p9c_mss_attr_cleanup( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ); + +} + +#endif diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.mk b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.mk new file mode 100644 index 000000000..cee26c08e --- /dev/null +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.mk @@ -0,0 +1,29 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +-include 00common.mk + +PROCEDURE=p9c_mss_attr_cleanup +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml index f14a8d373..20803b485 100644 --- a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml +++ b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml @@ -40,7 +40,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>DDR3 = 0x0b, DDR4 = 0x0c</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -53,7 +53,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, SO_DIMM=0x03, LRDIMM = 0x0b, INVALID = 0xff</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -66,7 +66,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>NO = 0x0, YES = 0x1</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -89,7 +89,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs D256MB = 0x00, D512Mb = 0x01, D1GB = 0x02, D2GB = 0x03, D4GB = 0x04, D8GB = 0x05, D16GB = 0x06, D32GB=0x07 </enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -107,7 +107,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03, B4 = 0x04, UNKNOWN = 0xff</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -121,7 +121,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <enum>R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03, R16 = 0x04, R17 = 0x05, R18 = 0x06 </enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -133,7 +133,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>C9 = 0x00, C10 = 0x01, C11 = 0x02, C12 = 0x03</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -157,7 +157,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs OP1_2V = 0x08, END1_2V = 0x10 </enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -170,7 +170,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>R1 = 0x00, R2 = 0x01, R4 = 0x03, RX = 0xFF</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -183,7 +183,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>W4 = 0x00, W8 = 0x01, W16 = 0x02, W32 = 0x03</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -201,7 +201,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs W8 = 0x00, W16 = 0x01, W32 = 0x02, W64 = 0x03, WE8 = 0x08, WE16 = 0x09, WE32 = 0x0a, WE64 = 0x0b </enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -213,7 +213,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 18. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -253,7 +253,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs CL_5 = 0x00000002, CL_4 = 0x00000001 </enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -265,7 +265,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 24. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -277,7 +277,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 25. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -289,7 +289,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 26. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -301,7 +301,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 27, bits 3-0 and byte 28 (LSB) </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -313,7 +313,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 27, bits 7-4 and byte 29 (LSB) </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -325,7 +325,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 36, bits 3-0 and byte 37 (LSB). </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -338,7 +338,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>DLL_OFF = 0x80, RZQ7 = 0x02, RZQ6 = 0x01</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -351,7 +351,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>PASR = 0x80, ODTS = 0x08, ASR = 0x05, ETRR = 0x02, ETR = 0x01</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -364,7 +364,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>PRESENT = 0x80, ACCURACY_MASK = 0x7F</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -377,7 +377,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>STANDARD_MONOLITHIC = 0x00, NON_STANDARD = 0x01</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -390,7 +390,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>NOT_SPECIFIED = 0x00, MULTI_LOAD_STACK = 0x01, SINGLE_LOAD_STACK = 0x02</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -402,7 +402,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <enum>DIE1 = 0x00, DIE2 = 0x01, DIE3 = 0x02, DIE4 = 0x03,DIE5 = 0x04,DIE6 = 0x05,DIE7 = 0x06,DIE8 = 0x07</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -414,7 +414,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 125. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -426,7 +426,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 123. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -438,7 +438,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 122. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -450,7 +450,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 121. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -462,7 +462,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 120. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <!-- @@ -474,7 +474,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR3 SPD byte 63 bits 1-0. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -489,7 +489,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <array>57</array> - <platInit/> + <writeable/> </attribute> --> @@ -503,7 +503,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD bytes 320 (LSB) to 321. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -517,7 +517,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD byte 322. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -531,7 +531,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD bytes 323 (BCD year) to byte 324 (BCD week) (LSB). </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -545,7 +545,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD bytes 325 (LSB) to 328. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -558,7 +558,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR3 SPD bytes 126 (LSB) to 127. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -573,7 +573,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <array>18</array> - <platInit/> + <writeable/> </attribute> --> @@ -590,7 +590,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Platform support must call an Accessor HWP. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -604,7 +604,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs Located in DDR4 SPD bytes 350 (LSB) to 351. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -620,7 +620,6 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs </description> <valueType>uint8</valueType> <array>80</array> - <platInit/> <writeable/> </attribute> @@ -636,6 +635,7 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <valueType>uint64</valueType> <odmVisable/> <odmChangeable/> + <writeable/> </attribute> --> @@ -650,6 +650,8 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs <odmVisable/> <odmChangeable/> <array> 2 2</array> + <platInit/> + <writeable/> </attribute> <!-- @@ -667,7 +669,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 9, bits 7-4. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -678,7 +680,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 9, bits 3-0. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -689,7 +691,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 10. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -700,7 +702,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 11. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -711,7 +713,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 17. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -722,7 +724,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 19. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -733,7 +735,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 24 (LSB) and byte 25. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -744,7 +746,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 26. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -755,7 +757,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 27. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <!-- @@ -771,7 +773,7 @@ Querying them from DDR4 DIMMs will result in an error NO_RANKS = 0x00, ODD_RANKS = 0x01 </enum> - <platInit/> + <writeable/> </attribute> --> @@ -785,7 +787,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 67. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -799,7 +801,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 68. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -813,7 +815,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 69. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -827,7 +829,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 70. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -841,7 +843,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 71. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -855,7 +857,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 72. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -869,7 +871,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 73. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -883,7 +885,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 74. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -897,7 +899,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 75. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -911,7 +913,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 76. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -925,7 +927,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 77. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -939,7 +941,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 78. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -953,7 +955,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 79. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -967,7 +969,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 80. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -981,7 +983,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 81. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -995,7 +997,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 82. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1009,7 +1011,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 83. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1023,7 +1025,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 84. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1037,7 +1039,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 85. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1051,7 +1053,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 86. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1065,7 +1067,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 87. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1079,7 +1081,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 88. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1093,7 +1095,7 @@ Querying them from DDR4 DIMMs will result in an error Located in DDR3 SPD byte 89. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1113,7 +1115,7 @@ Querying them from DDR3 DIMMs will result in an error </description> <valueType>uint8</valueType> <enum>BG0 = 0x00, BG2 = 0x01, BG4 = 0x02</enum> - <platInit/> + <writeable/> </attribute> --> @@ -1128,7 +1130,7 @@ Querying them from DDR3 DIMMs will result in an error </description> <valueType>uint8</valueType> <enum>PS125 = 0x00</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1142,7 +1144,7 @@ Querying them from DDR3 DIMMs will result in an error </description> <valueType>uint8</valueType> <enum>PS1 = 0x00</enum> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1153,7 +1155,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 19. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1164,7 +1166,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD bytes 31(MSB) bits 15-8 and SPD byte 30(LSB) 7-0. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1175,7 +1177,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD bytes 33(MSB) bits 15-8 and SPD byte 32(LSB) 7-0. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1186,7 +1188,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 35(MSB) bits 15-8 and SPD byte 34(LSB) 7-0. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1201,7 +1203,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 38 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1216,7 +1218,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 39 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <attribute> @@ -1231,7 +1233,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 40 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> <!-- @@ -1246,7 +1248,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 117 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1262,7 +1264,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 118 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1278,7 +1280,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 119 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1291,7 +1293,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 124. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1304,7 +1306,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 126(LSB) and 127(MSB). </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1320,7 +1322,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 352 </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1333,7 +1335,7 @@ Querying them from DDR3 DIMMs will result in an error Located in DDR4 SPD byte 382(LSB) and 383(MSB). </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1346,6 +1348,7 @@ Querying them from DDR3 DIMMs will result in an error <valueType>uint32</valueType> <enum>UNKNOWN = 0x3030, OLD_CDIMM = 0x3031, CURRENT = 0x3230</enum> <platInit/> + <writeable/> </attribute> <!-- @@ -1359,13 +1362,11 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only <targetType>TARGET_TYPE_DIMM</targetType> <description> Indicates number of registers used and number of rows of DRAM's on LRDIMM. - Byte 131, Bits 1-0 for # of registers used on LRDIMM. - 00 - Undefined , 01 - 1 Register , 10,11 -Reserved. Byte 131, Bits 3-2 for # of rows of DRAM's on LRDIMM 00,11- Undefined, 01- 1 Row, 10 - 2 Rows. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1373,16 +1374,14 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only <attribute> <id>ATTR_CEN_SPD_REGISTER_MANF_ID</id> <targetType>TARGET_TYPE_DIMM</targetType> - <description> Manufacturer of the memory buffer on DIMM module. - Located in DDR4 SPD bytes 133(LSB) and 134(MSB). + Located in DDR4 SPD bytes 133(LSB) and 134(MSB). </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> -<!-- <attribute> <id>ATTR_CEN_SPD_ADDR_MAP_REG_TO_DRAM</id> <targetType>TARGET_TYPE_DIMM</targetType> @@ -1390,12 +1389,10 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Address mapping from Register to DRAM and Drive strength. Located in DDR4 SPD bytes 136 and 137. Byte 136 bit 0, 0 - Standard, 1 - Mirrored. - Byte 137 has drive strength for control and command/Address. </description> - <valueType>uint32</valueType> - <platInit/> + <valueType>uint8</valueType> + <writeable/> </attribute> ---> <!-- <attribute> @@ -1406,7 +1403,20 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 138. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> +</attribute> +--> + +<!-- +<attribute> + <id>ATTR_CEN_SPD_REG_OUTPUT_DRV_STRENGTH_CA</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + Drive strength for ca outputs of the registering clock driver. + Located in DDR4 SPD bytes 137. + </description> + <valueType>uint8</valueType> + <writeable/> </attribute> --> @@ -1419,7 +1429,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 140. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1432,7 +1442,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 141. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1445,7 +1455,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 142. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1458,7 +1468,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 143. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1471,7 +1481,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 144. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1486,7 +1496,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bits 6-4 for MDQ Drive strength. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1501,7 +1511,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bits 6-4 for MDQ Drive strength. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1516,7 +1526,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bits 6-4 for MDQ Drive strength. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1532,7 +1542,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bits 5-4 for data rate between 2400 and 3200. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1545,7 +1555,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 149 bits 2-0. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1558,7 +1568,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 149 bits 5-3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1571,7 +1581,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 150 bits 2-0. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1584,7 +1594,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 150 bits 5-3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1597,7 +1607,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 151 bits 2-0. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1610,7 +1620,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Located in DDR4 SPD bytes 151 bits 5-3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1625,7 +1635,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bit 5-3 for package ranks 2 and 3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1640,7 +1650,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bit 5-3 for package ranks 2 and 3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1655,7 +1665,7 @@ The following attributes can be queried from LRDIMM type DDR4 DIMMs only Bit 5-3 for package ranks 2 and 3. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> <!-- @@ -1677,7 +1687,7 @@ that handles the DDR neutral attribute. </description> <valueType>uint8</valueType> <enum>B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03</enum> - <platInit/> + <writeable/> </attribute> --> @@ -1693,7 +1703,7 @@ that handles the DDR neutral attribute. </description> <valueType>uint8</valueType> <enum>NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04</enum> - <platInit/> + <writeable/> </attribute> --> @@ -1725,7 +1735,7 @@ that handles the DDR neutral attribute. CL_5 = 0x00000002, CL_4 = 0x00000001 </enum> - <platInit/> + <writeable/> </attribute> --> @@ -1740,7 +1750,7 @@ that handles the DDR neutral attribute. Regular HWPs must use ATTR_CEN_SPD_MODULE_REVISION_CODE. </description> <valueType>uint32</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1763,7 +1773,7 @@ that handles the DDR neutral attribute. </description> <valueType>uint8</valueType> <enum>B4 = 0x00, B8 = 0x01</enum> - <platInit/> + <writeable/> </attribute> --> @@ -1784,7 +1794,7 @@ that handles the DDR neutral attribute. OPTBD1V = 0x04, ENDTBD1V = 0x08, OPTBD2V = 0x10, ENDTBD2V = 0x20 </enum> - <platInit/> + <writeable/> </attribute> --> @@ -1819,7 +1829,7 @@ that handles the DDR neutral attribute. CL_8 = 0x00000002, CL_7 = 0x00000001 </enum> - <platInit/> + <writeable/> </attribute> --> @@ -1834,7 +1844,7 @@ that handles the DDR neutral attribute. Regular HWPs must use ATTR_CEN_SPD_MODULE_REVISION_CODE. </description> <valueType>uint8</valueType> - <platInit/> + <writeable/> </attribute> --> @@ -1862,6 +1872,7 @@ The following attributes are from Centaur VPD. </enum> <platInit/> <array> 2 2</array> + <writeable/> </attribute> <!-- Attributes added to support the VPD which was formally using the EFF settings --> @@ -1878,6 +1889,7 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> + <writeable/> </attribute> <attribute> @@ -1892,6 +1904,7 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> + <writeable/> </attribute> <attribute> @@ -1909,6 +1922,7 @@ This Attribute is to be interpreted as an Integer </description> <odmVisable/> <odmChangeable/> <array> 2 2</array> + <writeable/> </attribute> <attribute> @@ -1925,6 +1939,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> + <writeable/> </attribute> <attribute> @@ -1941,6 +1956,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> + <writeable/> </attribute> <attribute> @@ -1958,6 +1974,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2 2 4</array> + <writeable/> </attribute> <attribute> @@ -1976,6 +1993,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -1997,6 +2015,7 @@ Decode: (R for Range V for Value, blank for unused) <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2015,6 +2034,7 @@ OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2032,6 +2052,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2049,6 +2070,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2066,6 +2088,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2083,6 +2106,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2100,6 +2124,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2121,6 +2146,7 @@ SLEW_MAXV_NS = 7</enum> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2142,6 +2168,7 @@ SLEW_MAXV_NS = 7</enum> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2163,6 +2190,7 @@ SLEW_MAXV_NS = 7</enum> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2185,6 +2213,7 @@ SLEW_MAXV_NS = 7 <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2207,6 +2236,7 @@ SLEW_MAXV_NS = 7 <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2224,6 +2254,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2235,6 +2266,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2246,6 +2278,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2257,6 +2290,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2268,6 +2302,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2279,6 +2314,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2290,6 +2326,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2301,6 +2338,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2312,6 +2350,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2323,6 +2362,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2334,6 +2374,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2345,6 +2386,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2356,6 +2398,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2367,6 +2410,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2378,6 +2422,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2389,6 +2434,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2400,6 +2446,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2411,6 +2458,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2422,6 +2470,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2433,6 +2482,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2444,6 +2494,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2455,6 +2506,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2466,6 +2518,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2477,6 +2530,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2488,6 +2542,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2499,6 +2554,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2510,6 +2566,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2521,6 +2578,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2532,6 +2590,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2543,6 +2602,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2554,6 +2614,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2565,6 +2626,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2576,6 +2638,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2587,6 +2650,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2598,6 +2662,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2609,6 +2674,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2620,6 +2686,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2631,6 +2698,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2642,6 +2710,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2653,6 +2722,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2664,6 +2734,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2675,6 +2746,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2686,6 +2758,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2697,6 +2770,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2708,6 +2782,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2719,6 +2794,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2730,6 +2806,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2741,6 +2818,7 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> <attribute> @@ -2752,9 +2830,9 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> -<!-- <attribute> <id>ATTR_CEN_VPD_PERIODIC_MEMCAL_MODE_OPTIONS</id> <targetType>TARGET_TYPE_MBA</targetType> @@ -2765,8 +2843,8 @@ This Attribute is to be interpreted as an Integer</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> ---> <attribute> <id>ATTR_CEN_VPD_CKE_PRI_MAP</id> @@ -2776,6 +2854,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2785,6 +2864,7 @@ This Attribute is to be interpreted as an Integer</description> <valueType>uint64</valueType> <platInit/> <odmVisable/> + <writeable/> </attribute> <attribute> @@ -2795,6 +2875,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2805,6 +2886,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2815,6 +2897,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2825,6 +2908,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2835,6 +2919,7 @@ This Attribute is to be interpreted as an Integer</description> <platInit/> <odmVisable/> <array>2</array> + <writeable/> </attribute> <attribute> @@ -2854,6 +2939,7 @@ Comes from the VPD MW Keyword</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> + <writeable/> </attribute> <attribute> @@ -2873,6 +2959,7 @@ Comes from the VPD MW Keyword</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> + <writeable/> </attribute> <attribute> @@ -2884,6 +2971,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <odmChangeable/> + <writeable/> </attribute> <attribute> @@ -2894,6 +2982,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2904,6 +2993,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2914,6 +3004,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -2924,6 +3015,7 @@ Comes from the VPD MW Keyword</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <!-- @@ -2937,10 +3029,10 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint32</valueType> <writeable/> <persistent/> + <writeable/> </attribute> --> -<!-- <attribute> <id>ATTR_CEN_VPD_MT_VERSION_BYTE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2948,10 +3040,9 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> - </attribute> ---> + <writeable/> +</attribute> -<!-- <attribute> <id>ATTR_CEN_VPD_MR_VERSION_BYTE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2959,10 +3050,9 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> - </attribute> ---> + <writeable/> +</attribute> -<!-- <attribute> <id>ATTR_CEN_VPD_MR_DATA_CONTROL_BYTE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2970,10 +3060,9 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> - </attribute> ---> + <writeable/> +</attribute> -<!-- <attribute> <id>ATTR_CEN_VPD_MT_DATA_CONTROL_BYTE</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> @@ -2981,8 +3070,8 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint8</valueType> <platInit/> <odmVisable/> - </attribute> ---> + <writeable/> +</attribute> <!-- <attribute> @@ -2992,7 +3081,8 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - </attribute> + <writeable/> +</attribute> --> <!-- @@ -3003,7 +3093,8 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - </attribute> + <writeable/> +</attribute> --> <!-- @@ -3014,7 +3105,8 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <valueType>uint32</valueType> <platInit/> <odmVisable/> - </attribute> + <writeable/> +</attribute> --> @@ -3029,6 +3121,7 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> </description> <valueType>uint8</valueType> <platInit/> + <writeable/> </attribute> --> @@ -3046,6 +3139,7 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> A = 0x00, B = 0x01, C = 0x02, D = 0x03, E = 0x04, F = 0x05, G = 0x06, H = 0x07, J = 0x08, K = 0x09, L = 0x0a, M = 0x0b, N = 0x0c, P = 0x0d, R = 0x0e, T = 0x0f, U = 0x10, V = 0x11, W = 0x12, Y = 0x13, AA = 0x14, AB = 0x15, AC = 0x16, AD = 0x17, AE = 0x18, AF = 0x19, AG = 0x1a, AH = 0x1b, AJ = 0x1c, AK = 0x1d, AL = 0x1e, AM = 0x20, AN = 0x21, AP = 0x22, AR = 0x23, AT = 0x24, AU = 0x25, AV = 0x26, AW = 0x27, AY = 0x28, BA = 0x29, BB = 0x2a, BC = 0x2b, BD = 0x2c, BE = 0x2d, BF = 0x2e, BG = 0x2f, BH = 0x30, BJ = 0x31, BK = 0x32, BL = 0x33, BM = 0x34, BN = 0x35, BP = 0x36, BR = 0x37, BT = 0x38, BU = 0x39, BV = 0x3a, BW = 0x3b, BY = 0x3c, CA = 0x3d, CB = 0x3e, ZZ = 0x3f </enum> <platInit/> + <writeable/> </attribute> --> @@ -3057,7 +3151,8 @@ Data will be pulled from backplane VPD if IS DIMMs present.</description> <enum>NONE = 0x00, SLOWEXIT_CAPABLE = 0x01, FASTEXIT_CAPABLE = 0x02, FASTSLOW_CAPABLE = 0x03</enum> <platInit/> <odmVisable/> - </attribute> + <writeable/> +</attribute> <attribute> @@ -3072,10 +3167,10 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> <array> 2 2</array> + <writeable/> </attribute> -<!-- <attribute> <id>ATTR_CEN_VPD_RD_CTR_WINDAGE_OFFSET</id> <targetType>TARGET_TYPE_MBA</targetType> @@ -3088,19 +3183,17 @@ firmware notes: none</description> <odmVisable/> <odmChangeable/> <array> 2</array> + <writeable/> </attribute> ---> - -<!-- <attribute> <id>ATTR_CEN_ISDIMM_MBVPD_INDEX</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>VPD index for associated chip's memory buffer VPD</description> <valueType>uint8</valueType> <platInit/> + <writeable/> </attribute> ---> <attribute> <id>ATTR_CEN_CDIMM_VPD_MASTER_TOTAL_POWER_SLOPE</id> @@ -3110,6 +3203,7 @@ firmware notes: none</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -3120,6 +3214,7 @@ firmware notes: none</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -3130,6 +3225,7 @@ firmware notes: none</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> <attribute> @@ -3140,6 +3236,7 @@ firmware notes: none</description> <platInit/> <odmVisable/> <persistRuntime/> + <writeable/> </attribute> </attributes> |
