Implement cen_switch_rec_attn and proc_switch_rec_attn

Change-Id: Iae01facf7e3647389c7565925133f8d729c22ff7
RTC:59015 59014
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2922
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

10 files changed, 804 insertions, 103 deletions

diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index 4d0a619c1..ed4f7abff 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -164,6 +164,10 @@ enum istepReasonCode
     ISTEP_GET_SLW_OUTPUT_BUFFER_FAILED          = ISTEP_COMP_ID | 0x27,
     ISTEP_GET_SLW_REALMEM_FAILED                = ISTEP_COMP_ID | 0x28,
 
+    ISTEP_CEN_REC_ATTN_FAILED                   = ISTEP_COMP_ID | 0x29,
+    ISTEP_PROC_REC_ATTN_FAILED                  = ISTEP_COMP_ID | 0x2A,
+
+
 };  // end ISTEP
 
 }
diff --git a/src/usr/hwpf/hwp/core_activate/core_activate.C b/src/usr/hwpf/hwp/core_activate/core_activate.C
index e91845354..c840bc88d 100644
--- a/src/usr/hwpf/hwp/core_activate/core_activate.C
+++ b/src/usr/hwpf/hwp/core_activate/core_activate.C
@@ -43,6 +43,7 @@
 #include    <initservice/istepdispatcherif.H>
 
 #include    <hwpisteperror.H>
+#include    <errl/errludtarget.H>
 
 //  targeting support
 #include    <targeting/common/commontargeting.H>
@@ -65,10 +66,13 @@
 #include    "p8_set_pore_bar.H"
 // #include    "host_activate_slave_cores/host_activate_slave_cores.H"
 #include    "proc_switch_cfsim.H"
+#include    "proc_switch_rec_attn.H"
+#include    "cen_switch_rec_attn.H"
 
 namespace   CORE_ACTIVATE
 {
 
+using   namespace   ERRORLOG;
 using   namespace   TARGETING;
 using   namespace   fapi;
 using   namespace   ISTEP;
@@ -313,11 +317,13 @@ void*    call_host_activate_slave_cores( void    *io_pArgs )
         TARGETING::TargetHandleList l_procTargetList;
         getAllChips(l_procTargetList, TYPE_PROC);
 
-        // loop thru all the cpu's
-        for ( uint8_t l_procNum=0; l_procNum < l_procTargetList.size(); l_procNum++)
+        // loop thru all the proc's
+        for ( TargetHandleList::iterator l_iter = l_procTargetList.begin();
+              l_iter != l_procTargetList.end();
+              ++l_iter )
         {
             //  make a local copy of the CPU target
-            TARGETING::Target*  l_proc_target = l_procTargetList[l_procNum];
+            TARGETING::Target*  l_proc_target = (*l_iter) ;
 
             //  dump physical path to target
             EntityPath l_path;
@@ -325,10 +331,10 @@ void*    call_host_activate_slave_cores( void    *io_pArgs )
             l_path.dump();
 
             // cast OUR type of target to a FAPI type of target.
-            fapi::Target l_fapi_proc_target(
-                                           TARGET_TYPE_PROC_CHIP,
-                                           reinterpret_cast<void *>
-                                           (const_cast<TARGETING::Target*>(l_proc_target)) );
+            fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP,
+                                             reinterpret_cast<void *>
+                                               (const_cast<TARGETING::Target*>
+                                                 (l_proc_target)) );
 
             //  reset pore bar notes:
             //  A mem_size of 0 means to ignore the image address
@@ -350,8 +356,10 @@ void*    call_host_activate_slave_cores( void    *io_pArgs )
                  * @reasoncode      ISTEP_RESET_PORE_BARS_FAILED
                  * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
                  * @moduleid        ISTEP_HOST_ACTIVATE_SLAVE_CORES
-                 * @userdata1       0
-                 * @userdata2       0
+                 * @userdata1       bytes 0-1: plid identifying first error
+                 *                  bytes 2-3: reason code of first error
+                 * @userdata2       bytes 0-1: total number of elogs included
+                 *                  bytes 2-3: N/A
                  * @devdesc         call to set_pore_bars failed.
                  *                  see error identified by the plid in
                  *                  user data field.
@@ -399,8 +407,7 @@ void*    call_host_ipl_complete( void    *io_pArgs )
                "call_host_ipl_complete entry" );
     do
     {
-        // We only need to do this to the master Processor.
-
+        // We only need to run cfsim on the master Processor.
         TARGETING::Target * l_masterProc =   NULL;
         (void)TARGETING::targetService().masterProcChipTargetHandle( l_masterProc );
 
@@ -415,6 +422,7 @@ void*    call_host_ipl_complete( void    *io_pArgs )
         l_path  =   l_masterProc->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
+
         //  call proc_switch_cfsim
         FAPI_INVOKE_HWP(l_err, proc_switch_cfsim, l_fapi_proc_target,
                         true, // RESET
@@ -437,6 +445,148 @@ void*    call_host_ipl_complete( void    *io_pArgs )
                        "SUCCESS: proc_switch_cfsim HWP( )" );
         }
 
+
+        //  Loop through all the centaurs in the system
+        //  and run cen_switch_rec_attn
+        TARGETING::TargetHandleList l_memTargetList;
+        getAllChips(l_memTargetList, TYPE_MEMBUF );
+
+        for ( TargetHandleList::iterator l_iter = l_memTargetList.begin();
+              l_iter != l_memTargetList.end();
+              ++l_iter )
+        {
+            TARGETING::Target * l_memChip  =   (*l_iter) ;
+
+            //  dump physical path to target
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                       "Running cen_switch_rec_attn HWP on ...");
+            EntityPath l_path;
+            l_path  =   l_memChip->getAttr<ATTR_PHYS_PATH>();
+            l_path.dump();
+
+
+            // cast OUR type of target to a FAPI type of target.
+            fapi::Target l_fapi_centaur_target( TARGET_TYPE_MEMBUF_CHIP,
+                                                l_memChip );
+            FAPI_INVOKE_HWP( l_err,
+                             cen_switch_rec_attn,
+                             l_fapi_centaur_target );
+            if (l_err)
+            {
+                // log error for this centaur and continue
+
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                          "ERROR 0x%.8X: cen_switch_rec_attn HWP( )",
+                          l_err->reasonCode() );
+
+                // Add all the details for this centaur
+                ErrlUserDetailsTarget myDetails(l_memChip);
+
+                // capture the target data in the elog
+                myDetails.addToLog(l_err);
+
+                /*@
+                 * @errortype
+                 * @reasoncode      ISTEP_CEN_REC_ATTN_FAILED
+                 * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
+                 * @moduleid        ISTEP_HOST_IPL_COMPLETE
+                 * @userdata1       bytes 0-1: plid identifying first error
+                 *                  bytes 2-3: reason code of first error
+                 * @userdata2       bytes 0-1: total number of elogs included
+                 *                  bytes 2-3: N/A
+                 * @devdesc         call to cen_switch_attn failed.
+                 *                  see
+                 *                  error identified by the plid in user data
+                 *                  field.
+                 */
+                l_stepError.addErrorDetails( ISTEP_CEN_REC_ATTN_FAILED,
+                                             ISTEP_HOST_IPL_COMPLETE,
+                                             l_err );
+
+                errlCommit( l_err, HWPF_COMP_ID );
+            }
+            else
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "SUCCESS: cen_switch_rec_attn HWP( )" );
+            }
+        }   // endfor
+
+
+        //  Loop through all the mcs in the system
+        //  and run proc_switch_rec_attn
+        TARGETING::TargetHandleList l_mcsTargetList;
+        getAllChiplets(l_mcsTargetList, TYPE_MCS);
+
+        for ( TargetHandleList::iterator l_iter = l_mcsTargetList.begin();
+            l_iter != l_mcsTargetList.end();
+            ++l_iter )
+        {
+            TARGETING::Target * l_mcsChiplet  =   (*l_iter) ;
+
+            //  dump physical path to target
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                        "Running proc_switch_rec_attn HWP on ...");
+            EntityPath l_path;
+            l_path  =   l_mcsChiplet->getAttr<ATTR_PHYS_PATH>();
+            l_path.dump();
+
+            // cast OUR type of target to a FAPI type of target.
+            fapi::Target l_fapi_mcs_target( TARGET_TYPE_MCS_CHIPLET,
+                                            l_mcsChiplet );
+
+            FAPI_INVOKE_HWP( l_err,
+                             proc_switch_rec_attn,
+                             l_fapi_mcs_target );
+            if (l_err)
+            {
+                // log error for this mcs and continue
+
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                          "ERROR 0x%.8X: proc_switch_rec_attn HWP( )",
+                          l_err->reasonCode() );
+
+                // Add all the details for this proc
+                ErrlUserDetailsTarget myDetails(l_mcsChiplet);
+
+                // capture the target data in the elog
+                myDetails.addToLog(l_err);
+
+                /*@
+                 * @errortype
+                 * @reasoncode      ISTEP_PROC_REC_ATTN_FAILED
+                 * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
+                 * @moduleid        ISTEP_HOST_IPL_COMPLETE
+                 * @userdata1       bytes 0-1: plid identifying first error
+                 *                  bytes 2-3: reason code of first error
+                 * @userdata2       bytes 0-1: total number of elogs included
+                 *                  bytes 2-3: N/A
+                 * @devdesc         call to cen_switch_attn failed.
+                 *                  see
+                 *                  error identified by the plid in user data
+                 *                  field.
+                 */
+                l_stepError.addErrorDetails( ISTEP_PROC_REC_ATTN_FAILED,
+                                             ISTEP_HOST_IPL_COMPLETE,
+                                             l_err );
+
+                errlCommit( l_err, HWPF_COMP_ID );
+            }
+            else
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "SUCCESS: proc_switch_rec_attn HWP( )" );
+            }
+
+        }   //  endfor
+
+
+        // check if any errors were collected above.  If so, drop out here.
+        if ( !l_stepError.isNull() )
+        {
+            break;
+        }
+
         // Sync attributes to Fsp
         l_err = syncAllAttributesToFsp();
 
@@ -454,6 +604,8 @@ void*    call_host_ipl_complete( void    *io_pArgs )
 
     if( l_err )
     {
+        // collect and log any remaining errors
+
         /*@
          * @errortype
          * @reasoncode      ISTEP_CORE_ACTIVATE_FAILED
@@ -474,10 +626,11 @@ void*    call_host_ipl_complete( void    *io_pArgs )
         errlCommit( l_err, HWPF_COMP_ID );
     }
 
+
+
     TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_host_ipl_complete exit ");
 
-
     // end task, returning any errorlogs to IStepDisp
     return l_stepError.getErrorHandle();
 }
diff --git a/src/usr/hwpf/hwp/core_activate/makefile b/src/usr/hwpf/hwp/core_activate/makefile
index 686ef6649..334ca1075 100644
--- a/src/usr/hwpf/hwp/core_activate/makefile
+++ b/src/usr/hwpf/hwp/core_activate/makefile
@@ -1,25 +1,25 @@
-#   IBM_PROLOG_BEGIN_TAG
-#  This is an automatically generated prolog.
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
 #
-#  $Source: src/usr/hwpf/hwp/core_activate/makefile $
+# $Source: src/usr/hwpf/hwp/core_activate/makefile $
 #
-#  IBM CONFIDENTIAL
+# IBM CONFIDENTIAL
 #
-#  COPYRIGHT International Business Machines Corp. 2012
+# COPYRIGHT International Business Machines Corp. 2012,2013
 #
-#  p1
+# p1
 #
-#  Object Code Only (OCO) source materials
-#  Licensed Internal Code Source Materials
-#  IBM HostBoot Licensed Internal Code
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
 #
-#  The source code for this program is not published or other-
-#  wise divested of its trade secrets, irrespective of what has
-#  been deposited with the U.S. Copyright Office.
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
 #
-#  Origin: 30
+# Origin: 30
 #
-#  IBM_PROLOG_END_TAG
+# IBM_PROLOG_END_TAG
 ROOTPATH = ../../../../..
 
 MODULE = core_activate
@@ -47,13 +47,16 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim
 ##  proc_set_pore_bar is used by multiple isteps, so it should be in its own
 ##  "utility" library
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/switch_rec_attn
 
 ##  NOTE: add new object files when you add a new HWP
 OBJS =  core_activate.o \
         proc_prep_master_winkle.o   \
         proc_sbe_ffdc.o             \
-        proc_stop_deadman_timer.o \
-        proc_switch_cfsim.o
+        proc_stop_deadman_timer.o   \
+        proc_switch_cfsim.o         \
+        proc_switch_rec_attn.o      \
+        cen_switch_rec_attn.o
 
 
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
@@ -62,6 +65,7 @@ OBJS =  core_activate.o \
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/switch_rec_attn
 
 
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C
new file mode 100644
index 000000000..b5c1c12cd
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C
@@ -0,0 +1,113 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: cen_switch_rec_attn.C,v 1.2 2012/12/13 22:54:32 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : cen_switch_rec_attn
+// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host.
+// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
+// #! ADDITIONAL COMMENTS : See inline comments below.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include <cen_scom_addresses.H>
+#include <cen_switch_rec_attn.H>
+
+//  Constants
+const uint8_t RECOV_ERR_IPOLL_MASK_BIT = 5;
+
+extern "C" {
+
+using namespace fapi;
+
+fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target)
+{
+    // Target is centaur
+
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase scom_data(64);
+
+
+    FAPI_INF("********* cen_switch_rec_attn start *********");
+    do
+    {
+
+        // Clear bit 5 in the IPOLL Mask Register 0x01020013 to unmask the recoverable errors going to FSI and DMI.
+        // Note: In Centaur the outputs of the ITR Macro go to both the FSI and to the DMI.
+        //       The "HostBridge" mentioned in the P8 Pervasive Workbook is NOT the DMI path.
+        //       In Centaur the IPOLL Mask bits 0-3 to not do anything.
+        //       In Centaur the IPOLL Mask bits 4-7 controll signals going to BOTH FSI and DMI.
+        FAPI_DBG("Writing IPOLL Mask Register 0x01020013 to clear bit 5 (to unmask recoverable errors) ...");
+        rc = fapiGetScom( i_target, TP_IPOLL_MSK_0x01020013, scom_data);
+        if ( rc )
+        {
+            FAPI_ERR("Error reading Interrupt IPOLL Mask Reg 0x01020013.");
+            break;
+        }
+        rc_ecmd |= scom_data.clearBit(RECOV_ERR_IPOLL_MASK_BIT);
+        if (rc_ecmd)
+        {
+            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Interrupt IPOLL Mask Register.",  rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+        rc = fapiPutScom( i_target, TP_IPOLL_MSK_0x01020013, scom_data);
+        if (rc)
+        {
+            FAPI_ERR("Error writing Interrupt IPOLL Mask Reg 0x01020013.");
+            break;
+        }
+
+
+    } while(0);
+
+
+    FAPI_INF("********* cen_switch_rec_attn complete *********");
+    return rc;
+}
+
+} //end extern C
+
+
+
+/*
+*************** Do not edit this area ***************
+This section is automatically updated by CVS when you check in this file.
+Be sure to create CVS comments when you commit so that they can be included here.
+$Log: cen_switch_rec_attn.C,v $
+Revision 1.2  2012/12/13 22:54:32  mfred
+Update to remove unneeded commands and unmask recoverable path to FSI.
+
+Revision 1.1  2012/12/10 22:39:02  mfred
+Adding new procedure cen_switch_rec_attn.
+
+
+*/
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H
new file mode 100644
index 000000000..5139db96f
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: cen_switch_rec_attn.H,v 1.1 2012/12/10 22:39:06 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : cen_switch_rec_attn.H
+// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host.
+// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
+//
+// Header file for cen_switch_rec_attn.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.0    | mfred    | 05/30/12| Initial creation
+
+#ifndef CEN_SWITCH_REC_ATTNHWPB_H_
+#define CEN_SWITCH_REC_ATTNHWPB_H_
+
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*cen_switch_rec_attn_FP_t)(const fapi::Target& i_target);
+
+extern "C"
+{
+    // Target is centaur
+
+/**
+ * @brief cen_switch_rec_attn procedure.  The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host.
+ *
+ * @param[in]  i_target  Reference to centaur target
+ *
+ * @return ReturnCode
+ */
+
+    fapi::ReturnCode cen_switch_rec_attn(const fapi::Target& i_target);
+    // Target is centaur
+
+} // extern "C"
+
+#endif // CEN_SWITCH_REC_ATTNHWPB_H_
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
new file mode 100644
index 000000000..c2f483adc
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
@@ -0,0 +1,188 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// -*- mode: C++; c-file-style: "linux";  -*-
+// $Id: proc_switch_rec_attn.C,v 1.1 2012/12/10 20:38:04 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_rec_attn.C,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_switch_rec_attn.C
+// *! DESCRIPTION : The purpose of this procedure is to mask Centaur recoverable attentions from the host
+// *!               (At this point in the IPL process those attentions should be routed to the FSP.)
+// *!
+// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include "p8_scom_addresses.H"
+#include "proc_switch_rec_attn.H"
+#include <fapi.H>
+
+
+using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// MCS MCI FIR bit/field definitions
+const uint8_t MCI_CENTAUR_CHECKSTOP_BIT  = 12;
+const uint8_t MCI_CENTAUR_RECOV_ERR_BIT  = 15;
+const uint8_t MCI_CENTAUR_SPEC_ATTN_BIT  = 16;
+const uint8_t MCI_CENTAUR_MAINT_COMP_BIT = 17;
+
+
+//------------------------------------------------------------------------------
+// Function definition
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+    //------------------------------------------------------------------------------
+    // function:  mask Centaur recoverable attentions from the host
+    //
+    // parameters: i_target       =>   MCS chiplet of processor chip
+    // returns: FAPI_RC_SUCCESS if operation was successful, else error
+    //------------------------------------------------------------------------------
+    fapi::ReturnCode proc_switch_rec_attn(const fapi::Target & i_target)
+    {
+        // data buffer to hold register values
+        ecmdDataBufferBase scom_data(64);
+
+        // return codes
+        uint32_t rc_ecmd = 0;
+        fapi::ReturnCode rc;
+
+
+
+        // mark function entry
+        FAPI_INF("********* Starting proc_switch_rec_attn *********");
+        do
+        {
+
+            // Mask the following FIR bits that came over from Centaur
+            // MCS_MCIFIR(12,15,16,17)
+            // The FIR bits are in the MCS MCIFIR register (02011840 is the first instance)
+            // The FIR masks are in the MCS MCIFIRMASK reg (02011843 is the first instance)
+            FAPI_INF("Mask OFF the MCI FIR bits 12,15,16,17 coming from Centaur.\n");
+            rc_ecmd |= scom_data.flushTo0();
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_CHECKSTOP_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_RECOV_ERR_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_SPEC_ATTN_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_MAINT_COMP_BIT);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up data buffer to mask the MCI FIR bits", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, MCS_MCIFIRMASK_0x02011843, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiPutScom error (MCS_MCIFIRMASK_0x02011843)");
+                break;
+            }
+
+
+            // Marc Gollub also suggested that the action bits for these signals should be set to recoverable attention (A0=0, A1=1)
+            // The action0 bits are in the MCS MCIFIRACT0 reg (02011846 is the first instance)
+            // The action1 bits are in the MCS MCIFIRACT1 reg (02011847 is the first instance)
+            FAPI_INF("Set MCS MCI ACTION0 bits 12,15,16,17 to zero in MCS_MCIFIRACT0_0x02011846.\n");
+            rc = fapiGetScom(i_target, MCS_MCIFIRACT0_0x02011846, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiGetScom error (MCS_MCIFIRACT0_0x02011846)");
+                break;
+            }
+            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_CHECKSTOP_BIT);
+            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_RECOV_ERR_BIT);
+            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_SPEC_ATTN_BIT);
+            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_MAINT_COMP_BIT);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up data buffer to clear action bits in MCS_MCIFIRACT0_0x02011846", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, MCS_MCIFIRACT0_0x02011846, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiPutScom error (MCS_MCIFIRACT0_0x02011846)");
+                break;
+            }
+
+            FAPI_INF("Set MCS MCI ACTION1 bits 12,15,16,17 to one in MCS_MCIFIRACT1_0x02011847.\n");
+            rc = fapiGetScom(i_target, MCS_MCIFIRACT1_0x02011847, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiGetScom error (MCS_MCIFIRACT1_0x02011847)");
+                break;
+            }
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_CHECKSTOP_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_RECOV_ERR_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_SPEC_ATTN_BIT);
+            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_MAINT_COMP_BIT);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up data buffer to set action bits in MCS_MCIFIRACT1_0x02011847", rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(i_target, MCS_MCIFIRACT1_0x02011847, scom_data);
+            if (rc)
+            {
+                FAPI_ERR("fapiPutScom error (MCS_MCIFIRACT1_0x02011847)");
+                break;
+            }
+
+
+        } while (0); // end do
+
+        // mark function exit
+        FAPI_INF("********* proc_switch_rec_attn complete *********");
+        return rc;
+    }  // end FAPI procedure proc_switch_rec_attn
+
+} // extern "C"
+
+/*
+*************** Do not edit this area ***************
+This section is automatically updated by CVS when you check in this file.
+Be sure to create CVS comments when you commit so that they can be included here.
+$Log: proc_switch_rec_attn.C,v $
+Revision 1.1  2012/12/10 20:38:04  mfred
+Committing new procedure proc_switch_rec_attn.
+
+
+
+*/
+
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H
new file mode 100644
index 000000000..5883f3869
--- /dev/null
+++ b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H
@@ -0,0 +1,75 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_switch_rec_attn.H,v 1.1 2012/12/10 20:38:07 mfred Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_rec_attn.H,v $
+//------------------------------------------------------------------------------
+// *|
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *|
+// *! TITLE       : proc_switch_rec_attn.H
+// *! DESCRIPTION : The purpose of this procedure is to mask Centaur recoverable attentions from the host
+// *!               (At this point in the IPL process those attentions should be routed to the FSP.)
+// *!
+// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef _PROC_SWITCH_REC_ATTN_H_
+#define _PROC_SWITCH_REC_ATTN_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode (*proc_switch_rec_attn_FP_t)(const fapi::Target &);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+/**
+ * @brief proc_switch_rec_attn procedure.  The purpose of this procedure is to mask Centaur recoverable attentions from the host.
+ *
+ * @param[in]  i_target  Reference to pu.mcs target
+ *
+ * @return ReturnCode
+ */
+
+    fapi::ReturnCode proc_switch_rec_attn(const fapi::Target & i_target);
+    // Target is pu.mcs
+
+} // extern "C"
+
+#endif // _PROC_SWITCH_REC_ATTN_H_
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 331790695..df2731cec 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.46 2012/12/19 15:31:24 gollub Exp $
+// $Id: cen_scom_addresses.H,v 1.48 2013/01/09 20:32:14 jdsloat Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.48   | jdsloat  |09-Jan-13| Fixed typos.  Excuse me.
+//  1.47   | jdsloat  |09-Jan-13| Added DQS READ Phase select regs for RP 1-3
 //  1.46   | gollub   |19-Dec-12| Added:
 //         |          |         | MCBERRPTQ
 //         |          |         | MBA_MAINT_BUFF
@@ -65,7 +67,7 @@
 //  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
 //         |          |         | Added MBSPA AND/OR MASK registers
 //  1.38   | pardeik  |31-Oct-12| Added N/M Throttling Control Register
-//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers 
+//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers
 //  1.36   | menlowuu |25-Oct-12| Added PHY port 1 disable bit registers
 //  1.35   | menlowuu |25-Oct-12| Added PHY disable bit registers
 //  1.34   | aditya   |12-Oct-12| Added MCBIST and DPHY registers
@@ -785,7 +787,7 @@ CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC0_0x02011632			, ULL(0x02011632)
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC1_0x02011633			, ULL(0x02011633) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC2_0x02011634			, ULL(0x02011634) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC3_0x02011635			, ULL(0x02011635) );
-		
+
 // Maint Write Buffer 3
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA0_0x0201163A				, ULL(0x0201163A) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA1_0x0201163B				, ULL(0x0201163B) );
@@ -842,7 +844,7 @@ CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC0_0x02011732			, ULL(0x02011732)
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC1_0x02011733			, ULL(0x02011733) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC2_0x02011734			, ULL(0x02011734) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC3_0x02011735			, ULL(0x02011735) );
-	
+
 // Maint Write Buffer 3
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA0_0x0201173A				, ULL(0x0201173A) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA1_0x0201173B				, ULL(0x0201173B) );
@@ -1069,7 +1071,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,	           ULL(0x8001087A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,	           ULL(0x80010C7A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,	           ULL(0x8001107A0301143F) );
-                                                                                       
+
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,	           ULL(0x8000007B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,	           ULL(0x8000047B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,	           ULL(0x8000087B0301143F) );
@@ -1276,6 +1278,38 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x8001080
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F , ULL(0x80010C090301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F , ULL(0x800110090301143F) );
 
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F , ULL(0x800001090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F , ULL(0x800005090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F , ULL(0x800009090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F , ULL(0x80000D090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F , ULL(0x800011090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F , ULL(0x800101090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F , ULL(0x800105090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F , ULL(0x800109090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F , ULL(0x80010D090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F , ULL(0x800111090301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F , ULL(0x800002090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F , ULL(0x800006090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F , ULL(0x80000A090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F , ULL(0x80000E090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F , ULL(0x800012090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F , ULL(0x800102090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F , ULL(0x800106090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F , ULL(0x80010A090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F , ULL(0x80010E090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F , ULL(0x800112090301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F , ULL(0x800003090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F , ULL(0x800007090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F , ULL(0x80000B090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F , ULL(0x80000F090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F , ULL(0x800013090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F , ULL(0x800103090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F , ULL(0x800107090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F , ULL(0x80010B090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F , ULL(0x80010F090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F , ULL(0x800113090301143F) );
 
 //------------------------------------------------------------------------------
 //     DQS Gate Delay Rank Pair 0
@@ -1319,7 +1353,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD1Q_0x02011782  , ULL(0x02011782) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD2Q_0x02011783  , ULL(0x02011783) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD3Q_0x02011784  , ULL(0x02011784) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD4Q_0x02011785  , ULL(0x02011785) );
-CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) ); 
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD6Q_0x02011787  , ULL(0x02011787) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD7Q_0x02011788  , ULL(0x02011788) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDQ_0x02011789   , ULL(0x02011789) );
@@ -1329,7 +1363,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A , ULL(0x0201178A) );
 //------------------------------------------------------------------------------
 
 CONST_UINT64_T( MBA01_CCS_MODEQ_0x030106a7       		, ULL(0x030106a7) );
-CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Configuration Register
 //------------------------------------------------------------------------------
@@ -1339,39 +1373,39 @@ CONST_UINT64_T( MBA01_MCBIST_MCBCFGQ_0x030106e0  		, ULL(0x030106e0) );
 //     MBS Error Map Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Memory Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) ); 
-CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) );
+CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) );
 //------------------------------------------------------------------------------
 //     MBA Fixed Data Seed Registers
 
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MCBIST_MCBFD0Q_0x030106be  		, ULL(0x030106be) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) );
 //------------------------------------------------------------------------------
 //     MBA Data Rotate Configuration Register
 
@@ -1383,7 +1417,7 @@ CONST_UINT64_T( MBA01_MCBIST_MCBDRCRQ_0x030106bd 		, ULL(0x030106bd) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_MCBIST01_MCBCMA1Q_0x02011672 		, ULL(0x02011672) );
 
-CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );      
+CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );
 CONST_UINT64_T( MBS_MCBIST01_MCBCMABQ_0x02011674 		, ULL(0x02011674) );
 //------------------------------------------------------------------------------
 //    MBA MCBIST Control Register
@@ -1394,60 +1428,60 @@ CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLQ_0x030106db		, ULL(0x030106db) );
 //    MBA MCBIST Memory Parameter Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) );
 //------------------------------------------------------------------------------
 //    MBA Address Map Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );    
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );       
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) ); 
-      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );  
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );   
-
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) );
 CONST_UINT64_T( MBA01_MCBIST_MCBAGRAQ_0x030106d6  , ULL(0x030106d6) );
 //------------------------------------------------------------------------------
 //    MBA Performance monitor  Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );  
+CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );
 //------------------------------------------------------------------------------
 //    MBA Maintenance Buffer Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );
 //------------------------------------------------------------------------------
 //    DPHY01 PC Rank Pair Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) );
 //------------------------------------------------------------------------------
 //    MCBIST Random Data Seed Registers
 
@@ -1488,6 +1522,13 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.48  2013/01/09 20:32:14  jdsloat
+
+Fixed typos.  Excuse me.
+
+Revision 1.47  2013/01/09 20:10:20  jdsloat
+Added DQS READ Phase select regs for RP 1-3
+
 Revision 1.46  2012/12/19 15:31:24  gollub
 
 Added:
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index df744ac9a..5566ba5f4 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: common_scom_addresses.H,v 1.38 2012/11/17 19:53:05 jmcgill Exp $
+// $Id: common_scom_addresses.H,v 1.40 2013/01/08 18:24:16 koenig Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -300,6 +300,7 @@ CONST_UINT64_T( I2CMS_MEMS0_STATUS_0x000A000B         , ULL(0x000A000B) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PCBMS_0x000F0000                      , ULL(0x000F0000) );
 CONST_UINT64_T( PCBMS_DEVICE_ID_0x000F000F            , ULL(0x000F000F) );
+CONST_UINT64_T( PCB_TIMEOUT_0x000F0019                , ULL(0x000F0019) );
 CONST_UINT64_T( MASTER_PCB_INT_0x000F001A             , ULL(0x000F001A) );
 CONST_UINT64_T( PRV_PIB_PCBMS_RESET_REG_0x000F001D    , ULL(0x000F001D) );
 CONST_UINT64_T( MASTER_PCB_ERR_0x000F001F             , ULL(0x000F001F) );
@@ -331,6 +332,31 @@ CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010401           , ULL(0x01010401) );
 //------------------------------------------------------------------------------
 //      TP ITR
 //------------------------------------------------------------------------------
+CONST_UINT64_T( TP_INTRPT_PRES_TYP1_0x01020000        , ULL(0x01020000) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP1_OR_0x01020001     , ULL(0x01020001) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP1_AND_0x01020002    , ULL(0x01020002) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP2_0x01020003        , ULL(0x01020003) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP2_OR_0x01020004     , ULL(0x01020004) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP2_AND_0x01020005    , ULL(0x01020005) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP3_0x01020006        , ULL(0x01020006) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP3_OR_0x01020007     , ULL(0x01020007) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP3_AND_0x01020008    , ULL(0x01020008) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP4_0x01020009        , ULL(0x01020009) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP4_OR_0x0102000A     , ULL(0x0102000A) );
+CONST_UINT64_T( TP_INTRPT_PRES_TYP4_AND_0x0102000B    , ULL(0x0102000B) );
+
+CONST_UINT64_T( TP_INTRPT_TYP_MSK_0x0102000C          , ULL(0x0102000C) );
+CONST_UINT64_T( TP_INTRPT_TYP_MSK_OR_0x0102000D       , ULL(0x0102000D) );
+CONST_UINT64_T( TP_INTRPT_TYP_MSK_AND_0x0102000E      , ULL(0x0102000E) );
+
+CONST_UINT64_T( TP_INTRPT_CONFIG_0x0102000F           , ULL(0x0102000F) );
+CONST_UINT64_T( TP_INTRPT_CONFIG_OR_0x01020010        , ULL(0x01020010) );
+CONST_UINT64_T( TP_INTRPT_CONFIG_AND_0x01020011       , ULL(0x01020011) );
+
+CONST_UINT64_T( TP_INTRPT_HOLD_0x01020012             , ULL(0x01020012) );
+CONST_UINT64_T( TP_IPOLL_MSK_0x01020013               , ULL(0x01020013) );
+CONST_UINT64_T( TP_ITR_ERR_STAT_0x01020014            , ULL(0x01020014) );
+CONST_UINT64_T( TP_OSCERR_HOLD_0x01020019             , ULL(0x01020019) );
 CONST_UINT64_T( TP_OSC_MSK_0x0102001A                 , ULL(0x0102001A) );
 
 //------------------------------------------------------------------------------
@@ -610,6 +636,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.40  2013/01/08 18:24:16  koenig
+Updates - AK
+
+Revision 1.39  2012/12/10 22:02:51  mfred
+Adding addresses for interrupt macro.
+
 Revision 1.38  2012/11/17 19:53:05  jmcgill
 add trace status registers
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 86cc62df9..295ab48fd 100644
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.125 2012/12/12 04:55:22 stillgs Exp $
+// $Id: p8_scom_addresses.H,v 1.129 2013/01/10 01:17:27 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -392,13 +392,13 @@ CONST_UINT64_T( PMC_PARAMETER_REG1_0x00062006         , ULL(0x00062006) );
 CONST_UINT64_T( PMC_STATUS_REG_0x00062009             , ULL(0x00062009) );
 CONST_UINT64_T( PMC_OCC_HEARTBEAT_REG_0x00062066      , ULL(0x00062066) );
 CONST_UINT64_T( PMC_CORE_DECONFIG_REG_0x0006200D      , ULL(0x0006200D) );
-CONST_UINT64_T( PMC_FSMSTATE_STATUS_REG_0x00062000    , ULL(0x00062020) );
+CONST_UINT64_T( PMC_FSMSTATE_STATUS_REG_0x00062020    , ULL(0x00062020) );
 CONST_UINT64_T( PMC_PORRR0_REG_0x0006208E             , ULL(0x0006208E) );
 CONST_UINT64_T( PMC_PORRR1_REG_0x0006208F             , ULL(0x0006208F) );
 CONST_UINT64_T( PMC_PORRS_REG_0x00062090              , ULL(0x00062090) );
 CONST_UINT64_T( PMC_DEEPEXIT_MASK_0x00062092          , ULL(0x00062092) );
 CONST_UINT64_T( PMC_DEEPEXIT_MASK_WAND_0x000620A0     , ULL(0x000620A0) );
-CONST_UINT64_T( PMC_DEEPEXIT_MASK_WOR_0x000620A0      , ULL(0x000620A1) );
+CONST_UINT64_T( PMC_DEEPEXIT_MASK_WOR_0x000620A1      , ULL(0x000620A1) );
 
 // SPIVID Controller
 CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040        , ULL(0x00062040) );
@@ -1491,6 +1491,16 @@ CONST_UINT64_T( EX_PERV_TCTL5_R_STAT_0x10013052       , ULL(0x10013052) );
 CONST_UINT64_T( EX_PERV_TCTL6_R_STAT_0x10013062       , ULL(0x10013062) );
 CONST_UINT64_T( EX_PERV_TCTL7_R_STAT_0x10013072       , ULL(0x10013072) );
 
+// TCTL POW Status (for each thread)
+CONST_UINT64_T( EX_PERV_TCTL0_POW_STAT_0x10013004     , ULL(0x10013004) );
+CONST_UINT64_T( EX_PERV_TCTL1_POW_STAT_0x10013014     , ULL(0x10013014) );
+CONST_UINT64_T( EX_PERV_TCTL2_POW_STAT_0x10013024     , ULL(0x10013024) );
+CONST_UINT64_T( EX_PERV_TCTL3_POW_STAT_0x10013034     , ULL(0x10013034) );
+CONST_UINT64_T( EX_PERV_TCTL4_POW_STAT_0x10013044     , ULL(0x10013044) );
+CONST_UINT64_T( EX_PERV_TCTL5_POW_STAT_0x10013054     , ULL(0x10013054) );
+CONST_UINT64_T( EX_PERV_TCTL6_POW_STAT_0x10013064     , ULL(0x10013064) );
+CONST_UINT64_T( EX_PERV_TCTL7_POW_STAT_0x10013074     , ULL(0x10013074) );
+
 // Thread Active Status
 CONST_UINT64_T( EX_PERV_THREAD_ACTIVE_0x1001310E      , ULL(0x1001310E) );
 
@@ -1791,6 +1801,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.129  2013/01/10 01:17:27  stillgs
+Fix ID line typo
+
+Revision 1.128  2013/01/09 22:04:52  stillgs
+Fix PMC_FSMSTATE_STATU_REG name with correct value to match the address
+
+Revision 1.127  2013/01/09 16:21:54  stillgs
+Fix PMC_DEEPEXIT_MASK_WOR name typo --- make name match the actual address
+
+Revision 1.126  2012/12/20 18:55:31  stillgs
+Added PC POW STATUS regs
+
 Revision 1.125  2012/12/12 04:55:22  stillgs
 Added EX PCBS Slave Configuration register