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| author | Dan Crowell <dcrowell@us.ibm.com> | 2018-01-31 16:07:05 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-02-11 13:56:34 -0500 |
| commit | 093246224655865346ec1353383f1f96f9f403d9 (patch) | |
| tree | 5c82667c134911d34452df79372eff8a2863fa2f /src | |
| parent | 6a2a94e232d808fd630214956f661b428114eaaf (diff) | |
| download | talos-hostboot-093246224655865346ec1353383f1f96f9f403d9.tar.gz talos-hostboot-093246224655865346ec1353383f1f96f9f403d9.zip | |
Set ATTR_RISK_LEVEL based on scratch reg bits
The risk level value has expanded to 2 extra bits to handle new
modified settings.
Change-Id: Ic3794066659fe5ebe82b330c9530a04f7eadee94
RTC: 187088
Backport: fips910
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53023
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/usr/initservice/mboxRegs.H | 9 | ||||
| -rwxr-xr-x | src/usr/targeting/targetservicestart.C | 23 |
2 files changed, 26 insertions, 6 deletions
diff --git a/src/include/usr/initservice/mboxRegs.H b/src/include/usr/initservice/mboxRegs.H index a5b46abb3..52cd45ea6 100644 --- a/src/include/usr/initservice/mboxRegs.H +++ b/src/include/usr/initservice/mboxRegs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -86,12 +86,13 @@ namespace SPLESS uint32_t goToRuntime :1; //1 uint32_t isMpipl :1; //2 uint32_t fspAttached :1; //3 - uint32_t reserved1 :1; //4 -- do not repurpose + uint32_t reserved :1; //4 -- do not repurpose uint32_t sbeInternalFFDC :1; //5 uint32_t overrideSecurity :1; //6 uint32_t allowAttrOverrides :1; //7 uint32_t smtMode :2; //8:9 - uint32_t reserved2 :22; //10:31 -- Available + uint32_t unused :18; //10:27 -- Available + uint32_t riskLevel :4; //28:31 } PACKED; // NOTE: Used for debug tool communication during Hostboot IPL }; @@ -124,7 +125,7 @@ namespace SPLESS { uint32_t cacheContained :1; //0 uint32_t initAllCores :1; //1 - uint32_t riskLevel :1; //2 + uint32_t oldRiskLevel :1; //2 uint32_t noBLVectors :1; //3 uint32_t mcSyncMode :1; //4 uint32_t slowPci :1; //5 diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C index a725e731a..740470a53 100755 --- a/src/usr/targeting/targetservicestart.C +++ b/src/usr/targeting/targetservicestart.C @@ -387,9 +387,28 @@ static void initializeAttributes(TargetService& i_targetService, } //Set the RISK_LEVEL ATTR based off of master Scratch regs + // Risk Level is a 4 bit value that is treated as an integer, but + // there is a legacy mode that we need to maintain support for + ATTR_RISK_LEVEL_type l_riskLevel = 0; + + // Scratch5:bit2 is legacy risk level bit for backward compatibility INITSERVICE::SPLESS::MboxScratch5_t l_scratch5; - l_scratch5.data32 = i_masterScratch[INITSERVICE::SPLESS::SCRATCH_5]; - l_pTopLevel->setAttr<ATTR_RISK_LEVEL>(l_scratch5.riskLevel); + l_scratch5.data32 = + i_masterScratch[INITSERVICE::SPLESS::SCRATCH_5]; + if( l_scratch5.oldRiskLevel ) + { + l_riskLevel = 1; + } + // Scratch3 has the real risk level + else + { + INITSERVICE::SPLESS::MboxScratch3_t l_scratch3; + l_scratch3.data32 = + i_masterScratch[INITSERVICE::SPLESS::SCRATCH_3]; + l_riskLevel = l_scratch3.riskLevel; + } + TARG_INF( "Setting RISK_LEVEL=%d", l_riskLevel ); + l_pTopLevel->setAttr<ATTR_RISK_LEVEL>(l_riskLevel); } if(i_isMpipl) |
